arch/sparc/kernel/irq_64.c

   1 /* irq.c: UltraSparc IRQ handling/init/registry.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   5  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/sched.h>
   9 #include <linux/linkage.h>
  10 #include <linux/ptrace.h>
  11 #include <linux/errno.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/signal.h>
  14 #include <linux/mm.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/slab.h>
  17 #include <linux/random.h>
  18 #include <linux/init.h>
  19 #include <linux/delay.h>
  20 #include <linux/proc_fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/ftrace.h>
  23 #include <linux/irq.h>
  24 #include <linux/kmemleak.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <linux/atomic.h>
  29 #include <asm/irq.h>
  30 #include <asm/io.h>
  31 #include <asm/iommu.h>
  32 #include <asm/upa.h>
  33 #include <asm/oplib.h>
  34 #include <asm/prom.h>
  35 #include <asm/timer.h>
  36 #include <asm/smp.h>
  37 #include <asm/starfire.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/cache.h>
  40 #include <asm/cpudata.h>
  41 #include <asm/auxio.h>
  42 #include <asm/head.h>
  43 #include <asm/hypervisor.h>
  44 #include <asm/cacheflush.h>
  45
  46 #include "entry.h"
  47 #include "cpumap.h"
  48 #include "kstack.h"
  49
  50 struct ino_bucket *ivector_table;
  51 unsigned long ivector_table_pa;
  52
  53 /* On several sun4u processors, it is illegal to mix bypass and
  54  * non-bypass accesses.  Therefore we access all INO buckets
  55  * using bypass accesses only.
  56  */
  57 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  58 {
  59         unsigned long ret;
  60
  61         __asm__ __volatile__("ldxa      [%1] %2, %0"
  62                              : "=&r" (ret)
  63                              : "r" (bucket_pa +
  64                                     offsetof(struct ino_bucket,
  65                                              __irq_chain_pa)),
  66                                "i" (ASI_PHYS_USE_EC));
  67
  68         return ret;
  69 }
  70
  71 static void bucket_clear_chain_pa(unsigned long bucket_pa)
  72 {
  73         __asm__ __volatile__("stxa      %%g0, [%0] %1"
  74                              : /* no outputs */
  75                              : "r" (bucket_pa +
  76                                     offsetof(struct ino_bucket,
  77                                              __irq_chain_pa)),
  78                                "i" (ASI_PHYS_USE_EC));
  79 }
  80
  81 static unsigned int bucket_get_irq(unsigned long bucket_pa)
  82 {
  83         unsigned int ret;
  84
  85         __asm__ __volatile__("lduwa     [%1] %2, %0"
  86                              : "=&r" (ret)
  87                              : "r" (bucket_pa +
  88                                     offsetof(struct ino_bucket,
  89                                              __irq)),
  90                                "i" (ASI_PHYS_USE_EC));
  91
  92         return ret;
  93 }
  94
  95 static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq)
  96 {
  97         __asm__ __volatile__("stwa      %0, [%1] %2"
  98                              : /* no outputs */
  99                              : "r" (irq),
 100                                "r" (bucket_pa +
 101                                     offsetof(struct ino_bucket,
 102                                              __irq)),
 103                                "i" (ASI_PHYS_USE_EC));
 104 }
 105
 106 #define irq_work_pa(__cpu)      &(trap_block[(__cpu)].irq_worklist_pa)
 107
 108 static unsigned long hvirq_major __initdata;
 109 static int __init early_hvirq_major(char *p)
 110 {
 111         int rc = kstrtoul(p, 10, &hvirq_major);
 112
 113         return rc;
 114 }
 115 early_param("hvirq", early_hvirq_major);
 116
 117 static int hv_irq_version;
 118
 119 /* Major version 2.0 of HV_GRP_INTR added support for the VIRQ cookie
 120  * based interfaces, but:
 121  *
 122  * 1) Several OSs, Solaris and Linux included, use them even when only
 123  *    negotiating version 1.0 (or failing to negotiate at all).  So the
 124  *    hypervisor has a workaround that provides the VIRQ interfaces even
 125  *    when only verion 1.0 of the API is in use.
 126  *
 127  * 2) Second, and more importantly, with major version 2.0 these VIRQ
 128  *    interfaces only were actually hooked up for LDC interrupts, even
 129  *    though the Hypervisor specification clearly stated:
 130  *
 131  *      The new interrupt API functions will be available to a guest
 132  *      when it negotiates version 2.0 in the interrupt API group 0x2. When
 133  *      a guest negotiates version 2.0, all interrupt sources will only
 134  *      support using the cookie interface, and any attempt to use the
 135  *      version 1.0 interrupt APIs numbered 0xa0 to 0xa6 will result in the
 136  *      ENOTSUPPORTED error being returned.
 137  *
 138  *   with an emphasis on "all interrupt sources".
 139  *
 140  * To correct this, major version 3.0 was created which does actually
 141  * support VIRQs for all interrupt sources (not just LDC devices).  So
 142  * if we want to move completely over the cookie based VIRQs we must
 143  * negotiate major version 3.0 or later of HV_GRP_INTR.
 144  */
 145 static bool sun4v_cookie_only_virqs(void)
 146 {
 147         if (hv_irq_version >= 3)
 148                 return true;
 149         return false;
 150 }
 151
 152 static void __init irq_init_hv(void)
 153 {
 154         unsigned long hv_error, major, minor = 0;
 155
 156         if (tlb_type != hypervisor)
 157                 return;
 158
 159         if (hvirq_major)
 160                 major = hvirq_major;
 161         else
 162                 major = 3;
 163
 164         hv_error = sun4v_hvapi_register(HV_GRP_INTR, major, &minor);
 165         if (!hv_error)
 166                 hv_irq_version = major;
 167         else
 168                 hv_irq_version = 1;
 169
 170         pr_info("SUN4V: Using IRQ API major %d, cookie only virqs %s\n",
 171                 hv_irq_version,
 172                 sun4v_cookie_only_virqs() ? "enabled" : "disabled");
 173 }
 174
 175 /* This function is for the timer interrupt.*/
 176 int __init arch_probe_nr_irqs(void)
 177 {
 178         return 1;
 179 }
 180
 181 #define DEFAULT_NUM_IVECS       (0xfffU)
 182 static unsigned int nr_ivec = DEFAULT_NUM_IVECS;
 183 #define NUM_IVECS (nr_ivec)
 184
 185 static unsigned int __init size_nr_ivec(void)
 186 {
 187         if (tlb_type == hypervisor) {
 188                 switch (sun4v_chip_type) {
 189                 /* Athena's devhandle|devino is large.*/
 190                 case SUN4V_CHIP_SPARC64X:
 191                         nr_ivec = 0xffff;
 192                         break;
 193                 }
 194         }
 195         return nr_ivec;
 196 }
 197
 198 struct irq_handler_data {
 199         union {
 200                 struct {
 201                         unsigned int dev_handle;
 202                         unsigned int dev_ino;
 203                 };
 204                 unsigned long sysino;
 205         };
 206         struct ino_bucket bucket;
 207         unsigned long   iclr;
 208         unsigned long   imap;
 209 };
 210
 211 static inline unsigned int irq_data_to_handle(struct irq_data *data)
 212 {
 213         struct irq_handler_data *ihd = data->handler_data;
 214
 215         return ihd->dev_handle;
 216 }
 217
 218 static inline unsigned int irq_data_to_ino(struct irq_data *data)
 219 {
 220         struct irq_handler_data *ihd = data->handler_data;
 221
 222         return ihd->dev_ino;
 223 }
 224
 225 static inline unsigned long irq_data_to_sysino(struct irq_data *data)
 226 {
 227         struct irq_handler_data *ihd = data->handler_data;
 228
 229         return ihd->sysino;
 230 }
 231
 232 void irq_free(unsigned int irq)
 233 {
 234         void *data = irq_get_handler_data(irq);
 235
 236         kfree(data);
 237         irq_set_handler_data(irq, NULL);
 238         irq_free_descs(irq, 1);
 239 }
 240
 241 unsigned int irq_alloc(unsigned int dev_handle, unsigned int dev_ino)
 242 {
 243         int irq;
 244
 245         irq = __irq_alloc_descs(-1, 1, 1, numa_node_id(), NULL);
 246         if (irq <= 0)
 247                 goto out;
 248
 249         return irq;
 250 out:
 251         return 0;
 252 }
 253
 254 static unsigned int cookie_exists(u32 devhandle, unsigned int devino)
 255 {
 256         unsigned long hv_err, cookie;
 257         struct ino_bucket *bucket;
 258         unsigned int irq = 0U;
 259
 260         hv_err = sun4v_vintr_get_cookie(devhandle, devino, &cookie);
 261         if (hv_err) {
 262                 pr_err("HV get cookie failed hv_err = %ld\n", hv_err);
 263                 goto out;
 264         }
 265
 266         if (cookie & ((1UL << 63UL))) {
 267                 cookie = ~cookie;
 268                 bucket = (struct ino_bucket *) __va(cookie);
 269                 irq = bucket->__irq;
 270         }
 271 out:
 272         return irq;
 273 }
 274
 275 static unsigned int sysino_exists(u32 devhandle, unsigned int devino)
 276 {
 277         unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
 278         struct ino_bucket *bucket;
 279         unsigned int irq;
 280
 281         bucket = &ivector_table[sysino];
 282         irq = bucket_get_irq(__pa(bucket));
 283
 284         return irq;
 285 }
 286
 287 void ack_bad_irq(unsigned int irq)
 288 {
 289         pr_crit("BAD IRQ ack %d\n", irq);
 290 }
 291
 292 void irq_install_pre_handler(int irq,
 293                              void (*func)(unsigned int, void *, void *),
 294                              void *arg1, void *arg2)
 295 {
 296         pr_warn("IRQ pre handler NOT supported.\n");
 297 }
 298
 299 /*
 300  * /proc/interrupts printing:
 301  */
 302 int arch_show_interrupts(struct seq_file *p, int prec)
 303 {
 304         int j;
 305
 306         seq_printf(p, "NMI: ");
 307         for_each_online_cpu(j)
 308                 seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
 309         seq_printf(p, "     Non-maskable interrupts\n");
 310         return 0;
 311 }
 312
 313 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 314 {
 315         unsigned int tid;
 316
 317         if (this_is_starfire) {
 318                 tid = starfire_translate(imap, cpuid);
 319                 tid <<= IMAP_TID_SHIFT;
 320                 tid &= IMAP_TID_UPA;
 321         } else {
 322                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 323                         unsigned long ver;
 324
 325                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 326                         if ((ver >> 32UL) == __JALAPENO_ID ||
 327                             (ver >> 32UL) == __SERRANO_ID) {
 328                                 tid = cpuid << IMAP_TID_SHIFT;
 329                                 tid &= IMAP_TID_JBUS;
 330                         } else {
 331                                 unsigned int a = cpuid & 0x1f;
 332                                 unsigned int n = (cpuid >> 5) & 0x1f;
 333
 334                                 tid = ((a << IMAP_AID_SHIFT) |
 335                                        (n << IMAP_NID_SHIFT));
 336                                 tid &= (IMAP_AID_SAFARI |
 337                                         IMAP_NID_SAFARI);
 338                         }
 339                 } else {
 340                         tid = cpuid << IMAP_TID_SHIFT;
 341                         tid &= IMAP_TID_UPA;
 342                 }
 343         }
 344
 345         return tid;
 346 }
 347
 348 #ifdef CONFIG_SMP
 349 static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity)
 350 {
 351         cpumask_t mask;
 352         int cpuid;
 353
 354         cpumask_copy(&mask, affinity);
 355         if (cpumask_equal(&mask, cpu_online_mask)) {
 356                 cpuid = map_to_cpu(irq);
 357         } else {
 358                 cpumask_t tmp;
 359
 360                 cpumask_and(&tmp, cpu_online_mask, &mask);
 361                 cpuid = cpumask_empty(&tmp) ? map_to_cpu(irq) : cpumask_first(&tmp);
 362         }
 363
 364         return cpuid;
 365 }
 366 #else
 367 #define irq_choose_cpu(irq, affinity)   \
 368         real_hard_smp_processor_id()
 369 #endif
 370
 371 static void sun4u_irq_enable(struct irq_data *data)
 372 {
 373         struct irq_handler_data *handler_data = data->handler_data;
 374
 375         if (likely(handler_data)) {
 376                 unsigned long cpuid, imap, val;
 377                 unsigned int tid;
 378
 379                 cpuid = irq_choose_cpu(data->irq, data->affinity);
 380                 imap = handler_data->imap;
 381
 382                 tid = sun4u_compute_tid(imap, cpuid);
 383
 384                 val = upa_readq(imap);
 385                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 386                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 387                 val |= tid | IMAP_VALID;
 388                 upa_writeq(val, imap);
 389                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 390         }
 391 }
 392
 393 static int sun4u_set_affinity(struct irq_data *data,
 394                                const struct cpumask *mask, bool force)
 395 {
 396         struct irq_handler_data *handler_data = data->handler_data;
 397
 398         if (likely(handler_data)) {
 399                 unsigned long cpuid, imap, val;
 400                 unsigned int tid;
 401
 402                 cpuid = irq_choose_cpu(data->irq, mask);
 403                 imap = handler_data->imap;
 404
 405                 tid = sun4u_compute_tid(imap, cpuid);
 406
 407                 val = upa_readq(imap);
 408                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 409                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 410                 val |= tid | IMAP_VALID;
 411                 upa_writeq(val, imap);
 412                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 413         }
 414
 415         return 0;
 416 }
 417
 418 /* Don't do anything.  The desc->status check for IRQ_DISABLED in
 419  * handler_irq() will skip the handler call and that will leave the
 420  * interrupt in the sent state.  The next ->enable() call will hit the
 421  * ICLR register to reset the state machine.
 422  *
 423  * This scheme is necessary, instead of clearing the Valid bit in the
 424  * IMAP register, to handle the case of IMAP registers being shared by
 425  * multiple INOs (and thus ICLR registers).  Since we use a different
 426  * virtual IRQ for each shared IMAP instance, the generic code thinks
 427  * there is only one user so it prematurely calls ->disable() on
 428  * free_irq().
 429  *
 430  * We have to provide an explicit ->disable() method instead of using
 431  * NULL to get the default.  The reason is that if the generic code
 432  * sees that, it also hooks up a default ->shutdown method which
 433  * invokes ->mask() which we do not want.  See irq_chip_set_defaults().
 434  */
 435 static void sun4u_irq_disable(struct irq_data *data)
 436 {
 437 }
 438
 439 static void sun4u_irq_eoi(struct irq_data *data)
 440 {
 441         struct irq_handler_data *handler_data = data->handler_data;
 442
 443         if (likely(handler_data))
 444                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 445 }
 446
 447 static void sun4v_irq_enable(struct irq_data *data)
 448 {
 449         unsigned long cpuid = irq_choose_cpu(data->irq, data->affinity);
 450         unsigned int ino = irq_data_to_sysino(data);
 451         int err;
 452
 453         err = sun4v_intr_settarget(ino, cpuid);
 454         if (err != HV_EOK)
 455                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 456                        "err(%d)\n", ino, cpuid, err);
 457         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 458         if (err != HV_EOK)
 459                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 460                        "err(%d)\n", ino, err);
 461         err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 462         if (err != HV_EOK)
 463                 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
 464                        ino, err);
 465 }
 466
 467 static int sun4v_set_affinity(struct irq_data *data,
 468                                const struct cpumask *mask, bool force)
 469 {
 470         unsigned long cpuid = irq_choose_cpu(data->irq, mask);
 471         unsigned int ino = irq_data_to_sysino(data);
 472         int err;
 473
 474         err = sun4v_intr_settarget(ino, cpuid);
 475         if (err != HV_EOK)
 476                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 477                        "err(%d)\n", ino, cpuid, err);
 478
 479         return 0;
 480 }
 481
 482 static void sun4v_irq_disable(struct irq_data *data)
 483 {
 484         unsigned int ino = irq_data_to_sysino(data);
 485         int err;
 486
 487         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 488         if (err != HV_EOK)
 489                 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
 490                        "err(%d)\n", ino, err);
 491 }
 492
 493 static void sun4v_irq_eoi(struct irq_data *data)
 494 {
 495         unsigned int ino = irq_data_to_sysino(data);
 496         int err;
 497
 498         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 499         if (err != HV_EOK)
 500                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 501                        "err(%d)\n", ino, err);
 502 }
 503
 504 static void sun4v_virq_enable(struct irq_data *data)
 505 {
 506         unsigned long dev_handle = irq_data_to_handle(data);
 507         unsigned long dev_ino = irq_data_to_ino(data);
 508         unsigned long cpuid;
 509         int err;
 510
 511         cpuid = irq_choose_cpu(data->irq, data->affinity);
 512
 513         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 514         if (err != HV_EOK)
 515                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 516                        "err(%d)\n",
 517                        dev_handle, dev_ino, cpuid, err);
 518         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 519                                     HV_INTR_STATE_IDLE);
 520         if (err != HV_EOK)
 521                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 522                        "HV_INTR_STATE_IDLE): err(%d)\n",
 523                        dev_handle, dev_ino, err);
 524         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 525                                     HV_INTR_ENABLED);
 526         if (err != HV_EOK)
 527                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 528                        "HV_INTR_ENABLED): err(%d)\n",
 529                        dev_handle, dev_ino, err);
 530 }
 531
 532 static int sun4v_virt_set_affinity(struct irq_data *data,
 533                                     const struct cpumask *mask, bool force)
 534 {
 535         unsigned long dev_handle = irq_data_to_handle(data);
 536         unsigned long dev_ino = irq_data_to_ino(data);
 537         unsigned long cpuid;
 538         int err;
 539
 540         cpuid = irq_choose_cpu(data->irq, mask);
 541
 542         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 543         if (err != HV_EOK)
 544                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 545                        "err(%d)\n",
 546                        dev_handle, dev_ino, cpuid, err);
 547
 548         return 0;
 549 }
 550
 551 static void sun4v_virq_disable(struct irq_data *data)
 552 {
 553         unsigned long dev_handle = irq_data_to_handle(data);
 554         unsigned long dev_ino = irq_data_to_ino(data);
 555         int err;
 556
 557
 558         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 559                                     HV_INTR_DISABLED);
 560         if (err != HV_EOK)
 561                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 562                        "HV_INTR_DISABLED): err(%d)\n",
 563                        dev_handle, dev_ino, err);
 564 }
 565
 566 static void sun4v_virq_eoi(struct irq_data *data)
 567 {
 568         unsigned long dev_handle = irq_data_to_handle(data);
 569         unsigned long dev_ino = irq_data_to_ino(data);
 570         int err;
 571
 572         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 573                                     HV_INTR_STATE_IDLE);
 574         if (err != HV_EOK)
 575                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 576                        "HV_INTR_STATE_IDLE): err(%d)\n",
 577                        dev_handle, dev_ino, err);
 578 }
 579
 580 static struct irq_chip sun4u_irq = {
 581         .name                   = "sun4u",
 582         .irq_enable             = sun4u_irq_enable,
 583         .irq_disable            = sun4u_irq_disable,
 584         .irq_eoi                = sun4u_irq_eoi,
 585         .irq_set_affinity       = sun4u_set_affinity,
 586         .flags                  = IRQCHIP_EOI_IF_HANDLED,
 587 };
 588
 589 static struct irq_chip sun4v_irq = {
 590         .name                   = "sun4v",
 591         .irq_enable             = sun4v_irq_enable,
 592         .irq_disable            = sun4v_irq_disable,
 593         .irq_eoi                = sun4v_irq_eoi,
 594         .irq_set_affinity       = sun4v_set_affinity,
 595         .flags                  = IRQCHIP_EOI_IF_HANDLED,
 596 };
 597
 598 static struct irq_chip sun4v_virq = {
 599         .name                   = "vsun4v",
 600         .irq_enable             = sun4v_virq_enable,
 601         .irq_disable            = sun4v_virq_disable,
 602         .irq_eoi                = sun4v_virq_eoi,
 603         .irq_set_affinity       = sun4v_virt_set_affinity,
 604         .flags                  = IRQCHIP_EOI_IF_HANDLED,
 605 };
 606
 607 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
 608 {
 609         struct irq_handler_data *handler_data;
 610         struct ino_bucket *bucket;
 611         unsigned int irq;
 612         int ino;
 613
 614         BUG_ON(tlb_type == hypervisor);
 615
 616         ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 617         bucket = &ivector_table[ino];
 618         irq = bucket_get_irq(__pa(bucket));
 619         if (!irq) {
 620                 irq = irq_alloc(0, ino);
 621                 bucket_set_irq(__pa(bucket), irq);
 622                 irq_set_chip_and_handler_name(irq, &sun4u_irq,
 623                                               handle_fasteoi_irq, "IVEC");
 624         }
 625
 626         handler_data = irq_get_handler_data(irq);
 627         if (unlikely(handler_data))
 628                 goto out;
 629
 630         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 631         if (unlikely(!handler_data)) {
 632                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 633                 prom_halt();
 634         }
 635         irq_set_handler_data(irq, handler_data);
 636
 637         handler_data->imap  = imap;
 638         handler_data->iclr  = iclr;
 639
 640 out:
 641         return irq;
 642 }
 643
 644 static unsigned int sun4v_build_common(u32 devhandle, unsigned int devino,
 645                 void (*handler_data_init)(struct irq_handler_data *data,
 646                 u32 devhandle, unsigned int devino),
 647                 struct irq_chip *chip)
 648 {
 649         struct irq_handler_data *data;
 650         unsigned int irq;
 651
 652         irq = irq_alloc(devhandle, devino);
 653         if (!irq)
 654                 goto out;
 655
 656         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 657         if (unlikely(!data)) {
 658                 pr_err("IRQ handler data allocation failed.\n");
 659                 irq_free(irq);
 660                 irq = 0;
 661                 goto out;
 662         }
 663
 664         irq_set_handler_data(irq, data);
 665         handler_data_init(data, devhandle, devino);
 666         irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq, "IVEC");
 667         data->imap = ~0UL;
 668         data->iclr = ~0UL;
 669 out:
 670         return irq;
 671 }
 672
 673 static unsigned long cookie_assign(unsigned int irq, u32 devhandle,
 674                 unsigned int devino)
 675 {
 676         struct irq_handler_data *ihd = irq_get_handler_data(irq);
 677         unsigned long hv_error, cookie;
 678
 679         /* handler_irq needs to find the irq. cookie is seen signed in
 680          * sun4v_dev_mondo and treated as a non ivector_table delivery.
 681          */
 682         ihd->bucket.__irq = irq;
 683         cookie = ~__pa(&ihd->bucket);
 684
 685         hv_error = sun4v_vintr_set_cookie(devhandle, devino, cookie);
 686         if (hv_error)
 687                 pr_err("HV vintr set cookie failed = %ld\n", hv_error);
 688
 689         return hv_error;
 690 }
 691
 692 static void cookie_handler_data(struct irq_handler_data *data,
 693                                 u32 devhandle, unsigned int devino)
 694 {
 695         data->dev_handle = devhandle;
 696         data->dev_ino = devino;
 697 }
 698
 699 static unsigned int cookie_build_irq(u32 devhandle, unsigned int devino,
 700                                      struct irq_chip *chip)
 701 {
 702         unsigned long hv_error;
 703         unsigned int irq;
 704
 705         irq = sun4v_build_common(devhandle, devino, cookie_handler_data, chip);
 706
 707         hv_error = cookie_assign(irq, devhandle, devino);
 708         if (hv_error) {
 709                 irq_free(irq);
 710                 irq = 0;
 711         }
 712
 713         return irq;
 714 }
 715
 716 static unsigned int sun4v_build_cookie(u32 devhandle, unsigned int devino)
 717 {
 718         unsigned int irq;
 719
 720         irq = cookie_exists(devhandle, devino);
 721         if (irq)
 722                 goto out;
 723
 724         irq = cookie_build_irq(devhandle, devino, &sun4v_virq);
 725
 726 out:
 727         return irq;
 728 }
 729
 730 static void sysino_set_bucket(unsigned int irq)
 731 {
 732         struct irq_handler_data *ihd = irq_get_handler_data(irq);
 733         struct ino_bucket *bucket;
 734         unsigned long sysino;
 735
 736         sysino = sun4v_devino_to_sysino(ihd->dev_handle, ihd->dev_ino);
 737         BUG_ON(sysino >= nr_ivec);
 738         bucket = &ivector_table[sysino];
 739         bucket_set_irq(__pa(bucket), irq);
 740 }
 741
 742 static void sysino_handler_data(struct irq_handler_data *data,
 743                                 u32 devhandle, unsigned int devino)
 744 {
 745         unsigned long sysino;
 746
 747         sysino = sun4v_devino_to_sysino(devhandle, devino);
 748         data->sysino = sysino;
 749 }
 750
 751 static unsigned int sysino_build_irq(u32 devhandle, unsigned int devino,
 752                                      struct irq_chip *chip)
 753 {
 754         unsigned int irq;
 755
 756         irq = sun4v_build_common(devhandle, devino, sysino_handler_data, chip);
 757         if (!irq)
 758                 goto out;
 759
 760         sysino_set_bucket(irq);
 761 out:
 762         return irq;
 763 }
 764
 765 static int sun4v_build_sysino(u32 devhandle, unsigned int devino)
 766 {
 767         int irq;
 768
 769         irq = sysino_exists(devhandle, devino);
 770         if (irq)
 771                 goto out;
 772
 773         irq = sysino_build_irq(devhandle, devino, &sun4v_irq);
 774 out:
 775         return irq;
 776 }
 777
 778 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
 779 {
 780         unsigned int irq;
 781
 782         if (sun4v_cookie_only_virqs())
 783                 irq = sun4v_build_cookie(devhandle, devino);
 784         else
 785                 irq = sun4v_build_sysino(devhandle, devino);
 786
 787         return irq;
 788 }
 789
 790 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
 791 {
 792         int irq;
 793
 794         irq = cookie_build_irq(devhandle, devino, &sun4v_virq);
 795         if (!irq)
 796                 goto out;
 797
 798         /* This is borrowed from the original function.
 799          */
 800         irq_set_status_flags(irq, IRQ_NOAUTOEN);
 801
 802 out:
 803         return irq;
 804 }
 805
 806 void *hardirq_stack[NR_CPUS];
 807 void *softirq_stack[NR_CPUS];
 808
 809 void __irq_entry handler_irq(int pil, struct pt_regs *regs)
 810 {
 811         unsigned long pstate, bucket_pa;
 812         struct pt_regs *old_regs;
 813         void *orig_sp;
 814
 815         clear_softint(1 << pil);
 816
 817         old_regs = set_irq_regs(regs);
 818         irq_enter();
 819
 820         /* Grab an atomic snapshot of the pending IVECs.  */
 821         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
 822                              "wrpr      %0, %3, %%pstate\n\t"
 823                              "ldx       [%2], %1\n\t"
 824                              "stx       %%g0, [%2]\n\t"
 825                              "wrpr      %0, 0x0, %%pstate\n\t"
 826                              : "=&r" (pstate), "=&r" (bucket_pa)
 827                              : "r" (irq_work_pa(smp_processor_id())),
 828                                "i" (PSTATE_IE)
 829                              : "memory");
 830
 831         orig_sp = set_hardirq_stack();
 832
 833         while (bucket_pa) {
 834                 unsigned long next_pa;
 835                 unsigned int irq;
 836
 837                 next_pa = bucket_get_chain_pa(bucket_pa);
 838                 irq = bucket_get_irq(bucket_pa);
 839                 bucket_clear_chain_pa(bucket_pa);
 840
 841                 generic_handle_irq(irq);
 842
 843                 bucket_pa = next_pa;
 844         }
 845
 846         restore_hardirq_stack(orig_sp);
 847
 848         irq_exit();
 849         set_irq_regs(old_regs);
 850 }
 851
 852 void do_softirq_own_stack(void)
 853 {
 854         void *orig_sp, *sp = softirq_stack[smp_processor_id()];
 855
 856         sp += THREAD_SIZE - 192 - STACK_BIAS;
 857
 858         __asm__ __volatile__("mov %%sp, %0\n\t"
 859                              "mov %1, %%sp"
 860                              : "=&r" (orig_sp)
 861                              : "r" (sp));
 862         __do_softirq();
 863         __asm__ __volatile__("mov %0, %%sp"
 864                              : : "r" (orig_sp));
 865 }
 866
 867 #ifdef CONFIG_HOTPLUG_CPU
 868 void fixup_irqs(void)
 869 {
 870         unsigned int irq;
 871
 872         for (irq = 0; irq < NR_IRQS; irq++) {
 873                 struct irq_desc *desc = irq_to_desc(irq);
 874                 struct irq_data *data;
 875                 unsigned long flags;
 876
 877                 if (!desc)
 878                         continue;
 879                 data = irq_desc_get_irq_data(desc);
 880                 raw_spin_lock_irqsave(&desc->lock, flags);
 881                 if (desc->action && !irqd_is_per_cpu(data)) {
 882                         if (data->chip->irq_set_affinity)
 883                                 data->chip->irq_set_affinity(data,
 884                                                              data->affinity,
 885                                                              false);
 886                 }
 887                 raw_spin_unlock_irqrestore(&desc->lock, flags);
 888         }
 889
 890         tick_ops->disable_irq();
 891 }
 892 #endif
 893
 894 struct sun5_timer {
 895         u64     count0;
 896         u64     limit0;
 897         u64     count1;
 898         u64     limit1;
 899 };
 900
 901 static struct sun5_timer *prom_timers;
 902 static u64 prom_limit0, prom_limit1;
 903
 904 static void map_prom_timers(void)
 905 {
 906         struct device_node *dp;
 907         const unsigned int *addr;
 908
 909         /* PROM timer node hangs out in the top level of device siblings... */
 910         dp = of_find_node_by_path("/");
 911         dp = dp->child;
 912         while (dp) {
 913                 if (!strcmp(dp->name, "counter-timer"))
 914                         break;
 915                 dp = dp->sibling;
 916         }
 917
 918         /* Assume if node is not present, PROM uses different tick mechanism
 919          * which we should not care about.
 920          */
 921         if (!dp) {
 922                 prom_timers = (struct sun5_timer *) 0;
 923                 return;
 924         }
 925
 926         /* If PROM is really using this, it must be mapped by him. */
 927         addr = of_get_property(dp, "address", NULL);
 928         if (!addr) {
 929                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 930                 prom_timers = (struct sun5_timer *) 0;
 931                 return;
 932         }
 933         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 934 }
 935
 936 static void kill_prom_timer(void)
 937 {
 938         if (!prom_timers)
 939                 return;
 940
 941         /* Save them away for later. */
 942         prom_limit0 = prom_timers->limit0;
 943         prom_limit1 = prom_timers->limit1;
 944
 945         /* Just as in sun4c PROM uses timer which ticks at IRQ 14.
 946          * We turn both off here just to be paranoid.
 947          */
 948         prom_timers->limit0 = 0;
 949         prom_timers->limit1 = 0;
 950
 951         /* Wheee, eat the interrupt packet too... */
 952         __asm__ __volatile__(
 953 "       mov     0x40, %%g2\n"
 954 "       ldxa    [%%g0] %0, %%g1\n"
 955 "       ldxa    [%%g2] %1, %%g1\n"
 956 "       stxa    %%g0, [%%g0] %0\n"
 957 "       membar  #Sync\n"
 958         : /* no outputs */
 959         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 960         : "g1", "g2");
 961 }
 962
 963 void notrace init_irqwork_curcpu(void)
 964 {
 965         int cpu = hard_smp_processor_id();
 966
 967         trap_block[cpu].irq_worklist_pa = 0UL;
 968 }
 969
 970 /* Please be very careful with register_one_mondo() and
 971  * sun4v_register_mondo_queues().
 972  *
 973  * On SMP this gets invoked from the CPU trampoline before
 974  * the cpu has fully taken over the trap table from OBP,
 975  * and it's kernel stack + %g6 thread register state is
 976  * not fully cooked yet.
 977  *
 978  * Therefore you cannot make any OBP calls, not even prom_printf,
 979  * from these two routines.
 980  */
 981 static void notrace register_one_mondo(unsigned long paddr, unsigned long type,
 982                                        unsigned long qmask)
 983 {
 984         unsigned long num_entries = (qmask + 1) / 64;
 985         unsigned long status;
 986
 987         status = sun4v_cpu_qconf(type, paddr, num_entries);
 988         if (status != HV_EOK) {
 989                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 990                             "err %lu\n", type, paddr, num_entries, status);
 991                 prom_halt();
 992         }
 993 }
 994
 995 void notrace sun4v_register_mondo_queues(int this_cpu)
 996 {
 997         struct trap_per_cpu *tb = &trap_block[this_cpu];
 998
 999         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
1000                            tb->cpu_mondo_qmask);
1001         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
1002                            tb->dev_mondo_qmask);
1003         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
1004                            tb->resum_qmask);
1005         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
1006                            tb->nonresum_qmask);
1007 }
1008
1009 /* Each queue region must be a power of 2 multiple of 64 bytes in
1010  * size.  The base real address must be aligned to the size of the
1011  * region.  Thus, an 8KB queue must be 8KB aligned, for example.
1012  */
1013 static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
1014 {
1015         unsigned long size = PAGE_ALIGN(qmask + 1);
1016         unsigned long order = get_order(size);
1017         unsigned long p;
1018
1019         p = __get_free_pages(GFP_KERNEL, order);
1020         if (!p) {
1021                 prom_printf("SUN4V: Error, cannot allocate queue.\n");
1022                 prom_halt();
1023         }
1024
1025         *pa_ptr = __pa(p);
1026 }
1027
1028 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
1029 {
1030 #ifdef CONFIG_SMP
1031         unsigned long page;
1032
1033         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
1034
1035         page = get_zeroed_page(GFP_KERNEL);
1036         if (!page) {
1037                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1038                 prom_halt();
1039         }
1040
1041         tb->cpu_mondo_block_pa = __pa(page);
1042         tb->cpu_list_pa = __pa(page + 64);
1043 #endif
1044 }
1045
1046 /* Allocate mondo and error queues for all possible cpus.  */
1047 static void __init sun4v_init_mondo_queues(void)
1048 {
1049         int cpu;
1050
1051         for_each_possible_cpu(cpu) {
1052                 struct trap_per_cpu *tb = &trap_block[cpu];
1053
1054                 alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
1055                 alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
1056                 alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
1057                 alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
1058                 alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
1059                 alloc_one_queue(&tb->nonresum_kernel_buf_pa,
1060                                 tb->nonresum_qmask);
1061         }
1062 }
1063
1064 static void __init init_send_mondo_info(void)
1065 {
1066         int cpu;
1067
1068         for_each_possible_cpu(cpu) {
1069                 struct trap_per_cpu *tb = &trap_block[cpu];
1070
1071                 init_cpu_send_mondo_info(tb);
1072         }
1073 }
1074
1075 static struct irqaction timer_irq_action = {
1076         .name = "timer",
1077 };
1078
1079 static void __init irq_ivector_init(void)
1080 {
1081         unsigned long size, order;
1082         unsigned int ivecs;
1083
1084         /* If we are doing cookie only VIRQs then we do not need the ivector
1085          * table to process interrupts.
1086          */
1087         if (sun4v_cookie_only_virqs())
1088                 return;
1089
1090         ivecs = size_nr_ivec();
1091         size = sizeof(struct ino_bucket) * ivecs;
1092         order = get_order(size);
1093         ivector_table = (struct ino_bucket *)
1094                 __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
1095         if (!ivector_table) {
1096                 prom_printf("Fatal error, cannot allocate ivector_table\n");
1097                 prom_halt();
1098         }
1099         __flush_dcache_range((unsigned long) ivector_table,
1100                              ((unsigned long) ivector_table) + size);
1101
1102         ivector_table_pa = __pa(ivector_table);
1103 }
1104
1105 /* Only invoked on boot processor.*/
1106 void __init init_IRQ(void)
1107 {
1108         irq_init_hv();
1109         irq_ivector_init();
1110         map_prom_timers();
1111         kill_prom_timer();
1112
1113         if (tlb_type == hypervisor)
1114                 sun4v_init_mondo_queues();
1115
1116         init_send_mondo_info();
1117
1118         if (tlb_type == hypervisor) {
1119                 /* Load up the boot cpu's entries.  */
1120                 sun4v_register_mondo_queues(hard_smp_processor_id());
1121         }
1122
1123         /* We need to clear any IRQ's pending in the soft interrupt
1124          * registers, a spurious one could be left around from the
1125          * PROM timer which we just disabled.
1126          */
1127         clear_softint(get_softint());
1128
1129         /* Now that ivector table is initialized, it is safe
1130          * to receive IRQ vector traps.  We will normally take
1131          * one or two right now, in case some device PROM used
1132          * to boot us wants to speak to us.  We just ignore them.
1133          */
1134         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1135                              "or        %%g1, %0, %%g1\n\t"
1136                              "wrpr      %%g1, 0x0, %%pstate"
1137                              : /* No outputs */
1138                              : "i" (PSTATE_IE)
1139                              : "g1");
1140
1141         irq_to_desc(0)->action = &timer_irq_action;
1142 }