arch/sparc/include/asm/processor_64.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * include/asm/processor.h
   4  *
   5  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
   6  */
   7
   8 #ifndef __ASM_SPARC64_PROCESSOR_H
   9 #define __ASM_SPARC64_PROCESSOR_H
  10
  11 /*
  12  * Sparc64 implementation of macro that returns current
  13  * instruction pointer ("program counter").
  14  */
  15 #define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
  16
  17 #include <asm/asi.h>
  18 #include <asm/pstate.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/page.h>
  21
  22 /*
  23  * User lives in his very own context, and cannot reference us. Note
  24  * that TASK_SIZE is a misnomer, it really gives maximum user virtual
  25  * address that the kernel will allocate out.
  26  *
  27  * XXX No longer using virtual page tables, kill this upper limit...
  28  */
  29 #define VA_BITS         44
  30 #ifndef __ASSEMBLY__
  31 #define VPTE_SIZE       (1UL << (VA_BITS - PAGE_SHIFT + 3))
  32 #else
  33 #define VPTE_SIZE       (1 << (VA_BITS - PAGE_SHIFT + 3))
  34 #endif
  35
  36 #define TASK_SIZE_OF(tsk) \
  37         (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
  38          (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
  39 #define TASK_SIZE \
  40         (test_thread_flag(TIF_32BIT) ? \
  41          (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
  42 #ifdef __KERNEL__
  43
  44 #define STACK_TOP32     ((1UL << 32UL) - PAGE_SIZE)
  45 #define STACK_TOP64     (0x0000080000000000UL - (1UL << 32UL))
  46
  47 #define STACK_TOP       (test_thread_flag(TIF_32BIT) ? \
  48                          STACK_TOP32 : STACK_TOP64)
  49
  50 #define STACK_TOP_MAX   STACK_TOP64
  51
  52 #endif
  53
  54 #ifndef __ASSEMBLY__
  55
  56 typedef struct {
  57         unsigned char seg;
  58 } mm_segment_t;
  59
  60 /* The Sparc processor specific thread struct. */
  61 /* XXX This should die, everything can go into thread_info now. */
  62 struct thread_struct {
  63 #ifdef CONFIG_DEBUG_SPINLOCK
  64         /* How many spinlocks held by this thread.
  65          * Used with spin lock debugging to catch tasks
  66          * sleeping illegally with locks held.
  67          */
  68         int smp_lock_count;
  69         unsigned int smp_lock_pc;
  70 #else
  71         int dummy; /* f'in gcc bug... */
  72 #endif
  73 };
  74
  75 #endif /* !(__ASSEMBLY__) */
  76
  77 #ifndef CONFIG_DEBUG_SPINLOCK
  78 #define INIT_THREAD  {                  \
  79         0,                              \
  80 }
  81 #else /* CONFIG_DEBUG_SPINLOCK */
  82 #define INIT_THREAD  {                                  \
  83 /* smp_lock_count, smp_lock_pc, */                      \
  84    0,              0,                                   \
  85 }
  86 #endif /* !(CONFIG_DEBUG_SPINLOCK) */
  87
  88 #ifndef __ASSEMBLY__
  89
  90 #include <linux/types.h>
  91 #include <asm/fpumacro.h>
  92
  93 struct task_struct;
  94
  95 /* On Uniprocessor, even in RMO processes see TSO semantics */
  96 #ifdef CONFIG_SMP
  97 #define TSTATE_INITIAL_MM       TSTATE_TSO
  98 #else
  99 #define TSTATE_INITIAL_MM       TSTATE_RMO
 100 #endif
 101
 102 /* Do necessary setup to start up a newly executed thread. */
 103 #define start_thread(regs, pc, sp) \
 104 do { \
 105         unsigned long __asi = ASI_PNF; \
 106         regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
 107         regs->tpc = ((pc & (~3)) - 4); \
 108         regs->tnpc = regs->tpc + 4; \
 109         regs->y = 0; \
 110         set_thread_wstate(1 << 3); \
 111         if (current_thread_info()->utraps) { \
 112                 if (*(current_thread_info()->utraps) < 2) \
 113                         kfree(current_thread_info()->utraps); \
 114                 else \
 115                         (*(current_thread_info()->utraps))--; \
 116                 current_thread_info()->utraps = NULL; \
 117         } \
 118         __asm__ __volatile__( \
 119         "stx            %%g0, [%0 + %2 + 0x00]\n\t" \
 120         "stx            %%g0, [%0 + %2 + 0x08]\n\t" \
 121         "stx            %%g0, [%0 + %2 + 0x10]\n\t" \
 122         "stx            %%g0, [%0 + %2 + 0x18]\n\t" \
 123         "stx            %%g0, [%0 + %2 + 0x20]\n\t" \
 124         "stx            %%g0, [%0 + %2 + 0x28]\n\t" \
 125         "stx            %%g0, [%0 + %2 + 0x30]\n\t" \
 126         "stx            %%g0, [%0 + %2 + 0x38]\n\t" \
 127         "stx            %%g0, [%0 + %2 + 0x40]\n\t" \
 128         "stx            %%g0, [%0 + %2 + 0x48]\n\t" \
 129         "stx            %%g0, [%0 + %2 + 0x50]\n\t" \
 130         "stx            %%g0, [%0 + %2 + 0x58]\n\t" \
 131         "stx            %%g0, [%0 + %2 + 0x60]\n\t" \
 132         "stx            %%g0, [%0 + %2 + 0x68]\n\t" \
 133         "stx            %1,   [%0 + %2 + 0x70]\n\t" \
 134         "stx            %%g0, [%0 + %2 + 0x78]\n\t" \
 135         "wrpr           %%g0, (1 << 3), %%wstate\n\t" \
 136         : \
 137         : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
 138           "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
 139         fprs_write(0);  \
 140         current_thread_info()->xfsr[0] = 0;     \
 141         current_thread_info()->fpsaved[0] = 0;  \
 142         regs->tstate &= ~TSTATE_PEF;    \
 143 } while (0)
 144
 145 #define start_thread32(regs, pc, sp) \
 146 do { \
 147         unsigned long __asi = ASI_PNF; \
 148         pc &= 0x00000000ffffffffUL; \
 149         sp &= 0x00000000ffffffffUL; \
 150         regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
 151         regs->tpc = ((pc & (~3)) - 4); \
 152         regs->tnpc = regs->tpc + 4; \
 153         regs->y = 0; \
 154         set_thread_wstate(2 << 3); \
 155         if (current_thread_info()->utraps) { \
 156                 if (*(current_thread_info()->utraps) < 2) \
 157                         kfree(current_thread_info()->utraps); \
 158                 else \
 159                         (*(current_thread_info()->utraps))--; \
 160                 current_thread_info()->utraps = NULL; \
 161         } \
 162         __asm__ __volatile__( \
 163         "stx            %%g0, [%0 + %2 + 0x00]\n\t" \
 164         "stx            %%g0, [%0 + %2 + 0x08]\n\t" \
 165         "stx            %%g0, [%0 + %2 + 0x10]\n\t" \
 166         "stx            %%g0, [%0 + %2 + 0x18]\n\t" \
 167         "stx            %%g0, [%0 + %2 + 0x20]\n\t" \
 168         "stx            %%g0, [%0 + %2 + 0x28]\n\t" \
 169         "stx            %%g0, [%0 + %2 + 0x30]\n\t" \
 170         "stx            %%g0, [%0 + %2 + 0x38]\n\t" \
 171         "stx            %%g0, [%0 + %2 + 0x40]\n\t" \
 172         "stx            %%g0, [%0 + %2 + 0x48]\n\t" \
 173         "stx            %%g0, [%0 + %2 + 0x50]\n\t" \
 174         "stx            %%g0, [%0 + %2 + 0x58]\n\t" \
 175         "stx            %%g0, [%0 + %2 + 0x60]\n\t" \
 176         "stx            %%g0, [%0 + %2 + 0x68]\n\t" \
 177         "stx            %1,   [%0 + %2 + 0x70]\n\t" \
 178         "stx            %%g0, [%0 + %2 + 0x78]\n\t" \
 179         "wrpr           %%g0, (2 << 3), %%wstate\n\t" \
 180         : \
 181         : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
 182           "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
 183         fprs_write(0);  \
 184         current_thread_info()->xfsr[0] = 0;     \
 185         current_thread_info()->fpsaved[0] = 0;  \
 186         regs->tstate &= ~TSTATE_PEF;    \
 187 } while (0)
 188
 189 /* Free all resources held by a thread. */
 190 #define release_thread(tsk)             do { } while (0)
 191
 192 unsigned long get_wchan(struct task_struct *task);
 193
 194 #define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
 195 #define KSTK_EIP(tsk)  (task_pt_regs(tsk)->tpc)
 196 #define KSTK_ESP(tsk)  (task_pt_regs(tsk)->u_regs[UREG_FP])
 197
 198 /* Please see the commentary in asm/backoff.h for a description of
 199  * what these instructions are doing and how they have been chosen.
 200  * To make a long story short, we are trying to yield the current cpu
 201  * strand during busy loops.
 202  */
 203 #define cpu_relax()     asm volatile("\n99:\n\t"                        \
 204                                      "rd        %%ccr, %%g0\n\t"        \
 205                                      "rd        %%ccr, %%g0\n\t"        \
 206                                      "rd        %%ccr, %%g0\n\t"        \
 207                                      ".section  .pause_3insn_patch,\"ax\"\n\t"\
 208                                      ".word     99b\n\t"                \
 209                                      "wr        %%g0, 128, %%asr27\n\t" \
 210                                      "nop\n\t"                          \
 211                                      "nop\n\t"                          \
 212                                      ".previous"                        \
 213                                      ::: "memory")
 214
 215 /* Prefetch support.  This is tuned for UltraSPARC-III and later.
 216  * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
 217  * a shallower prefetch queue than later chips.
 218  */
 219 #define ARCH_HAS_PREFETCH
 220 #define ARCH_HAS_PREFETCHW
 221 #define ARCH_HAS_SPINLOCK_PREFETCH
 222
 223 static inline void prefetch(const void *x)
 224 {
 225         /* We do not use the read prefetch mnemonic because that
 226          * prefetches into the prefetch-cache which only is accessible
 227          * by floating point operations in UltraSPARC-III and later.
 228          * By contrast, "#one_write" prefetches into the L2 cache
 229          * in shared state.
 230          */
 231         __asm__ __volatile__("prefetch [%0], #one_write"
 232                              : /* no outputs */
 233                              : "r" (x));
 234 }
 235
 236 static inline void prefetchw(const void *x)
 237 {
 238         /* The most optimal prefetch to use for writes is
 239          * "#n_writes".  This brings the cacheline into the
 240          * L2 cache in "owned" state.
 241          */
 242         __asm__ __volatile__("prefetch [%0], #n_writes"
 243                              : /* no outputs */
 244                              : "r" (x));
 245 }
 246
 247 #define spin_lock_prefetch(x)   prefetchw(x)
 248
 249 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 250
 251 int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap);
 252
 253 #endif /* !(__ASSEMBLY__) */
 254
 255 #endif /* !(__ASM_SPARC64_PROCESSOR_H) */