1 #ifndef _SPARC64_HYPERVISOR_H
2 #define _SPARC64_HYPERVISOR_H
4 /* Sun4v hypervisor interfaces and defines.
6 * Hypervisor calls are made via traps to software traps number 0x80
7 * and above. Registers %o0 to %o5 serve as argument, status, and
8 * return value registers.
10 * There are two kinds of these traps. First there are the normal
11 * "fast traps" which use software trap 0x80 and encode the function
12 * to invoke by number in register %o5. Argument and return value
13 * handling is as follows:
15 * -----------------------------------------------
16 * | %o5 | function number | undefined |
17 * | %o0 | argument 0 | return status |
18 * | %o1 | argument 1 | return value 1 |
19 * | %o2 | argument 2 | return value 2 |
20 * | %o3 | argument 3 | return value 3 |
21 * | %o4 | argument 4 | return value 4 |
22 * -----------------------------------------------
24 * The second type are "hyper-fast traps" which encode the function
25 * number in the software trap number itself. So these use trap
26 * numbers > 0x80. The register usage for hyper-fast traps is as
29 * -----------------------------------------------
30 * | %o0 | argument 0 | return status |
31 * | %o1 | argument 1 | return value 1 |
32 * | %o2 | argument 2 | return value 2 |
33 * | %o3 | argument 3 | return value 3 |
34 * | %o4 | argument 4 | return value 4 |
35 * -----------------------------------------------
37 * Registers providing explicit arguments to the hypervisor calls
38 * are volatile across the call. Upon return their values are
39 * undefined unless explicitly specified as containing a particular
40 * return value by the specific call. The return status is always
41 * returned in register %o0, zero indicates a successful execution of
42 * the hypervisor call and other values indicate an error status as
43 * defined below. So, for example, if a hyper-fast trap takes
44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
45 * the call and %o3, %o4, and %o5 would be preserved.
47 * If the hypervisor trap is invalid, or the fast trap function number
48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
49 * of the argument and return values are significant.
53 #define HV_FAST_TRAP 0x80
54 #define HV_MMU_MAP_ADDR_TRAP 0x83
55 #define HV_MMU_UNMAP_ADDR_TRAP 0x84
56 #define HV_TTRACE_ADDENTRY_TRAP 0x85
57 #define HV_CORE_TRAP 0xff
60 #define HV_EOK 0 /* Successful return */
61 #define HV_ENOCPU 1 /* Invalid CPU id */
62 #define HV_ENORADDR 2 /* Invalid real address */
63 #define HV_ENOINTR 3 /* Invalid interrupt id */
64 #define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
65 #define HV_EBADTSB 5 /* Invalid TSB description */
66 #define HV_EINVAL 6 /* Invalid argument */
67 #define HV_EBADTRAP 7 /* Invalid function number */
68 #define HV_EBADALIGN 8 /* Invalid address alignment */
69 #define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
70 #define HV_ENOACCESS 10 /* No access to resource */
71 #define HV_EIO 11 /* I/O error */
72 #define HV_ECPUERROR 12 /* CPU in error state */
73 #define HV_ENOTSUPPORTED 13 /* Function not supported */
74 #define HV_ENOMAP 14 /* No mapping found */
75 #define HV_ETOOMANY 15 /* Too many items specified */
76 #define HV_ECHANNEL 16 /* Invalid LDC channel */
77 #define HV_EBUSY 17 /* Resource busy */
81 * FUNCTION: HV_FAST_MACH_EXIT
83 * ERRORS: This service does not return.
85 * Stop all CPUs in the virtual domain and place them into the stopped
86 * state. The 64-bit exit code may be passed to a service entity as
87 * the domain's exit status. On systems without a service entity, the
88 * domain will undergo a reset, and the boot firmware will be
91 * This function will never return to the guest that invokes it.
93 * Note: By convention an exit code of zero denotes a successful exit by
94 * the guest code. A non-zero exit code denotes a guest specific
98 #define HV_FAST_MACH_EXIT 0x00
101 void sun4v_mach_exit(unsigned long exit_code);
104 /* Domain services. */
108 * FUNCTION: HV_FAST_MACH_DESC
113 * ERRORS: HV_EBADALIGN Buffer is badly aligned
114 * HV_ENORADDR Buffer is to an illegal real address.
115 * HV_EINVAL Buffer length is too small for complete
116 * machine description.
118 * Copy the most current machine description into the buffer indicated
119 * by the real address in ARG0. The buffer provided must be 16 byte
120 * aligned. Upon success or HV_EINVAL, this service returns the
121 * actual size of the machine description in the RET1 return value.
123 * Note: A method of determining the appropriate buffer size for the
124 * machine description is to first call this service with a buffer
127 #define HV_FAST_MACH_DESC 0x01
130 unsigned long sun4v_mach_desc(unsigned long buffer_pa,
131 unsigned long buf_len,
132 unsigned long *real_buf_len);
137 * FUNCTION: HV_FAST_MACH_SIR
138 * ERRORS: This service does not return.
140 * Perform a software initiated reset of the virtual machine domain.
141 * All CPUs are captured as soon as possible, all hardware devices are
142 * returned to the entry default state, and the domain is restarted at
143 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
144 * of the CPUs. The single CPU restarted is selected as determined by
145 * platform specific policy. Memory is preserved across this
148 #define HV_FAST_MACH_SIR 0x02
151 void sun4v_mach_sir(void);
154 /* mach_set_watchdog()
156 * FUNCTION: HV_FAST_MACH_SET_WATCHDOG
157 * ARG0: timeout in milliseconds
159 * RET1: time remaining in milliseconds
161 * A guest uses this API to set a watchdog timer. Once the gues has set
162 * the timer, it must call the timer service again either to disable or
163 * postpone the expiration. If the timer expires before being reset or
164 * disabled, then the hypervisor take a platform specific action leading
165 * to guest termination within a bounded time period. The platform action
166 * may include recovery actions such as reporting the expiration to a
167 * Service Processor, and/or automatically restarting the gues.
169 * The 'timeout' parameter is specified in milliseconds, however the
170 * implementated granularity is given by the 'watchdog-resolution'
171 * property in the 'platform' node of the guest's machine description.
172 * The largest allowed timeout value is specified by the
173 * 'watchdog-max-timeout' property of the 'platform' node.
175 * If the 'timeout' argument is not zero, the watchdog timer is set to
176 * expire after a minimum of 'timeout' milliseconds.
178 * If the 'timeout' argument is zero, the watchdog timer is disabled.
180 * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
181 * property, the hypervisor leaves the watchdog timer state unchanged,
182 * and returns a status of EINVAL.
184 * The 'time remaining' return value is valid regardless of whether the
185 * return status is EOK or EINVAL. A non-zero return value indicates the
186 * number of milliseconds that were remaining until the timer was to expire.
187 * If less than one millisecond remains, the return value is '1'. If the
188 * watchdog timer was disabled at the time of the call, the return value is
191 * If the hypervisor cannot support the exact timeout value requested, but
192 * can support a larger timeout value, the hypervisor may round the actual
193 * timeout to a value larger than the requested timeout, consequently the
194 * 'time remaining' return value may be larger than the previously requested
197 * Any guest OS debugger should be aware that the watchdog service may be in
198 * use. Consequently, it is recommended that the watchdog service is
199 * disabled upon debugger entry (e.g. reaching a breakpoint), and then
200 * re-enabled upon returning to normal execution. The API has been designed
201 * with this in mind, and the 'time remaining' result of the disable call may
202 * be used directly as the timeout argument of the re-enable call.
204 #define HV_FAST_MACH_SET_WATCHDOG 0x05
207 unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
208 unsigned long *orig_timeout);
213 * CPUs represent devices that can execute software threads. A single
214 * chip that contains multiple cores or strands is represented as
215 * multiple CPUs with unique CPU identifiers. CPUs are exported to
216 * OBP via the machine description (and to the OS via the OBP device
217 * tree). CPUs are always in one of three states: stopped, running,
220 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
221 * CPU within a logical domain. Operations that are to be performed
222 * on multiple CPUs specify them via a CPU list. A CPU list is an
223 * array in real memory, of which each 16-bit word is a CPU ID. CPU
224 * lists are passed through the API as two arguments. The first is
225 * the number of entries (16-bit words) in the CPU list, and the
226 * second is the (real address) pointer to the CPU ID list.
231 * FUNCTION: HV_FAST_CPU_START
237 * ERRORS: ENOCPU Invalid CPU ID
238 * EINVAL Target CPU ID is not in the stopped state
239 * ENORADDR Invalid PC or RTBA real address
240 * EBADALIGN Unaligned PC or unaligned RTBA
241 * EWOULDBLOCK Starting resources are not available
243 * Start CPU with given CPU ID with PC in %pc and with a real trap
244 * base address value of RTBA. The indicated CPU must be in the
245 * stopped state. The supplied RTBA must be aligned on a 256 byte
246 * boundary. On successful completion, the specified CPU will be in
247 * the running state and will be supplied with "target ARG0" in %o0
250 #define HV_FAST_CPU_START 0x10
253 unsigned long sun4v_cpu_start(unsigned long cpuid,
261 * FUNCTION: HV_FAST_CPU_STOP
264 * ERRORS: ENOCPU Invalid CPU ID
265 * EINVAL Target CPU ID is the current cpu
266 * EINVAL Target CPU ID is not in the running state
267 * EWOULDBLOCK Stopping resources are not available
268 * ENOTSUPPORTED Not supported on this platform
270 * The specified CPU is stopped. The indicated CPU must be in the
271 * running state. On completion, it will be in the stopped state. It
272 * is not legal to stop the current CPU.
274 * Note: As this service cannot be used to stop the current cpu, this service
275 * may not be used to stop the last running CPU in a domain. To stop
276 * and exit a running domain, a guest must use the mach_exit() service.
278 #define HV_FAST_CPU_STOP 0x11
281 unsigned long sun4v_cpu_stop(unsigned long cpuid);
286 * FUNCTION: HV_FAST_CPU_YIELD
288 * ERRORS: No possible error.
290 * Suspend execution on the current CPU. Execution will resume when
291 * an interrupt (device, %stick_compare, or cross-call) is targeted to
292 * the CPU. On some CPUs, this API may be used by the hypervisor to
293 * save power by disabling hardware strands.
295 #define HV_FAST_CPU_YIELD 0x12
298 unsigned long sun4v_cpu_yield(void);
303 * FUNCTION: HV_FAST_CPU_QCONF
305 * ARG1: base real address
306 * ARG2: number of entries
308 * ERRORS: ENORADDR Invalid base real address
309 * EINVAL Invalid queue or number of entries is less
310 * than 2 or too large.
311 * EBADALIGN Base real address is not correctly aligned
314 * Configure the given queue to be placed at the given base real
315 * address, with the given number of entries. The number of entries
316 * must be a power of 2. The base real address must be aligned
317 * exactly to match the queue size. Each queue entry is 64 bytes
318 * long, so for example a 32 entry queue must be aligned on a 2048
319 * byte real address boundary.
321 * The specified queue is unconfigured if the number of entries is given
324 * For the current version of this API service, the argument queue is defined
328 * ----- -------------------------
329 * 0x3c cpu mondo queue
330 * 0x3d device mondo queue
331 * 0x3e resumable error queue
332 * 0x3f non-resumable error queue
334 * Note: The maximum number of entries for each queue for a specific cpu may
335 * be determined from the machine description.
337 #define HV_FAST_CPU_QCONF 0x14
338 #define HV_CPU_QUEUE_CPU_MONDO 0x3c
339 #define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
340 #define HV_CPU_QUEUE_RES_ERROR 0x3e
341 #define HV_CPU_QUEUE_NONRES_ERROR 0x3f
344 unsigned long sun4v_cpu_qconf(unsigned long type,
345 unsigned long queue_paddr,
346 unsigned long num_queue_entries);
351 * FUNCTION: HV_FAST_CPU_QINFO
354 * RET1: base real address
355 * RET1: number of entries
356 * ERRORS: EINVAL Invalid queue
358 * Return the configuration info for the given queue. The base real
359 * address and number of entries of the defined queue are returned.
360 * The queue argument values are the same as for cpu_qconf() above.
362 * If the specified queue is a valid queue number, but no queue has
363 * been defined, the number of entries will be set to zero and the
364 * base real address returned is undefined.
366 #define HV_FAST_CPU_QINFO 0x15
370 * FUNCTION: HV_FAST_CPU_MONDO_SEND
372 * ARG2: data real address
374 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
375 * is not 2-byte aligned.
376 * ENORADDR Invalid data mondo address, or invalid cpu list
378 * ENOCPU Invalid cpu in CPU list
379 * EWOULDBLOCK Some or all of the listed CPUs did not receive
381 * ECPUERROR One or more of the listed CPUs are in error
382 * state, use HV_FAST_CPU_STATE to see which ones
383 * EINVAL CPU list includes caller's CPU ID
385 * Send a mondo interrupt to the CPUs in the given CPU list with the
386 * 64-bytes at the given data real address. The data must be 64-byte
387 * aligned. The mondo data will be delivered to the cpu_mondo queues
388 * of the recipient CPUs.
390 * In all cases, error or not, the CPUs in the CPU list to which the
391 * mondo has been successfully delivered will be indicated by having
392 * their entry in CPU list updated with the value 0xffff.
394 #define HV_FAST_CPU_MONDO_SEND 0x42
397 unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count,
398 unsigned long cpu_list_pa,
399 unsigned long mondo_block_pa);
404 * FUNCTION: HV_FAST_CPU_MYID
407 * ERRORS: No errors defined.
409 * Return the hypervisor ID handle for the current CPU. Use by a
410 * virtual CPU to discover it's own identity.
412 #define HV_FAST_CPU_MYID 0x16
416 * FUNCTION: HV_FAST_CPU_STATE
420 * ERRORS: ENOCPU Invalid CPU ID
422 * Retrieve the current state of the CPU with the given CPU ID.
424 #define HV_FAST_CPU_STATE 0x17
425 #define HV_CPU_STATE_STOPPED 0x01
426 #define HV_CPU_STATE_RUNNING 0x02
427 #define HV_CPU_STATE_ERROR 0x03
430 long sun4v_cpu_state(unsigned long cpuid);
435 * FUNCTION: HV_FAST_CPU_SET_RTBA
438 * RET1: previous RTBA
439 * ERRORS: ENORADDR Invalid RTBA real address
440 * EBADALIGN RTBA is incorrectly aligned for a trap table
442 * Set the real trap base address of the local cpu to the given RTBA.
443 * The supplied RTBA must be aligned on a 256 byte boundary. Upon
444 * success the previous value of the RTBA is returned in RET1.
446 * Note: This service does not affect %tba
448 #define HV_FAST_CPU_SET_RTBA 0x18
452 * FUNCTION: HV_FAST_CPU_GET_RTBA
454 * RET1: previous RTBA
455 * ERRORS: No possible error.
457 * Returns the current value of RTBA in RET1.
459 #define HV_FAST_CPU_GET_RTBA 0x19
463 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
466 struct hv_tsb_descr {
467 unsigned short pgsz_idx;
468 unsigned short assoc;
469 unsigned int num_ttes; /* in TTEs */
470 unsigned int ctx_idx;
471 unsigned int pgsz_mask;
472 unsigned long tsb_base;
476 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
477 #define HV_TSB_DESCR_ASSOC_OFFSET 0x02
478 #define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
479 #define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
480 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
481 #define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
482 #define HV_TSB_DESCR_RESV_OFFSET 0x18
484 /* Page size bitmask. */
485 #define HV_PGSZ_MASK_8K (1 << 0)
486 #define HV_PGSZ_MASK_64K (1 << 1)
487 #define HV_PGSZ_MASK_512K (1 << 2)
488 #define HV_PGSZ_MASK_4MB (1 << 3)
489 #define HV_PGSZ_MASK_32MB (1 << 4)
490 #define HV_PGSZ_MASK_256MB (1 << 5)
491 #define HV_PGSZ_MASK_2GB (1 << 6)
492 #define HV_PGSZ_MASK_16GB (1 << 7)
494 /* Page size index. The value given in the TSB descriptor must correspond
495 * to the smallest page size specified in the pgsz_mask page size bitmask.
497 #define HV_PGSZ_IDX_8K 0
498 #define HV_PGSZ_IDX_64K 1
499 #define HV_PGSZ_IDX_512K 2
500 #define HV_PGSZ_IDX_4MB 3
501 #define HV_PGSZ_IDX_32MB 4
502 #define HV_PGSZ_IDX_256MB 5
503 #define HV_PGSZ_IDX_2GB 6
504 #define HV_PGSZ_IDX_16GB 7
506 /* MMU fault status area.
508 * MMU related faults have their status and fault address information
509 * placed into a memory region made available by privileged code. Each
510 * virtual processor must make a mmu_fault_area_conf() call to tell the
511 * hypervisor where that processor's fault status should be stored.
513 * The fault status block is a multiple of 64-bytes and must be aligned
514 * on a 64-byte boundary.
517 struct hv_fault_status {
518 unsigned long i_fault_type;
519 unsigned long i_fault_addr;
520 unsigned long i_fault_ctx;
521 unsigned long i_reserved[5];
522 unsigned long d_fault_type;
523 unsigned long d_fault_addr;
524 unsigned long d_fault_ctx;
525 unsigned long d_reserved[5];
528 #define HV_FAULT_I_TYPE_OFFSET 0x00
529 #define HV_FAULT_I_ADDR_OFFSET 0x08
530 #define HV_FAULT_I_CTX_OFFSET 0x10
531 #define HV_FAULT_D_TYPE_OFFSET 0x40
532 #define HV_FAULT_D_ADDR_OFFSET 0x48
533 #define HV_FAULT_D_CTX_OFFSET 0x50
535 #define HV_FAULT_TYPE_FAST_MISS 1
536 #define HV_FAULT_TYPE_FAST_PROT 2
537 #define HV_FAULT_TYPE_MMU_MISS 3
538 #define HV_FAULT_TYPE_INV_RA 4
539 #define HV_FAULT_TYPE_PRIV_VIOL 5
540 #define HV_FAULT_TYPE_PROT_VIOL 6
541 #define HV_FAULT_TYPE_NFO 7
542 #define HV_FAULT_TYPE_NFO_SEFF 8
543 #define HV_FAULT_TYPE_INV_VA 9
544 #define HV_FAULT_TYPE_INV_ASI 10
545 #define HV_FAULT_TYPE_NC_ATOMIC 11
546 #define HV_FAULT_TYPE_PRIV_ACT 12
547 #define HV_FAULT_TYPE_RESV1 13
548 #define HV_FAULT_TYPE_UNALIGNED 14
549 #define HV_FAULT_TYPE_INV_PGSZ 15
550 /* Values 16 --> -2 are reserved. */
551 #define HV_FAULT_TYPE_MULTIPLE -1
553 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
554 * and mmu_{map,unmap}_perm_addr().
556 #define HV_MMU_DMMU 0x01
557 #define HV_MMU_IMMU 0x02
558 #define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
561 * TRAP: HV_MMU_MAP_ADDR_TRAP
562 * ARG0: virtual address
565 * ARG3: flags (HV_MMU_{IMMU,DMMU})
566 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
567 * EBADPGSZ Invalid page size value
568 * ENORADDR Invalid real address in TTE
570 * Create a non-permanent mapping using the given TTE, virtual
571 * address, and mmu context. The flags argument determines which
572 * (data, or instruction, or both) TLB the mapping gets loaded into.
574 * The behavior is undefined if the valid bit is clear in the TTE.
576 * Note: This API call is for privileged code to specify temporary translation
577 * mappings without the need to create and manage a TSB.
581 * TRAP: HV_MMU_UNMAP_ADDR_TRAP
582 * ARG0: virtual address
584 * ARG2: flags (HV_MMU_{IMMU,DMMU})
585 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
587 * Demaps the given virtual address in the given mmu context on this
588 * CPU. This function is intended to be used to demap pages mapped
589 * with mmu_map_addr. This service is equivalent to invoking
590 * mmu_demap_page() with only the current CPU in the CPU list. The
591 * flags argument determines which (data, or instruction, or both) TLB
592 * the mapping gets unmapped from.
594 * Attempting to perform an unmap operation for a previously defined
595 * permanent mapping will have undefined results.
600 * FUNCTION: HV_FAST_MMU_TSB_CTX0
601 * ARG0: number of TSB descriptions
602 * ARG1: TSB descriptions pointer
604 * ERRORS: ENORADDR Invalid TSB descriptions pointer or
605 * TSB base within a descriptor
606 * EBADALIGN TSB descriptions pointer is not aligned
607 * to an 8-byte boundary, or TSB base
608 * within a descriptor is not aligned for
610 * EBADPGSZ Invalid page size in a TSB descriptor
611 * EBADTSB Invalid associativity or size in a TSB
613 * EINVAL Invalid number of TSB descriptions, or
614 * invalid context index in a TSB
615 * descriptor, or index page size not
616 * equal to smallest page size in page
617 * size bitmask field.
619 * Configures the TSBs for the current CPU for virtual addresses with
620 * context zero. The TSB descriptions pointer is a pointer to an
621 * array of the given number of TSB descriptions.
623 * Note: The maximum number of TSBs available to a virtual CPU is given by the
624 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
625 * machine description.
627 #define HV_FAST_MMU_TSB_CTX0 0x20
630 unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
631 unsigned long tsb_desc_ra);
636 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
637 * ARG0: number of TSB descriptions
638 * ARG1: TSB descriptions pointer
640 * ERRORS: Same as for mmu_tsb_ctx0() above.
642 * Configures the TSBs for the current CPU for virtual addresses with
643 * non-zero contexts. The TSB descriptions pointer is a pointer to an
644 * array of the given number of TSB descriptions.
646 * Note: A maximum of 16 TSBs may be specified in the TSB description list.
648 #define HV_FAST_MMU_TSB_CTXNON0 0x21
652 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
653 * ARG0: reserved, must be zero
654 * ARG1: reserved, must be zero
655 * ARG2: virtual address
657 * ARG4: flags (HV_MMU_{IMMU,DMMU})
659 * ERRORS: EINVAL Invalid virtual address, context, or
661 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
663 * Demaps any page mapping of the given virtual address in the given
664 * mmu context for the current virtual CPU. Any virtually tagged
665 * caches are guaranteed to be kept consistent. The flags argument
666 * determines which TLB (instruction, or data, or both) participate in
669 * ARG0 and ARG1 are both reserved and must be set to zero.
671 #define HV_FAST_MMU_DEMAP_PAGE 0x22
675 * FUNCTION: HV_FAST_MMU_DEMAP_CTX
676 * ARG0: reserved, must be zero
677 * ARG1: reserved, must be zero
679 * ARG3: flags (HV_MMU_{IMMU,DMMU})
681 * ERRORS: EINVAL Invalid context or flags value
682 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
684 * Demaps all non-permanent virtual page mappings previously specified
685 * for the given context for the current virtual CPU. Any virtual
686 * tagged caches are guaranteed to be kept consistent. The flags
687 * argument determines which TLB (instruction, or data, or both)
688 * participate in the operation.
690 * ARG0 and ARG1 are both reserved and must be set to zero.
692 #define HV_FAST_MMU_DEMAP_CTX 0x23
696 * FUNCTION: HV_FAST_MMU_DEMAP_ALL
697 * ARG0: reserved, must be zero
698 * ARG1: reserved, must be zero
699 * ARG2: flags (HV_MMU_{IMMU,DMMU})
701 * ERRORS: EINVAL Invalid flags value
702 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
704 * Demaps all non-permanent virtual page mappings previously specified
705 * for the current virtual CPU. Any virtual tagged caches are
706 * guaranteed to be kept consistent. The flags argument determines
707 * which TLB (instruction, or data, or both) participate in the
710 * ARG0 and ARG1 are both reserved and must be set to zero.
712 #define HV_FAST_MMU_DEMAP_ALL 0x24
715 void sun4v_mmu_demap_all(void);
718 /* mmu_map_perm_addr()
720 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
721 * ARG0: virtual address
722 * ARG1: reserved, must be zero
724 * ARG3: flags (HV_MMU_{IMMU,DMMU})
726 * ERRORS: EINVAL Invalid virtual address or flags value
727 * EBADPGSZ Invalid page size value
728 * ENORADDR Invalid real address in TTE
729 * ETOOMANY Too many mappings (max of 8 reached)
731 * Create a permanent mapping using the given TTE and virtual address
732 * for context 0 on the calling virtual CPU. A maximum of 8 such
733 * permanent mappings may be specified by privileged code. Mappings
734 * may be removed with mmu_unmap_perm_addr().
736 * The behavior is undefined if a TTE with the valid bit clear is given.
738 * Note: This call is used to specify address space mappings for which
739 * privileged code does not expect to receive misses. For example,
740 * this mechanism can be used to map kernel nucleus code and data.
742 #define HV_FAST_MMU_MAP_PERM_ADDR 0x25
745 unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
746 unsigned long set_to_zero,
748 unsigned long flags);
751 /* mmu_fault_area_conf()
753 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
756 * RET1: previous mmu fault area real address
757 * ERRORS: ENORADDR Invalid real address
758 * EBADALIGN Invalid alignment for fault area
760 * Configure the MMU fault status area for the calling CPU. A 64-byte
761 * aligned real address specifies where MMU fault status information
762 * is placed. The return value is the previously specified area, or 0
763 * for the first invocation. Specifying a fault area at real address
766 #define HV_FAST_MMU_FAULT_AREA_CONF 0x26
770 * FUNCTION: HV_FAST_MMU_ENABLE
772 * ARG1: return target address
774 * ERRORS: ENORADDR Invalid real address when disabling
776 * EBADALIGN The return target address is not
777 * aligned to an instruction.
778 * EINVAL The enable flag request the current
779 * operating mode (e.g. disable if already
782 * Enable or disable virtual address translation for the calling CPU
783 * within the virtual machine domain. If the enable flag is zero,
784 * translation is disabled, any non-zero value will enable
787 * When this function returns, the newly selected translation mode
788 * will be active. If the mmu is being enabled, then the return
789 * target address is a virtual address else it is a real address.
791 * Upon successful completion, control will be returned to the given
792 * return target address (ie. the cpu will jump to that address). On
793 * failure, the previous mmu mode remains and the trap simply returns
794 * as normal with the appropriate error code in RET0.
796 #define HV_FAST_MMU_ENABLE 0x27
798 /* mmu_unmap_perm_addr()
800 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
801 * ARG0: virtual address
802 * ARG1: reserved, must be zero
803 * ARG2: flags (HV_MMU_{IMMU,DMMU})
805 * ERRORS: EINVAL Invalid virtual address or flags value
806 * ENOMAP Specified mapping was not found
808 * Demaps any permanent page mapping (established via
809 * mmu_map_perm_addr()) at the given virtual address for context 0 on
810 * the current virtual CPU. Any virtual tagged caches are guaranteed
811 * to be kept consistent.
813 #define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
815 /* mmu_tsb_ctx0_info()
817 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
819 * ARG1: buffer pointer
821 * RET1: number of TSBs
822 * ERRORS: EINVAL Supplied buffer is too small
823 * EBADALIGN The buffer pointer is badly aligned
824 * ENORADDR Invalid real address for buffer pointer
826 * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
827 * into the provided buffer. The size of the buffer is given in ARG1
828 * in terms of the number of TSB description entries.
830 * Upon return, RET1 always contains the number of TSB descriptions
831 * previously configured. If zero TSBs were configured, EOK is
832 * returned with RET1 containing 0.
834 #define HV_FAST_MMU_TSB_CTX0_INFO 0x29
836 /* mmu_tsb_ctxnon0_info()
838 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
840 * ARG1: buffer pointer
842 * RET1: number of TSBs
843 * ERRORS: EINVAL Supplied buffer is too small
844 * EBADALIGN The buffer pointer is badly aligned
845 * ENORADDR Invalid real address for buffer pointer
847 * Return the TSB configuration as previous defined by
848 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
849 * is given in ARG1 in terms of the number of TSB description entries.
851 * Upon return, RET1 always contains the number of TSB descriptions
852 * previously configured. If zero TSBs were configured, EOK is
853 * returned with RET1 containing 0.
855 #define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
857 /* mmu_fault_area_info()
859 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
861 * RET1: fault area real address
862 * ERRORS: No errors defined.
864 * Return the currently defined MMU fault status area for the current
865 * CPU. The real address of the fault status area is returned in
866 * RET1, or 0 is returned in RET1 if no fault status area is defined.
868 * Note: mmu_fault_area_conf() may be called with the return value (RET1)
869 * from this service if there is a need to save and restore the fault
872 #define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
874 /* Cache and Memory services. */
878 * FUNCTION: HV_FAST_MEM_SCRUB
882 * RET1: length scrubbed
883 * ERRORS: ENORADDR Invalid real address
884 * EBADALIGN Start address or length are not correctly
886 * EINVAL Length is zero
888 * Zero the memory contents in the range real address to real address
889 * plus length minus 1. Also, valid ECC will be generated for that
890 * memory address range. Scrubbing is started at the given real
891 * address, but may not scrub the entire given length. The actual
892 * length scrubbed will be returned in RET1.
894 * The real address and length must be aligned on an 8K boundary, or
895 * contain the start address and length from a sun4v error report.
897 * Note: There are two uses for this function. The first use is to block clear
898 * and initialize memory and the second is to scrub an u ncorrectable
899 * error reported via a resumable or non-resumable trap. The second
900 * use requires the arguments to be equal to the real address and length
901 * provided in a sun4v memory error report.
903 #define HV_FAST_MEM_SCRUB 0x31
907 * FUNCTION: HV_FAST_MEM_SYNC
911 * RET1: length synced
912 * ERRORS: ENORADDR Invalid real address
913 * EBADALIGN Start address or length are not correctly
915 * EINVAL Length is zero
917 * Force the next access within the real address to real address plus
918 * length minus 1 to be fetches from main system memory. Less than
919 * the given length may be synced, the actual amount synced is
920 * returned in RET1. The real address and length must be aligned on
923 #define HV_FAST_MEM_SYNC 0x32
925 /* Time of day services.
927 * The hypervisor maintains the time of day on a per-domain basis.
928 * Changing the time of day in one domain does not affect the time of
929 * day on any other domain.
931 * Time is described by a single unsigned 64-bit word which is the
932 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
938 * FUNCTION: HV_FAST_TOD_GET
941 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
942 * ENOTSUPPORTED If TOD not supported on this platform
944 * Return the current time of day. May block if TOD access is
945 * temporarily not possible.
947 #define HV_FAST_TOD_GET 0x50
950 unsigned long sun4v_tod_get(unsigned long *time);
955 * FUNCTION: HV_FAST_TOD_SET
958 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
959 * ENOTSUPPORTED If TOD not supported on this platform
961 * The current time of day is set to the value specified in ARG0. May
962 * block if TOD access is temporarily not possible.
964 #define HV_FAST_TOD_SET 0x51
967 unsigned long sun4v_tod_set(unsigned long time);
970 /* Console services */
974 * FUNCTION: HV_FAST_CONS_GETCHAR
977 * ERRORS: EWOULDBLOCK No character available.
979 * Returns a character from the console device. If no character is
980 * available then an EWOULDBLOCK error is returned. If a character is
981 * available, then the returned status is EOK and the character value
984 * A virtual BREAK is represented by the 64-bit value -1.
986 * A virtual HUP signal is represented by the 64-bit value -2.
988 #define HV_FAST_CONS_GETCHAR 0x60
992 * FUNCTION: HV_FAST_CONS_PUTCHAR
995 * ERRORS: EINVAL Illegal character
996 * EWOULDBLOCK Output buffer currently full, would block
998 * Send a character to the console device. Only character values
999 * between 0 and 255 may be used. Values outside this range are
1000 * invalid except for the 64-bit value -1 which is used to send a
1003 #define HV_FAST_CONS_PUTCHAR 0x61
1006 * TRAP: HV_FAST_TRAP
1007 * FUNCTION: HV_FAST_CONS_READ
1008 * ARG0: buffer real address
1009 * ARG1: buffer size in bytes
1011 * RET1: bytes read or BREAK or HUP
1012 * ERRORS: EWOULDBLOCK No character available.
1014 * Reads characters into a buffer from the console device. If no
1015 * character is available then an EWOULDBLOCK error is returned.
1016 * If a character is available, then the returned status is EOK
1017 * and the number of bytes read into the given buffer is provided
1020 * A virtual BREAK is represented by the 64-bit RET1 value -1.
1022 * A virtual HUP signal is represented by the 64-bit RET1 value -2.
1024 * If BREAK or HUP are indicated, no bytes were read into buffer.
1026 #define HV_FAST_CONS_READ 0x62
1029 * TRAP: HV_FAST_TRAP
1030 * FUNCTION: HV_FAST_CONS_WRITE
1031 * ARG0: buffer real address
1032 * ARG1: buffer size in bytes
1034 * RET1: bytes written
1035 * ERRORS: EWOULDBLOCK Output buffer currently full, would block
1037 * Send a characters in buffer to the console device. Breaks must be
1038 * sent using con_putchar().
1040 #define HV_FAST_CONS_WRITE 0x63
1042 #ifndef __ASSEMBLY__
1043 long sun4v_con_getchar(long *status);
1044 long sun4v_con_putchar(long c);
1045 long sun4v_con_read(unsigned long buffer,
1047 unsigned long *bytes_read);
1048 unsigned long sun4v_con_write(unsigned long buffer,
1050 unsigned long *bytes_written);
1053 /* mach_set_soft_state()
1054 * TRAP: HV_FAST_TRAP
1055 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
1056 * ARG0: software state
1057 * ARG1: software state description pointer
1059 * ERRORS: EINVAL software state not valid or software state
1060 * description is not NULL terminated
1061 * ENORADDR software state description pointer is not a
1062 * valid real address
1063 * EBADALIGNED software state description is not correctly
1066 * This allows the guest to report it's soft state to the hypervisor. There
1067 * are two primary components to this state. The first part states whether
1068 * the guest software is running or not. The second containts optional
1069 * details specific to the software.
1071 * The software state argument is defined below in HV_SOFT_STATE_*, and
1072 * indicates whether the guest is operating normally or in a transitional
1075 * The software state description argument is a real address of a data buffer
1076 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
1077 * terminated 7-bit ASCII string of up to 31 characters not including the
1080 #define HV_FAST_MACH_SET_SOFT_STATE 0x70
1081 #define HV_SOFT_STATE_NORMAL 0x01
1082 #define HV_SOFT_STATE_TRANSITION 0x02
1084 #ifndef __ASSEMBLY__
1085 unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
1086 unsigned long msg_string_ra);
1089 /* mach_get_soft_state()
1090 * TRAP: HV_FAST_TRAP
1091 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
1092 * ARG0: software state description pointer
1094 * RET1: software state
1095 * ERRORS: ENORADDR software state description pointer is not a
1096 * valid real address
1097 * EBADALIGNED software state description is not correctly
1100 * Retrieve the current value of the guest's software state. The rules
1101 * for the software state pointer are the same as for mach_set_soft_state()
1104 #define HV_FAST_MACH_GET_SOFT_STATE 0x71
1107 * TRAP: HV_FAST_TRAP
1108 * FUNCTION: HV_FAST_SVC_SEND
1110 * ARG1: buffer real address
1115 * Be careful, all output registers are clobbered by this operation,
1116 * so for example it is not possible to save away a value in %o4
1119 #define HV_FAST_SVC_SEND 0x80
1122 * TRAP: HV_FAST_TRAP
1123 * FUNCTION: HV_FAST_SVC_RECV
1125 * ARG1: buffer real address
1130 * Be careful, all output registers are clobbered by this operation,
1131 * so for example it is not possible to save away a value in %o4
1134 #define HV_FAST_SVC_RECV 0x81
1137 * TRAP: HV_FAST_TRAP
1138 * FUNCTION: HV_FAST_SVC_GETSTATUS
1143 #define HV_FAST_SVC_GETSTATUS 0x82
1146 * TRAP: HV_FAST_TRAP
1147 * FUNCTION: HV_FAST_SVC_SETSTATUS
1152 #define HV_FAST_SVC_SETSTATUS 0x83
1155 * TRAP: HV_FAST_TRAP
1156 * FUNCTION: HV_FAST_SVC_CLRSTATUS
1158 * ARG1: bits to clear
1161 #define HV_FAST_SVC_CLRSTATUS 0x84
1163 #ifndef __ASSEMBLY__
1164 unsigned long sun4v_svc_send(unsigned long svc_id,
1165 unsigned long buffer,
1166 unsigned long buffer_size,
1167 unsigned long *sent_bytes);
1168 unsigned long sun4v_svc_recv(unsigned long svc_id,
1169 unsigned long buffer,
1170 unsigned long buffer_size,
1171 unsigned long *recv_bytes);
1172 unsigned long sun4v_svc_getstatus(unsigned long svc_id,
1173 unsigned long *status_bits);
1174 unsigned long sun4v_svc_setstatus(unsigned long svc_id,
1175 unsigned long status_bits);
1176 unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
1177 unsigned long status_bits);
1180 /* Trap trace services.
1182 * The hypervisor provides a trap tracing capability for privileged
1183 * code running on each virtual CPU. Privileged code provides a
1184 * round-robin trap trace queue within which the hypervisor writes
1185 * 64-byte entries detailing hyperprivileged traps taken n behalf of
1186 * privileged code. This is provided as a debugging capability for
1189 * The trap trace control structure is 64-bytes long and placed at the
1190 * start (offset 0) of the trap trace buffer, and is described as
1193 #ifndef __ASSEMBLY__
1194 struct hv_trap_trace_control {
1195 unsigned long head_offset;
1196 unsigned long tail_offset;
1197 unsigned long __reserved[0x30 / sizeof(unsigned long)];
1200 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
1201 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
1203 /* The head offset is the offset of the most recently completed entry
1204 * in the trap-trace buffer. The tail offset is the offset of the
1205 * next entry to be written. The control structure is owned and
1206 * modified by the hypervisor. A guest may not modify the control
1207 * structure contents. Attempts to do so will result in undefined
1208 * behavior for the guest.
1210 * Each trap trace buffer entry is laid out as follows:
1212 #ifndef __ASSEMBLY__
1213 struct hv_trap_trace_entry {
1214 unsigned char type; /* Hypervisor or guest entry? */
1215 unsigned char hpstate; /* Hyper-privileged state */
1216 unsigned char tl; /* Trap level */
1217 unsigned char gl; /* Global register level */
1218 unsigned short tt; /* Trap type */
1219 unsigned short tag; /* Extended trap identifier */
1220 unsigned long tstate; /* Trap state */
1221 unsigned long tick; /* Tick */
1222 unsigned long tpc; /* Trap PC */
1223 unsigned long f1; /* Entry specific */
1224 unsigned long f2; /* Entry specific */
1225 unsigned long f3; /* Entry specific */
1226 unsigned long f4; /* Entry specific */
1229 #define HV_TRAP_TRACE_ENTRY_TYPE 0x00
1230 #define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
1231 #define HV_TRAP_TRACE_ENTRY_TL 0x02
1232 #define HV_TRAP_TRACE_ENTRY_GL 0x03
1233 #define HV_TRAP_TRACE_ENTRY_TT 0x04
1234 #define HV_TRAP_TRACE_ENTRY_TAG 0x06
1235 #define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
1236 #define HV_TRAP_TRACE_ENTRY_TICK 0x10
1237 #define HV_TRAP_TRACE_ENTRY_TPC 0x18
1238 #define HV_TRAP_TRACE_ENTRY_F1 0x20
1239 #define HV_TRAP_TRACE_ENTRY_F2 0x28
1240 #define HV_TRAP_TRACE_ENTRY_F3 0x30
1241 #define HV_TRAP_TRACE_ENTRY_F4 0x38
1243 /* The type field is encoded as follows. */
1244 #define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
1245 #define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
1246 #define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
1248 /* ttrace_buf_conf()
1249 * TRAP: HV_FAST_TRAP
1250 * FUNCTION: HV_FAST_TTRACE_BUF_CONF
1251 * ARG0: real address
1252 * ARG1: number of entries
1254 * RET1: number of entries
1255 * ERRORS: ENORADDR Invalid real address
1256 * EINVAL Size is too small
1257 * EBADALIGN Real address not aligned on 64-byte boundary
1259 * Requests hypervisor trap tracing and declares a virtual CPU's trap
1260 * trace buffer to the hypervisor. The real address supplies the real
1261 * base address of the trap trace queue and must be 64-byte aligned.
1262 * Specifying a value of 0 for the number of entries disables trap
1263 * tracing for the calling virtual CPU. The buffer allocated must be
1264 * sized for a power of two number of 64-byte trap trace entries plus
1265 * an initial 64-byte control structure.
1267 * This may be invoked any number of times so that a virtual CPU may
1268 * relocate a trap trace buffer or create "snapshots" of information.
1270 * If the real address is illegal or badly aligned, then trap tracing
1271 * is disabled and an error is returned.
1273 * Upon failure with EINVAL, this service call returns in RET1 the
1274 * minimum number of buffer entries required. Upon other failures
1275 * RET1 is undefined.
1277 #define HV_FAST_TTRACE_BUF_CONF 0x90
1279 /* ttrace_buf_info()
1280 * TRAP: HV_FAST_TRAP
1281 * FUNCTION: HV_FAST_TTRACE_BUF_INFO
1283 * RET1: real address
1285 * ERRORS: None defined.
1287 * Returns the size and location of the previously declared trap-trace
1288 * buffer. In the event that no buffer was previously defined, or the
1289 * buffer is disabled, this call will return a size of zero bytes.
1291 #define HV_FAST_TTRACE_BUF_INFO 0x91
1294 * TRAP: HV_FAST_TRAP
1295 * FUNCTION: HV_FAST_TTRACE_ENABLE
1298 * RET1: previous enable state
1299 * ERRORS: EINVAL No trap trace buffer currently defined
1301 * Enable or disable trap tracing, and return the previous enabled
1302 * state in RET1. Future systems may define various flags for the
1303 * enable argument (ARG0), for the moment a guest should pass
1304 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1305 * tracing - which will ensure future compatibility.
1307 #define HV_FAST_TTRACE_ENABLE 0x92
1310 * TRAP: HV_FAST_TRAP
1311 * FUNCTION: HV_FAST_TTRACE_FREEZE
1314 * RET1: previous freeze state
1315 * ERRORS: EINVAL No trap trace buffer currently defined
1317 * Freeze or unfreeze trap tracing, returning the previous freeze
1318 * state in RET1. A guest should pass a non-zero value to freeze and
1319 * a zero value to unfreeze all tracing. The returned previous state
1320 * is 0 for not frozen and 1 for frozen.
1322 #define HV_FAST_TTRACE_FREEZE 0x93
1324 /* ttrace_addentry()
1325 * TRAP: HV_TTRACE_ADDENTRY_TRAP
1326 * ARG0: tag (16-bits)
1332 * ERRORS: EINVAL No trap trace buffer currently defined
1334 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
1335 * is modified - none of the other registers holding arguments are
1336 * volatile across this hypervisor service.
1339 /* Core dump services.
1341 * Since the hypervisor viraulizes and thus obscures a lot of the
1342 * physical machine layout and state, traditional OS crash dumps can
1343 * be difficult to diagnose especially when the problem is a
1344 * configuration error of some sort.
1346 * The dump services provide an opaque buffer into which the
1347 * hypervisor can place it's internal state in order to assist in
1348 * debugging such situations. The contents are opaque and extremely
1349 * platform and hypervisor implementation specific. The guest, during
1350 * a core dump, requests that the hypervisor update any information in
1351 * the dump buffer in preparation to being dumped as part of the
1352 * domain's memory image.
1355 /* dump_buf_update()
1356 * TRAP: HV_FAST_TRAP
1357 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
1358 * ARG0: real address
1361 * RET1: required size of dump buffer
1362 * ERRORS: ENORADDR Invalid real address
1363 * EBADALIGN Real address is not aligned on a 64-byte
1365 * EINVAL Size is non-zero but less than minimum size
1367 * ENOTSUPPORTED Operation not supported on current logical
1370 * Declare a domain dump buffer to the hypervisor. The real address
1371 * provided for the domain dump buffer must be 64-byte aligned. The
1372 * size specifies the size of the dump buffer and may be larger than
1373 * the minimum size specified in the machine description. The
1374 * hypervisor will fill the dump buffer with opaque data.
1376 * Note: A guest may elect to include dump buffer contents as part of a crash
1377 * dump to assist with debugging. This function may be called any number
1378 * of times so that a guest may relocate a dump buffer, or create
1379 * "snapshots" of any dump-buffer information. Each call to
1380 * dump_buf_update() atomically declares the new dump buffer to the
1383 * A specified size of 0 unconfigures the dump buffer. If the real
1384 * address is illegal or badly aligned, then any currently active dump
1385 * buffer is disabled and an error is returned.
1387 * In the event that the call fails with EINVAL, RET1 contains the
1388 * minimum size requires by the hypervisor for a valid dump buffer.
1390 #define HV_FAST_DUMP_BUF_UPDATE 0x94
1393 * TRAP: HV_FAST_TRAP
1394 * FUNCTION: HV_FAST_DUMP_BUF_INFO
1396 * RET1: real address of current dump buffer
1397 * RET2: size of current dump buffer
1398 * ERRORS: No errors defined.
1400 * Return the currently configures dump buffer description. A
1401 * returned size of 0 bytes indicates an undefined dump buffer. In
1402 * this case the return address in RET1 is undefined.
1404 #define HV_FAST_DUMP_BUF_INFO 0x95
1406 /* Device interrupt services.
1408 * Device interrupts are allocated to system bus bridges by the hypervisor,
1409 * and described to OBP in the machine description. OBP then describes
1410 * these interrupts to the OS via properties in the device tree.
1414 * cpuid Unique opaque value which represents a target cpu.
1416 * devhandle Device handle. It uniquely identifies a device, and
1417 * consistes of the lower 28-bits of the hi-cell of the
1418 * first entry of the device's "reg" property in the
1421 * devino Device interrupt number. Specifies the relative
1422 * interrupt number within the device. The unique
1423 * combination of devhandle and devino are used to
1424 * identify a specific device interrupt.
1426 * Note: The devino value is the same as the values in the
1427 * "interrupts" property or "interrupt-map" property
1428 * in the OBP device tree for that device.
1430 * sysino System interrupt number. A 64-bit unsigned interger
1431 * representing a unique interrupt within a virtual
1434 * intr_state A flag representing the interrupt state for a given
1435 * sysino. The state values are defined below.
1437 * intr_enabled A flag representing the 'enabled' state for a given
1438 * sysino. The enable values are defined below.
1441 #define HV_INTR_STATE_IDLE 0 /* Nothing pending */
1442 #define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
1443 #define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
1445 #define HV_INTR_DISABLED 0 /* sysino not enabled */
1446 #define HV_INTR_ENABLED 1 /* sysino enabled */
1448 /* intr_devino_to_sysino()
1449 * TRAP: HV_FAST_TRAP
1450 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
1455 * ERRORS: EINVAL Invalid devhandle/devino
1457 * Converts a device specific interrupt number of the given
1458 * devhandle/devino into a system specific ino (sysino).
1460 #define HV_FAST_INTR_DEVINO2SYSINO 0xa0
1462 #ifndef __ASSEMBLY__
1463 unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1464 unsigned long devino);
1467 /* intr_getenabled()
1468 * TRAP: HV_FAST_TRAP
1469 * FUNCTION: HV_FAST_INTR_GETENABLED
1472 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1473 * ERRORS: EINVAL Invalid sysino
1475 * Returns interrupt enabled state in RET1 for the interrupt defined
1476 * by the given sysino.
1478 #define HV_FAST_INTR_GETENABLED 0xa1
1480 #ifndef __ASSEMBLY__
1481 unsigned long sun4v_intr_getenabled(unsigned long sysino);
1484 /* intr_setenabled()
1485 * TRAP: HV_FAST_TRAP
1486 * FUNCTION: HV_FAST_INTR_SETENABLED
1488 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1490 * ERRORS: EINVAL Invalid sysino or intr_enabled value
1492 * Set the 'enabled' state of the interrupt sysino.
1494 #define HV_FAST_INTR_SETENABLED 0xa2
1496 #ifndef __ASSEMBLY__
1497 unsigned long sun4v_intr_setenabled(unsigned long sysino,
1498 unsigned long intr_enabled);
1502 * TRAP: HV_FAST_TRAP
1503 * FUNCTION: HV_FAST_INTR_GETSTATE
1506 * RET1: intr_state (HV_INTR_STATE_*)
1507 * ERRORS: EINVAL Invalid sysino
1509 * Returns current state of the interrupt defined by the given sysino.
1511 #define HV_FAST_INTR_GETSTATE 0xa3
1513 #ifndef __ASSEMBLY__
1514 unsigned long sun4v_intr_getstate(unsigned long sysino);
1518 * TRAP: HV_FAST_TRAP
1519 * FUNCTION: HV_FAST_INTR_SETSTATE
1521 * ARG1: intr_state (HV_INTR_STATE_*)
1523 * ERRORS: EINVAL Invalid sysino or intr_state value
1525 * Sets the current state of the interrupt described by the given sysino
1528 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1529 * interrupt for sysino.
1531 #define HV_FAST_INTR_SETSTATE 0xa4
1533 #ifndef __ASSEMBLY__
1534 unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1538 * TRAP: HV_FAST_TRAP
1539 * FUNCTION: HV_FAST_INTR_GETTARGET
1543 * ERRORS: EINVAL Invalid sysino
1545 * Returns CPU that is the current target of the interrupt defined by
1546 * the given sysino. The CPU value returned is undefined if the target
1547 * has not been set via intr_settarget().
1549 #define HV_FAST_INTR_GETTARGET 0xa5
1551 #ifndef __ASSEMBLY__
1552 unsigned long sun4v_intr_gettarget(unsigned long sysino);
1556 * TRAP: HV_FAST_TRAP
1557 * FUNCTION: HV_FAST_INTR_SETTARGET
1561 * ERRORS: EINVAL Invalid sysino
1562 * ENOCPU Invalid cpuid
1564 * Set the target CPU for the interrupt defined by the given sysino.
1566 #define HV_FAST_INTR_SETTARGET 0xa6
1568 #ifndef __ASSEMBLY__
1569 unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1572 /* vintr_get_cookie()
1573 * TRAP: HV_FAST_TRAP
1574 * FUNCTION: HV_FAST_VINTR_GET_COOKIE
1575 * ARG0: device handle
1580 #define HV_FAST_VINTR_GET_COOKIE 0xa7
1582 /* vintr_set_cookie()
1583 * TRAP: HV_FAST_TRAP
1584 * FUNCTION: HV_FAST_VINTR_SET_COOKIE
1585 * ARG0: device handle
1590 #define HV_FAST_VINTR_SET_COOKIE 0xa8
1592 /* vintr_get_valid()
1593 * TRAP: HV_FAST_TRAP
1594 * FUNCTION: HV_FAST_VINTR_GET_VALID
1595 * ARG0: device handle
1600 #define HV_FAST_VINTR_GET_VALID 0xa9
1602 /* vintr_set_valid()
1603 * TRAP: HV_FAST_TRAP
1604 * FUNCTION: HV_FAST_VINTR_SET_VALID
1605 * ARG0: device handle
1610 #define HV_FAST_VINTR_SET_VALID 0xaa
1612 /* vintr_get_state()
1613 * TRAP: HV_FAST_TRAP
1614 * FUNCTION: HV_FAST_VINTR_GET_STATE
1615 * ARG0: device handle
1620 #define HV_FAST_VINTR_GET_STATE 0xab
1622 /* vintr_set_state()
1623 * TRAP: HV_FAST_TRAP
1624 * FUNCTION: HV_FAST_VINTR_SET_STATE
1625 * ARG0: device handle
1630 #define HV_FAST_VINTR_SET_STATE 0xac
1632 /* vintr_get_target()
1633 * TRAP: HV_FAST_TRAP
1634 * FUNCTION: HV_FAST_VINTR_GET_TARGET
1635 * ARG0: device handle
1640 #define HV_FAST_VINTR_GET_TARGET 0xad
1642 /* vintr_set_target()
1643 * TRAP: HV_FAST_TRAP
1644 * FUNCTION: HV_FAST_VINTR_SET_TARGET
1645 * ARG0: device handle
1650 #define HV_FAST_VINTR_SET_TARGET 0xae
1652 #ifndef __ASSEMBLY__
1653 unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
1654 unsigned long dev_ino,
1655 unsigned long *cookie);
1656 unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
1657 unsigned long dev_ino,
1658 unsigned long cookie);
1659 unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
1660 unsigned long dev_ino,
1661 unsigned long *valid);
1662 unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
1663 unsigned long dev_ino,
1664 unsigned long valid);
1665 unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
1666 unsigned long dev_ino,
1667 unsigned long *state);
1668 unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
1669 unsigned long dev_ino,
1670 unsigned long state);
1671 unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
1672 unsigned long dev_ino,
1673 unsigned long *cpuid);
1674 unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1675 unsigned long dev_ino,
1676 unsigned long cpuid);
1681 * See the terminology descriptions in the device interrupt services
1682 * section above as those apply here too. Here are terminology
1683 * definitions specific to these PCI IO services:
1685 * tsbnum TSB number. Indentifies which io-tsb is used.
1686 * For this version of the specification, tsbnum
1689 * tsbindex TSB index. Identifies which entry in the TSB
1690 * is used. The first entry is zero.
1692 * tsbid A 64-bit aligned data structure which contains
1693 * a tsbnum and a tsbindex. Bits 63:32 contain the
1694 * tsbnum and bits 31:00 contain the tsbindex.
1696 * Use the HV_PCI_TSBID() macro to construct such
1699 * io_attributes IO attributes for IOMMU mappings. One of more
1700 * of the attritbute bits are stores in a 64-bit
1701 * value. The values are defined below.
1703 * r_addr 64-bit real address
1705 * pci_device PCI device address. A PCI device address identifies
1706 * a specific device on a specific PCI bus segment.
1707 * A PCI device address ia a 32-bit unsigned integer
1708 * with the following format:
1710 * 00000000.bbbbbbbb.dddddfff.00000000
1712 * Use the HV_PCI_DEVICE_BUILD() macro to construct
1716 * PCI configureation space offset. For conventional
1717 * PCI a value between 0 and 255. For extended
1718 * configuration space, a value between 0 and 4095.
1720 * Note: For PCI configuration space accesses, the offset
1721 * must be aligned to the access size.
1723 * error_flag A return value which specifies if the action succeeded
1724 * or failed. 0 means no error, non-0 means some error
1725 * occurred while performing the service.
1728 * Direction definition for pci_dma_sync(), defined
1729 * below in HV_PCI_SYNC_*.
1731 * io_page_list A list of io_page_addresses, an io_page_address is
1734 * io_page_list_p A pointer to an io_page_list.
1736 * "size based byte swap" - Some functions do size based byte swapping
1737 * which allows sw to access pointers and
1738 * counters in native form when the processor
1739 * operates in a different endianness than the
1740 * IO bus. Size-based byte swapping converts a
1741 * multi-byte field between big-endian and
1742 * little-endian format.
1745 #define HV_PCI_MAP_ATTR_READ 0x01
1746 #define HV_PCI_MAP_ATTR_WRITE 0x02
1747 #define HV_PCI_MAP_ATTR_RELAXED_ORDER 0x04
1749 #define HV_PCI_DEVICE_BUILD(b,d,f) \
1750 ((((b) & 0xff) << 16) | \
1751 (((d) & 0x1f) << 11) | \
1752 (((f) & 0x07) << 8))
1754 #define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1755 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1757 #define HV_PCI_SYNC_FOR_DEVICE 0x01
1758 #define HV_PCI_SYNC_FOR_CPU 0x02
1761 * TRAP: HV_FAST_TRAP
1762 * FUNCTION: HV_FAST_PCI_IOMMU_MAP
1766 * ARG3: io_attributes
1767 * ARG4: io_page_list_p
1769 * RET1: #ttes mapped
1770 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
1771 * EBADALIGN Improperly aligned real address
1772 * ENORADDR Invalid real address
1774 * Create IOMMU mappings in the sun4v device defined by the given
1775 * devhandle. The mappings are created in the TSB defined by the
1776 * tsbnum component of the given tsbid. The first mapping is created
1777 * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1778 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1779 * the second at tsbnum, tsbindex + 1, etc.
1781 * All mappings are created with the attributes defined by the io_attributes
1782 * argument. The page mapping addresses are described in the io_page_list
1783 * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1784 * The first entry in the io_page_list is the address for the first iotte, the
1785 * 2nd for the 2nd iotte, and so on.
1787 * Each io_page_address in the io_page_list must be appropriately aligned.
1788 * #ttes must be greater than zero. For this version of the spec, the tsbnum
1789 * component of the given tsbid must be zero.
1791 * Returns the actual number of mappings creates, which may be less than
1792 * or equal to the argument #ttes. If the function returns a value which
1793 * is less than the #ttes, the caller may continus to call the function with
1794 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1797 * Note: This function does not imply an iotte cache flush. The guest must
1798 * demap an entry before re-mapping it.
1800 #define HV_FAST_PCI_IOMMU_MAP 0xb0
1802 /* pci_iommu_demap()
1803 * TRAP: HV_FAST_TRAP
1804 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
1809 * RET1: #ttes demapped
1810 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1812 * Demap and flush IOMMU mappings in the device defined by the given
1813 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
1814 * component of the given tsbid, starting at the TSB index defined by the
1815 * tsbindex component of the given tsbid.
1817 * For this version of the spec, the tsbnum of the given tsbid must be zero.
1818 * #ttes must be greater than zero.
1820 * Returns the actual number of ttes demapped, which may be less than or equal
1821 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
1822 * may continue to call this function with updated tsbid and #ttes arguments
1823 * until all pages are demapped.
1825 * Note: Entries do not have to be mapped to be demapped. A demap of an
1826 * unmapped page will flush the entry from the tte cache.
1828 #define HV_FAST_PCI_IOMMU_DEMAP 0xb1
1830 /* pci_iommu_getmap()
1831 * TRAP: HV_FAST_TRAP
1832 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
1836 * RET1: io_attributes
1837 * RET2: real address
1838 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1839 * ENOMAP Mapping is not valid, no translation exists
1841 * Read and return the mapping in the device described by the given devhandle
1842 * and tsbid. If successful, the io_attributes shall be returned in RET1
1843 * and the page address of the mapping shall be returned in RET2.
1845 * For this version of the spec, the tsbnum component of the given tsbid
1848 #define HV_FAST_PCI_IOMMU_GETMAP 0xb2
1850 /* pci_iommu_getbypass()
1851 * TRAP: HV_FAST_TRAP
1852 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
1854 * ARG1: real address
1855 * ARG2: io_attributes
1858 * ERRORS: EINVAL Invalid devhandle/io_attributes
1859 * ENORADDR Invalid real address
1860 * ENOTSUPPORTED Function not supported in this implementation.
1862 * Create a "special" mapping in the device described by the given devhandle,
1863 * for the given real address and attributes. Return the IO address in RET1
1866 #define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
1869 * TRAP: HV_FAST_TRAP
1870 * FUNCTION: HV_FAST_PCI_CONFIG_GET
1873 * ARG2: pci_config_offset
1878 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1879 * EBADALIGN pci_config_offset not size aligned
1880 * ENOACCESS Access to this offset is not permitted
1882 * Read PCI configuration space for the adapter described by the given
1883 * devhandle. Read size (1, 2, or 4) bytes of data from the given
1884 * pci_device, at pci_config_offset from the beginning of the device's
1885 * configuration space. If there was no error, RET1 is set to zero and
1886 * RET2 is set to the data read. Insignificant bits in RET2 are not
1887 * guaranteed to have any specific value and therefore must be ignored.
1889 * The data returned in RET2 is size based byte swapped.
1891 * If an error occurs during the read, set RET1 to a non-zero value. The
1892 * given pci_config_offset must be 'size' aligned.
1894 #define HV_FAST_PCI_CONFIG_GET 0xb4
1897 * TRAP: HV_FAST_TRAP
1898 * FUNCTION: HV_FAST_PCI_CONFIG_PUT
1901 * ARG2: pci_config_offset
1906 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1907 * EBADALIGN pci_config_offset not size aligned
1908 * ENOACCESS Access to this offset is not permitted
1910 * Write PCI configuration space for the adapter described by the given
1911 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
1912 * at pci_config_offset from the beginning of the device's configuration
1913 * space. The data argument contains the data to be written to configuration
1914 * space. Prior to writing, the data is size based byte swapped.
1916 * If an error occurs during the write access, do not generate an error
1917 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
1918 * The given pci_config_offset must be 'size' aligned.
1920 * This function is permitted to read from offset zero in the configuration
1921 * space described by the given pci_device if necessary to ensure that the
1922 * write access to config space completes.
1924 #define HV_FAST_PCI_CONFIG_PUT 0xb5
1927 * TRAP: HV_FAST_TRAP
1928 * FUNCTION: HV_FAST_PCI_PEEK
1930 * ARG1: real address
1935 * ERRORS: EINVAL Invalid devhandle or size
1936 * EBADALIGN Improperly aligned real address
1937 * ENORADDR Bad real address
1938 * ENOACCESS Guest access prohibited
1940 * Attempt to read the IO address given by the given devhandle, real address,
1941 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
1942 * access operation using the given size. If an error occurs when reading
1943 * from the given location, do not generate an error report, but return a
1944 * non-zero value in RET1. If the read was successful, return zero in RET1
1945 * and return the actual data read in RET2. The data returned is size based
1948 * Non-significant bits in RET2 are not guaranteed to have any specific value
1949 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1950 * value is not guaranteed to have any specific value and should be ignored.
1952 * The caller must have permission to read from the given devhandle, real
1953 * address, which must be an IO address. The argument real address must be a
1954 * size aligned address.
1956 * The hypervisor implementation of this function must block access to any
1957 * IO address that the guest does not have explicit permission to access.
1959 #define HV_FAST_PCI_PEEK 0xb6
1962 * TRAP: HV_FAST_TRAP
1963 * FUNCTION: HV_FAST_PCI_POKE
1965 * ARG1: real address
1971 * ERRORS: EINVAL Invalid devhandle, size, or pci_device
1972 * EBADALIGN Improperly aligned real address
1973 * ENORADDR Bad real address
1974 * ENOACCESS Guest access prohibited
1975 * ENOTSUPPORTED Function is not supported by implementation
1977 * Attempt to write data to the IO address given by the given devhandle,
1978 * real address, and size. Size must be 1, 2, 4, or 8. The write is
1979 * performed as a single access operation using the given size. Prior to
1980 * writing the data is size based swapped.
1982 * If an error occurs when writing to the given location, do not generate an
1983 * error report, but return a non-zero value in RET1. If the write was
1984 * successful, return zero in RET1.
1986 * pci_device describes the configuration address of the device being
1987 * written to. The implementation may safely read from offset 0 with
1988 * the configuration space of the device described by devhandle and
1989 * pci_device in order to guarantee that the write portion of the operation
1992 * Any error that occurs due to the read shall be reported using the normal
1993 * error reporting mechanisms .. the read error is not suppressed.
1995 * The caller must have permission to write to the given devhandle, real
1996 * address, which must be an IO address. The argument real address must be a
1997 * size aligned address. The caller must have permission to read from
1998 * the given devhandle, pci_device cofiguration space offset 0.
2000 * The hypervisor implementation of this function must block access to any
2001 * IO address that the guest does not have explicit permission to access.
2003 #define HV_FAST_PCI_POKE 0xb7
2006 * TRAP: HV_FAST_TRAP
2007 * FUNCTION: HV_FAST_PCI_DMA_SYNC
2009 * ARG1: real address
2011 * ARG3: io_sync_direction
2014 * ERRORS: EINVAL Invalid devhandle or io_sync_direction
2015 * ENORADDR Bad real address
2017 * Synchronize a memory region described by the given real address and size,
2018 * for the device defined by the given devhandle using the direction(s)
2019 * defined by the given io_sync_direction. The argument size is the size of
2020 * the memory region in bytes.
2022 * Return the actual number of bytes synchronized in the return value #synced,
2023 * which may be less than or equal to the argument size. If the return
2024 * value #synced is less than size, the caller must continue to call this
2025 * function with updated real address and size arguments until the entire
2026 * memory region is synchronized.
2028 #define HV_FAST_PCI_DMA_SYNC 0xb8
2030 /* PCI MSI services. */
2032 #define HV_MSITYPE_MSI32 0x00
2033 #define HV_MSITYPE_MSI64 0x01
2035 #define HV_MSIQSTATE_IDLE 0x00
2036 #define HV_MSIQSTATE_ERROR 0x01
2038 #define HV_MSIQ_INVALID 0x00
2039 #define HV_MSIQ_VALID 0x01
2041 #define HV_MSISTATE_IDLE 0x00
2042 #define HV_MSISTATE_DELIVERED 0x01
2044 #define HV_MSIVALID_INVALID 0x00
2045 #define HV_MSIVALID_VALID 0x01
2047 #define HV_PCIE_MSGTYPE_PME_MSG 0x18
2048 #define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
2049 #define HV_PCIE_MSGTYPE_CORR_MSG 0x30
2050 #define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
2051 #define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
2053 #define HV_MSG_INVALID 0x00
2054 #define HV_MSG_VALID 0x01
2057 * TRAP: HV_FAST_TRAP
2058 * FUNCTION: HV_FAST_PCI_MSIQ_CONF
2061 * ARG2: real address
2062 * ARG3: number of entries
2064 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
2065 * EBADALIGN Improperly aligned real address
2066 * ENORADDR Bad real address
2068 * Configure the MSI queue given by the devhandle and msiqid arguments,
2069 * and to be placed at the given real address and be of the given
2070 * number of entries. The real address must be aligned exactly to match
2071 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
2072 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
2073 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
2075 * Implementation Note: Certain implementations have fixed sized queues. In
2076 * that case, number of entries must contain the correct
2079 #define HV_FAST_PCI_MSIQ_CONF 0xc0
2082 * TRAP: HV_FAST_TRAP
2083 * FUNCTION: HV_FAST_PCI_MSIQ_INFO
2087 * RET1: real address
2088 * RET2: number of entries
2089 * ERRORS: EINVAL Invalid devhandle or msiqid
2091 * Return the configuration information for the MSI queue described
2092 * by the given devhandle and msiqid. The base address of the queue
2093 * is returned in ARG1 and the number of entries is returned in ARG2.
2094 * If the queue is unconfigured, the real address is undefined and the
2095 * number of entries will be returned as zero.
2097 #define HV_FAST_PCI_MSIQ_INFO 0xc1
2099 /* pci_msiq_getvalid()
2100 * TRAP: HV_FAST_TRAP
2101 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2105 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2106 * ERRORS: EINVAL Invalid devhandle or msiqid
2108 * Get the valid state of the MSI-EQ described by the given devhandle and
2111 #define HV_FAST_PCI_MSIQ_GETVALID 0xc2
2113 /* pci_msiq_setvalid()
2114 * TRAP: HV_FAST_TRAP
2115 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
2118 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2120 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
2121 * value or MSI EQ is uninitialized
2123 * Set the valid state of the MSI-EQ described by the given devhandle and
2124 * msiqid to the given msiqvalid.
2126 #define HV_FAST_PCI_MSIQ_SETVALID 0xc3
2128 /* pci_msiq_getstate()
2129 * TRAP: HV_FAST_TRAP
2130 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
2134 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2135 * ERRORS: EINVAL Invalid devhandle or msiqid
2137 * Get the state of the MSI-EQ described by the given devhandle and
2140 #define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
2142 /* pci_msiq_getvalid()
2143 * TRAP: HV_FAST_TRAP
2144 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2147 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2149 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
2150 * value or MSI EQ is uninitialized
2152 * Set the state of the MSI-EQ described by the given devhandle and
2153 * msiqid to the given msiqvalid.
2155 #define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
2157 /* pci_msiq_gethead()
2158 * TRAP: HV_FAST_TRAP
2159 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
2164 * ERRORS: EINVAL Invalid devhandle or msiqid
2166 * Get the current MSI EQ queue head for the MSI-EQ described by the
2167 * given devhandle and msiqid.
2169 #define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
2171 /* pci_msiq_sethead()
2172 * TRAP: HV_FAST_TRAP
2173 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
2178 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
2179 * or MSI EQ is uninitialized
2181 * Set the current MSI EQ queue head for the MSI-EQ described by the
2182 * given devhandle and msiqid.
2184 #define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
2186 /* pci_msiq_gettail()
2187 * TRAP: HV_FAST_TRAP
2188 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
2193 * ERRORS: EINVAL Invalid devhandle or msiqid
2195 * Get the current MSI EQ queue tail for the MSI-EQ described by the
2196 * given devhandle and msiqid.
2198 #define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
2200 /* pci_msi_getvalid()
2201 * TRAP: HV_FAST_TRAP
2202 * FUNCTION: HV_FAST_PCI_MSI_GETVALID
2206 * RET1: msivalidstate
2207 * ERRORS: EINVAL Invalid devhandle or msinum
2209 * Get the current valid/enabled state for the MSI defined by the
2210 * given devhandle and msinum.
2212 #define HV_FAST_PCI_MSI_GETVALID 0xc9
2214 /* pci_msi_setvalid()
2215 * TRAP: HV_FAST_TRAP
2216 * FUNCTION: HV_FAST_PCI_MSI_SETVALID
2219 * ARG2: msivalidstate
2221 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
2223 * Set the current valid/enabled state for the MSI defined by the
2224 * given devhandle and msinum.
2226 #define HV_FAST_PCI_MSI_SETVALID 0xca
2228 /* pci_msi_getmsiq()
2229 * TRAP: HV_FAST_TRAP
2230 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
2235 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
2237 * Get the MSI EQ that the MSI defined by the given devhandle and
2238 * msinum is bound to.
2240 #define HV_FAST_PCI_MSI_GETMSIQ 0xcb
2242 /* pci_msi_setmsiq()
2243 * TRAP: HV_FAST_TRAP
2244 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
2250 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
2252 * Set the MSI EQ that the MSI defined by the given devhandle and
2253 * msinum is bound to.
2255 #define HV_FAST_PCI_MSI_SETMSIQ 0xcc
2257 /* pci_msi_getstate()
2258 * TRAP: HV_FAST_TRAP
2259 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
2264 * ERRORS: EINVAL Invalid devhandle or msinum
2266 * Get the state of the MSI defined by the given devhandle and msinum.
2267 * If not initialized, return HV_MSISTATE_IDLE.
2269 #define HV_FAST_PCI_MSI_GETSTATE 0xcd
2271 /* pci_msi_setstate()
2272 * TRAP: HV_FAST_TRAP
2273 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
2278 * ERRORS: EINVAL Invalid devhandle or msinum or msistate
2280 * Set the state of the MSI defined by the given devhandle and msinum.
2282 #define HV_FAST_PCI_MSI_SETSTATE 0xce
2284 /* pci_msg_getmsiq()
2285 * TRAP: HV_FAST_TRAP
2286 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
2291 * ERRORS: EINVAL Invalid devhandle or msgtype
2293 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2295 #define HV_FAST_PCI_MSG_GETMSIQ 0xd0
2297 /* pci_msg_setmsiq()
2298 * TRAP: HV_FAST_TRAP
2299 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
2304 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
2306 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2308 #define HV_FAST_PCI_MSG_SETMSIQ 0xd1
2310 /* pci_msg_getvalid()
2311 * TRAP: HV_FAST_TRAP
2312 * FUNCTION: HV_FAST_PCI_MSG_GETVALID
2316 * RET1: msgvalidstate
2317 * ERRORS: EINVAL Invalid devhandle or msgtype
2319 * Get the valid/enabled state of the MSG defined by the given
2320 * devhandle and msgtype.
2322 #define HV_FAST_PCI_MSG_GETVALID 0xd2
2324 /* pci_msg_setvalid()
2325 * TRAP: HV_FAST_TRAP
2326 * FUNCTION: HV_FAST_PCI_MSG_SETVALID
2329 * ARG2: msgvalidstate
2331 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
2333 * Set the valid/enabled state of the MSG defined by the given
2334 * devhandle and msgtype.
2336 #define HV_FAST_PCI_MSG_SETVALID 0xd3
2338 /* PCI IOMMU v2 definitions and services
2340 * While the PCI IO definitions above is valid IOMMU v2 adds new PCI IO
2341 * definitions and services.
2343 * CTE Clump Table Entry. First level table entry in the ATU.
2346 * A 32-bit aligned list of pci_devices.
2349 * real address of a pci_device_list. 32-bit aligned.
2351 * iotte IOMMU translation table entry.
2354 * IO Attributes for IOMMU v2 mappings. In addition to
2355 * read, write IOMMU v2 supports relax ordering
2357 * io_page_list A 64-bit aligned list of real addresses. Each real
2358 * address in an io_page_list must be properly aligned
2359 * to the pagesize of the given IOTSB.
2361 * io_page_list_p Real address of an io_page_list, 64-bit aligned.
2363 * IOTSB IO Translation Storage Buffer. An aligned table of
2364 * IOTTEs. Each IOTSB has a pagesize, table size, and
2365 * virtual address associated with it that must match
2366 * a pagesize and table size supported by the un-derlying
2367 * hardware implementation. The alignment requirements
2368 * for an IOTSB depend on the pagesize used for that IOTSB.
2369 * Each IOTTE in an IOTSB maps one pagesize-sized page.
2370 * The size of the IOTSB dictates how large of a virtual
2371 * address space the IOTSB is capable of mapping.
2373 * iotsb_handle An opaque identifier for an IOTSB. A devhandle plus
2374 * iotsb_handle represents a binding of an IOTSB to a
2377 * iotsb_index Zero-based IOTTE number within an IOTSB.
2380 /* The index_count argument consists of two fields:
2381 * bits 63:48 #iottes and bits 47:0 iotsb_index
2383 #define HV_PCI_IOTSB_INDEX_COUNT(__iottes, __iotsb_index) \
2384 (((u64)(__iottes) << 48UL) | ((u64)(__iotsb_index)))
2387 * TRAP: HV_FAST_TRAP
2388 * FUNCTION: HV_FAST_PCI_IOTSB_CONF
2395 * RET1: iotsb_handle
2396 * ERRORS: EINVAL Invalid devhandle, size, iova, or pagesize
2397 * EBADALIGN r_addr is not properly aligned
2398 * ENORADDR r_addr is not a valid real address
2399 * ETOOMANY No further IOTSBs may be configured
2400 * EBUSY Duplicate devhandle, raddir, iova combination
2402 * Create an IOTSB suitable for the PCI root complex identified by devhandle,
2403 * for the DMA virtual address defined by the argument iova.
2405 * r_addr is the properly aligned base address of the IOTSB and size is the
2406 * IOTSB (table) size in bytes.The IOTSB is required to be zeroed prior to
2407 * being configured. If it contains any values other than zeros then the
2408 * behavior is undefined.
2410 * pagesize is the size of each page in the IOTSB. Note that the combination of
2411 * size (table size) and pagesize must be valid.
2413 * virt is the DMA virtual address this IOTSB will map.
2415 * If successful, the opaque 64-bit handle iotsb_handle is returned in ret1.
2416 * Once configured, privileged access to the IOTSB memory is prohibited and
2417 * creates undefined behavior. The only permitted access is indirect via these
2420 #define HV_FAST_PCI_IOTSB_CONF 0x190
2423 * TRAP: HV_FAST_TRAP
2424 * FUNCTION: HV_FAST_PCI_IOTSB_INFO
2426 * ARG1: iotsb_handle
2433 * ERRORS: EINVAL Invalid devhandle or iotsb_handle
2435 * This service returns configuration information about an IOTSB previously
2436 * created with pci_iotsb_conf.
2438 * iotsb_handle value 0 may be used with this service to inquire about the
2439 * legacy IOTSB that may or may not exist. If the service succeeds, the return
2440 * values describe the legacy IOTSB and I/O virtual addresses mapped by that
2441 * table. However, the table base address r_addr may contain the value -1 which
2442 * indicates a memory range that cannot be accessed or be reclaimed.
2444 * The return value #bound contains the number of PCI devices that iotsb_handle
2445 * is currently bound to.
2447 #define HV_FAST_PCI_IOTSB_INFO 0x191
2449 /* pci_iotsb_unconf()
2450 * TRAP: HV_FAST_TRAP
2451 * FUNCTION: HV_FAST_PCI_IOTSB_UNCONF
2453 * ARG1: iotsb_handle
2455 * ERRORS: EINVAL Invalid devhandle or iotsb_handle
2456 * EBUSY The IOTSB is bound and may not be unconfigured
2458 * This service unconfigures the IOTSB identified by the devhandle and
2459 * iotsb_handle arguments, previously created with pci_iotsb_conf.
2460 * The IOTSB must not be currently bound to any device or the service will fail
2462 * If the call succeeds, iotsb_handle is no longer valid.
2464 #define HV_FAST_PCI_IOTSB_UNCONF 0x192
2467 * TRAP: HV_FAST_TRAP
2468 * FUNCTION: HV_FAST_PCI_IOTSB_BIND
2470 * ARG1: iotsb_handle
2473 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, or pci_device
2474 * EBUSY A PCI function is already bound to an IOTSB at the same
2475 * address range as specified by devhandle, iotsb_handle.
2477 * This service binds the PCI function specified by the argument pci_device to
2478 * the IOTSB specified by the arguments devhandle and iotsb_handle.
2480 * The PCI device function is bound to the specified IOTSB with the IOVA range
2481 * specified when the IOTSB was configured via pci_iotsb_conf. If the function
2482 * is already bound then it is unbound first.
2484 #define HV_FAST_PCI_IOTSB_BIND 0x193
2486 /* pci_iotsb_unbind()
2487 * TRAP: HV_FAST_TRAP
2488 * FUNCTION: HV_FAST_PCI_IOTSB_UNBIND
2490 * ARG1: iotsb_handle
2493 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, or pci_device
2494 * ENOMAP The PCI function was not bound to the specified IOTSB
2496 * This service unbinds the PCI device specified by the argument pci_device
2497 * from the IOTSB identified * by the arguments devhandle and iotsb_handle.
2499 * If the PCI device is not bound to the specified IOTSB then this service will
2500 * fail with status ENOMAP
2502 #define HV_FAST_PCI_IOTSB_UNBIND 0x194
2504 /* pci_iotsb_get_binding()
2505 * TRAP: HV_FAST_TRAP
2506 * FUNCTION: HV_FAST_PCI_IOTSB_GET_BINDING
2508 * ARG1: iotsb_handle
2511 * RET1: iotsb_handle
2512 * ERRORS: EINVAL Invalid devhandle, pci_device, or iova
2513 * ENOMAP The PCI function is not bound to an IOTSB at iova
2515 * This service returns the IOTSB binding, iotsb_handle, for a given pci_device
2516 * and DMA virtual address, iova.
2518 * iova must be the base address of a DMA virtual address range as defined by
2519 * the iommu-address-ranges property in the root complex device node defined
2520 * by the argument devhandle.
2522 #define HV_FAST_PCI_IOTSB_GET_BINDING 0x195
2525 * TRAP: HV_FAST_TRAP
2526 * FUNCTION: HV_FAST_PCI_IOTSB_MAP
2528 * ARG1: iotsb_handle
2530 * ARG3: iotte_attributes
2531 * ARG4: io_page_list_p
2534 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, #iottes,
2535 * iotsb_index or iotte_attributes
2536 * EBADALIGN Improperly aligned io_page_list_p or I/O page
2537 * address in the I/O page list.
2538 * ENORADDR Invalid io_page_list_p or I/O page address in
2539 * the I/O page list.
2541 * This service creates and flushes mappings in the IOTSB defined by the
2542 * arguments devhandle, iotsb.
2544 * The index_count argument consists of two fields. Bits 63:48 contain #iotte
2545 * and bits 47:0 contain iotsb_index
2547 * The first mapping is created in the IOTSB index specified by iotsb_index.
2548 * Subsequent mappings are created at iotsb_index+1 and so on.
2550 * The attributes of each mapping are defined by the argument iotte_attributes.
2552 * The io_page_list_p specifies the real address of the 64-bit-aligned list of
2553 * #iottes I/O page addresses. Each page address must be a properly aligned
2554 * real address of a page to be mapped in the IOTSB. The first entry in the I/O
2555 * page list contains the real address of the first page, the 2nd entry for the
2556 * 2nd page, and so on.
2558 * #iottes must be greater than zero.
2560 * The return value #mapped is the actual number of mappings created, which may
2561 * be less than or equal to the argument #iottes. If the function returns
2562 * successfully with a #mapped value less than the requested #iottes then the
2563 * caller should continue to invoke the service with updated iotsb_index,
2564 * #iottes, and io_page_list_p arguments until all pages are mapped.
2566 * This service must not be used to demap a mapping. In other words, all
2567 * mappings must be valid and have one or both of the RW attribute bits set.
2570 * It is implementation-defined whether I/O page real address validity checking
2571 * is done at time mappings are established or deferred until they are
2574 #define HV_FAST_PCI_IOTSB_MAP 0x196
2576 /* pci_iotsb_map_one()
2577 * TRAP: HV_FAST_TRAP
2578 * FUNCTION: HV_FAST_PCI_IOTSB_MAP_ONE
2580 * ARG1: iotsb_handle
2582 * ARG3: iotte_attributes
2585 * ERRORS: EINVAL Invalid devhandle,iotsb_handle, iotsb_index
2586 * or iotte_attributes
2587 * EBADALIGN Improperly aligned r_addr
2588 * ENORADDR Invalid r_addr
2590 * This service creates and flushes a single mapping in the IOTSB defined by the
2591 * arguments devhandle, iotsb.
2593 * The mapping for the page at r_addr is created at the IOTSB index specified by
2594 * iotsb_index with the attributes iotte_attributes.
2596 * This service must not be used to demap a mapping. In other words, the mapping
2597 * must be valid and have one or both of the RW attribute bits set.
2600 * It is implementation-defined whether I/O page real address validity checking
2601 * is done at time mappings are established or deferred until they are
2604 #define HV_FAST_PCI_IOTSB_MAP_ONE 0x197
2606 /* pci_iotsb_demap()
2607 * TRAP: HV_FAST_TRAP
2608 * FUNCTION: HV_FAST_PCI_IOTSB_DEMAP
2610 * ARG1: iotsb_handle
2615 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, iotsb_index or #iottes
2617 * This service unmaps and flushes up to #iottes mappings starting at index
2618 * iotsb_index from the IOTSB defined by the arguments devhandle, iotsb.
2620 * #iottes must be greater than zero.
2622 * The actual number of IOTTEs unmapped is returned in #unmapped and may be less
2623 * than or equal to the requested number of IOTTEs, #iottes.
2625 * If #unmapped is less than #iottes, the caller should continue to invoke this
2626 * service with updated iotsb_index and #iottes arguments until all pages are
2629 #define HV_FAST_PCI_IOTSB_DEMAP 0x198
2631 /* pci_iotsb_getmap()
2632 * TRAP: HV_FAST_TRAP
2633 * FUNCTION: HV_FAST_PCI_IOTSB_GETMAP
2635 * ARG1: iotsb_handle
2639 * RET2: iotte_attributes
2640 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, or iotsb_index
2641 * ENOMAP No mapping was found
2643 * This service returns the mapping specified by index iotsb_index from the
2644 * IOTSB defined by the arguments devhandle, iotsb.
2646 * Upon success, the real address of the mapping shall be returned in
2647 * r_addr and thethe IOTTE mapping attributes shall be returned in
2650 * The return value iotte_attributes may not include optional features used in
2651 * the call to create the mapping.
2653 #define HV_FAST_PCI_IOTSB_GETMAP 0x199
2655 /* pci_iotsb_sync_mappings()
2656 * TRAP: HV_FAST_TRAP
2657 * FUNCTION: HV_FAST_PCI_IOTSB_SYNC_MAPPINGS
2659 * ARG1: iotsb_handle
2664 * ERROS: EINVAL Invalid devhandle, iotsb_handle, iotsb_index, or #iottes
2666 * This service synchronizes #iottes mappings starting at index iotsb_index in
2667 * the IOTSB defined by the arguments devhandle, iotsb.
2669 * #iottes must be greater than zero.
2671 * The actual number of IOTTEs synchronized is returned in #synced, which may
2672 * be less than or equal to the requested number, #iottes.
2674 * Upon a successful return, #synced is less than #iottes, the caller should
2675 * continue to invoke this service with updated iotsb_index and #iottes
2676 * arguments until all pages are synchronized.
2678 #define HV_FAST_PCI_IOTSB_SYNC_MAPPINGS 0x19a
2680 /* Logical Domain Channel services. */
2682 #define LDC_CHANNEL_DOWN 0
2683 #define LDC_CHANNEL_UP 1
2684 #define LDC_CHANNEL_RESETTING 2
2687 * TRAP: HV_FAST_TRAP
2688 * FUNCTION: HV_FAST_LDC_TX_QCONF
2690 * ARG1: real address base of queue
2691 * ARG2: num entries in queue
2694 * Configure transmit queue for the LDC endpoint specified by the
2695 * given channel ID, to be placed at the given real address, and
2696 * be of the given num entries. Num entries must be a power of two.
2697 * The real address base of the queue must be aligned on the queue
2698 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2699 * queue must be aligned on a 2048 byte real address boundary.
2701 * Upon configuration of a valid transmit queue the head and tail
2702 * pointers are set to a hypervisor specific identical value indicating
2703 * that the queue initially is empty.
2705 * The endpoint's transmit queue is un-configured if num entries is zero.
2707 * The maximum number of entries for each queue for a specific cpu may be
2708 * determined from the machine description. A transmit queue may be
2709 * specified even in the event that the LDC is down (peer endpoint has no
2710 * receive queue specified). Transmission will begin as soon as the peer
2711 * endpoint defines a receive queue.
2713 * It is recommended that a guest wait for a transmit queue to empty prior
2714 * to reconfiguring it, or un-configuring it. Re or un-configuring of a
2715 * non-empty transmit queue behaves exactly as defined above, however it
2716 * is undefined as to how many of the pending entries in the original queue
2717 * will be delivered prior to the re-configuration taking effect.
2718 * Furthermore, as the queue configuration causes a reset of the head and
2719 * tail pointers there is no way for a guest to determine how many entries
2720 * have been sent after the configuration operation.
2722 #define HV_FAST_LDC_TX_QCONF 0xe0
2725 * TRAP: HV_FAST_TRAP
2726 * FUNCTION: HV_FAST_LDC_TX_QINFO
2729 * RET1: real address base of queue
2730 * RET2: num entries in queue
2732 * Return the configuration info for the transmit queue of LDC endpoint
2733 * defined by the given channel ID. The real address is the currently
2734 * defined real address base of the defined queue, and num entries is the
2735 * size of the queue in terms of number of entries.
2737 * If the specified channel ID is a valid endpoint number, but no transmit
2738 * queue has been defined this service will return success, but with num
2739 * entries set to zero and the real address will have an undefined value.
2741 #define HV_FAST_LDC_TX_QINFO 0xe1
2743 /* ldc_tx_get_state()
2744 * TRAP: HV_FAST_TRAP
2745 * FUNCTION: HV_FAST_LDC_TX_GET_STATE
2750 * RET3: channel state
2752 * Return the transmit state, and the head and tail queue pointers, for
2753 * the transmit queue of the LDC endpoint defined by the given channel ID.
2754 * The head and tail values are the byte offset of the head and tail
2755 * positions of the transmit queue for the specified endpoint.
2757 #define HV_FAST_LDC_TX_GET_STATE 0xe2
2759 /* ldc_tx_set_qtail()
2760 * TRAP: HV_FAST_TRAP
2761 * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL
2766 * Update the tail pointer for the transmit queue associated with the LDC
2767 * endpoint defined by the given channel ID. The tail offset specified
2768 * must be aligned on a 64 byte boundary, and calculated so as to increase
2769 * the number of pending entries on the transmit queue. Any attempt to
2770 * decrease the number of pending transmit queue entires is considered
2771 * an invalid tail offset and will result in an EINVAL error.
2773 * Since the tail of the transmit queue may not be moved backwards, the
2774 * transmit queue may be flushed by configuring a new transmit queue,
2775 * whereupon the hypervisor will configure the initial transmit head and
2776 * tail pointers to be equal.
2778 #define HV_FAST_LDC_TX_SET_QTAIL 0xe3
2781 * TRAP: HV_FAST_TRAP
2782 * FUNCTION: HV_FAST_LDC_RX_QCONF
2784 * ARG1: real address base of queue
2785 * ARG2: num entries in queue
2788 * Configure receive queue for the LDC endpoint specified by the
2789 * given channel ID, to be placed at the given real address, and
2790 * be of the given num entries. Num entries must be a power of two.
2791 * The real address base of the queue must be aligned on the queue
2792 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2793 * queue must be aligned on a 2048 byte real address boundary.
2795 * The endpoint's transmit queue is un-configured if num entries is zero.
2797 * If a valid receive queue is specified for a local endpoint the LDC is
2798 * in the up state for the purpose of transmission to this endpoint.
2800 * The maximum number of entries for each queue for a specific cpu may be
2801 * determined from the machine description.
2803 * As receive queue configuration causes a reset of the queue's head and
2804 * tail pointers there is no way for a gues to determine how many entries
2805 * have been received between a preceding ldc_get_rx_state() API call
2806 * and the completion of the configuration operation. It should be noted
2807 * that datagram delivery is not guaranteed via domain channels anyway,
2808 * and therefore any higher protocol should be resilient to datagram
2809 * loss if necessary. However, to overcome this specific race potential
2810 * it is recommended, for example, that a higher level protocol be employed
2811 * to ensure either retransmission, or ensure that no datagrams are pending
2812 * on the peer endpoint's transmit queue prior to the configuration process.
2814 #define HV_FAST_LDC_RX_QCONF 0xe4
2817 * TRAP: HV_FAST_TRAP
2818 * FUNCTION: HV_FAST_LDC_RX_QINFO
2821 * RET1: real address base of queue
2822 * RET2: num entries in queue
2824 * Return the configuration info for the receive queue of LDC endpoint
2825 * defined by the given channel ID. The real address is the currently
2826 * defined real address base of the defined queue, and num entries is the
2827 * size of the queue in terms of number of entries.
2829 * If the specified channel ID is a valid endpoint number, but no receive
2830 * queue has been defined this service will return success, but with num
2831 * entries set to zero and the real address will have an undefined value.
2833 #define HV_FAST_LDC_RX_QINFO 0xe5
2835 /* ldc_rx_get_state()
2836 * TRAP: HV_FAST_TRAP
2837 * FUNCTION: HV_FAST_LDC_RX_GET_STATE
2842 * RET3: channel state
2844 * Return the receive state, and the head and tail queue pointers, for
2845 * the receive queue of the LDC endpoint defined by the given channel ID.
2846 * The head and tail values are the byte offset of the head and tail
2847 * positions of the receive queue for the specified endpoint.
2849 #define HV_FAST_LDC_RX_GET_STATE 0xe6
2851 /* ldc_rx_set_qhead()
2852 * TRAP: HV_FAST_TRAP
2853 * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD
2858 * Update the head pointer for the receive queue associated with the LDC
2859 * endpoint defined by the given channel ID. The head offset specified
2860 * must be aligned on a 64 byte boundary, and calculated so as to decrease
2861 * the number of pending entries on the receive queue. Any attempt to
2862 * increase the number of pending receive queue entires is considered
2863 * an invalid head offset and will result in an EINVAL error.
2865 * The receive queue may be flushed by setting the head offset equal
2866 * to the current tail offset.
2868 #define HV_FAST_LDC_RX_SET_QHEAD 0xe7
2870 /* LDC Map Table Entry. Each slot is defined by a translation table
2871 * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
2872 * hypervisor invalidation cookie.
2874 #define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */
2875 #define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */
2876 #define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */
2877 #define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
2878 #define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */
2879 #define LDC_MTE_EXEC 0x0000000000000040 /* execute */
2880 #define LDC_MTE_WRITE 0x0000000000000020 /* read */
2881 #define LDC_MTE_READ 0x0000000000000010 /* write */
2882 #define LDC_MTE_SZALL 0x000000000000000f /* page size bits */
2883 #define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */
2884 #define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */
2885 #define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */
2886 #define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */
2887 #define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */
2888 #define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */
2889 #define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
2890 #define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
2892 #ifndef __ASSEMBLY__
2893 struct ldc_mtable_entry {
2895 unsigned long cookie;
2899 /* ldc_set_map_table()
2900 * TRAP: HV_FAST_TRAP
2901 * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE
2903 * ARG1: table real address
2907 * Register the MTE table at the given table real address, with the
2908 * specified num entries, for the LDC indicated by the given channel
2911 #define HV_FAST_LDC_SET_MAP_TABLE 0xea
2913 /* ldc_get_map_table()
2914 * TRAP: HV_FAST_TRAP
2915 * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE
2918 * RET1: table real address
2921 * Return the configuration of the current mapping table registered
2922 * for the given channel ID.
2924 #define HV_FAST_LDC_GET_MAP_TABLE 0xeb
2926 #define LDC_COPY_IN 0
2927 #define LDC_COPY_OUT 1
2930 * TRAP: HV_FAST_TRAP
2931 * FUNCTION: HV_FAST_LDC_COPY
2933 * ARG1: LDC_COPY_* direction code
2934 * ARG2: target real address
2935 * ARG3: local real address
2936 * ARG4: length in bytes
2938 * RET1: actual length in bytes
2940 #define HV_FAST_LDC_COPY 0xec
2942 #define LDC_MEM_READ 1
2943 #define LDC_MEM_WRITE 2
2944 #define LDC_MEM_EXEC 4
2947 * TRAP: HV_FAST_TRAP
2948 * FUNCTION: HV_FAST_LDC_MAPIN
2952 * RET1: real address
2953 * RET2: LDC_MEM_* permissions
2955 #define HV_FAST_LDC_MAPIN 0xed
2958 * TRAP: HV_FAST_TRAP
2959 * FUNCTION: HV_FAST_LDC_UNMAP
2960 * ARG0: real address
2963 #define HV_FAST_LDC_UNMAP 0xee
2966 * TRAP: HV_FAST_TRAP
2967 * FUNCTION: HV_FAST_LDC_REVOKE
2970 * ARG2: ldc_mtable_entry cookie
2973 #define HV_FAST_LDC_REVOKE 0xef
2975 #ifndef __ASSEMBLY__
2976 unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
2978 unsigned long num_entries);
2979 unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
2981 unsigned long *num_entries);
2982 unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
2983 unsigned long *head_off,
2984 unsigned long *tail_off,
2985 unsigned long *chan_state);
2986 unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
2987 unsigned long tail_off);
2988 unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
2990 unsigned long num_entries);
2991 unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
2993 unsigned long *num_entries);
2994 unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
2995 unsigned long *head_off,
2996 unsigned long *tail_off,
2997 unsigned long *chan_state);
2998 unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
2999 unsigned long head_off);
3000 unsigned long sun4v_ldc_set_map_table(unsigned long channel,
3002 unsigned long num_entries);
3003 unsigned long sun4v_ldc_get_map_table(unsigned long channel,
3005 unsigned long *num_entries);
3006 unsigned long sun4v_ldc_copy(unsigned long channel,
3007 unsigned long dir_code,
3008 unsigned long tgt_raddr,
3009 unsigned long lcl_raddr,
3011 unsigned long *actual_len);
3012 unsigned long sun4v_ldc_mapin(unsigned long channel,
3013 unsigned long cookie,
3015 unsigned long *perm);
3016 unsigned long sun4v_ldc_unmap(unsigned long ra);
3017 unsigned long sun4v_ldc_revoke(unsigned long channel,
3018 unsigned long cookie,
3019 unsigned long mte_cookie);
3022 /* Performance counter services. */
3024 #define HV_PERF_JBUS_PERF_CTRL_REG 0x00
3025 #define HV_PERF_JBUS_PERF_CNT_REG 0x01
3026 #define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
3027 #define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
3028 #define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
3029 #define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
3030 #define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
3031 #define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
3032 #define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
3033 #define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
3036 * TRAP: HV_FAST_TRAP
3037 * FUNCTION: HV_FAST_GET_PERFREG
3038 * ARG0: performance reg number
3040 * RET1: performance reg value
3041 * ERRORS: EINVAL Invalid performance register number
3042 * ENOACCESS No access allowed to performance counters
3044 * Read the value of the given DRAM/JBUS performance counter/control register.
3046 #define HV_FAST_GET_PERFREG 0x100
3049 * TRAP: HV_FAST_TRAP
3050 * FUNCTION: HV_FAST_SET_PERFREG
3051 * ARG0: performance reg number
3052 * ARG1: performance reg value
3054 * ERRORS: EINVAL Invalid performance register number
3055 * ENOACCESS No access allowed to performance counters
3057 * Write the given performance reg value to the given DRAM/JBUS
3058 * performance counter/control register.
3060 #define HV_FAST_SET_PERFREG 0x101
3062 #define HV_N2_PERF_SPARC_CTL 0x0
3063 #define HV_N2_PERF_DRAM_CTL0 0x1
3064 #define HV_N2_PERF_DRAM_CNT0 0x2
3065 #define HV_N2_PERF_DRAM_CTL1 0x3
3066 #define HV_N2_PERF_DRAM_CNT1 0x4
3067 #define HV_N2_PERF_DRAM_CTL2 0x5
3068 #define HV_N2_PERF_DRAM_CNT2 0x6
3069 #define HV_N2_PERF_DRAM_CTL3 0x7
3070 #define HV_N2_PERF_DRAM_CNT3 0x8
3072 #define HV_FAST_N2_GET_PERFREG 0x104
3073 #define HV_FAST_N2_SET_PERFREG 0x105
3075 #ifndef __ASSEMBLY__
3076 unsigned long sun4v_niagara_getperf(unsigned long reg,
3077 unsigned long *val);
3078 unsigned long sun4v_niagara_setperf(unsigned long reg,
3080 unsigned long sun4v_niagara2_getperf(unsigned long reg,
3081 unsigned long *val);
3082 unsigned long sun4v_niagara2_setperf(unsigned long reg,
3086 /* MMU statistics services.
3088 * The hypervisor maintains MMU statistics and privileged code provides
3089 * a buffer where these statistics can be collected. It is continually
3090 * updated once configured. The layout is as follows:
3092 #ifndef __ASSEMBLY__
3093 struct hv_mmu_statistics {
3094 unsigned long immu_tsb_hits_ctx0_8k_tte;
3095 unsigned long immu_tsb_ticks_ctx0_8k_tte;
3096 unsigned long immu_tsb_hits_ctx0_64k_tte;
3097 unsigned long immu_tsb_ticks_ctx0_64k_tte;
3098 unsigned long __reserved1[2];
3099 unsigned long immu_tsb_hits_ctx0_4mb_tte;
3100 unsigned long immu_tsb_ticks_ctx0_4mb_tte;
3101 unsigned long __reserved2[2];
3102 unsigned long immu_tsb_hits_ctx0_256mb_tte;
3103 unsigned long immu_tsb_ticks_ctx0_256mb_tte;
3104 unsigned long __reserved3[4];
3105 unsigned long immu_tsb_hits_ctxnon0_8k_tte;
3106 unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
3107 unsigned long immu_tsb_hits_ctxnon0_64k_tte;
3108 unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
3109 unsigned long __reserved4[2];
3110 unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
3111 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
3112 unsigned long __reserved5[2];
3113 unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
3114 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
3115 unsigned long __reserved6[4];
3116 unsigned long dmmu_tsb_hits_ctx0_8k_tte;
3117 unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
3118 unsigned long dmmu_tsb_hits_ctx0_64k_tte;
3119 unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
3120 unsigned long __reserved7[2];
3121 unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
3122 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
3123 unsigned long __reserved8[2];
3124 unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
3125 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
3126 unsigned long __reserved9[4];
3127 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
3128 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
3129 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
3130 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
3131 unsigned long __reserved10[2];
3132 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
3133 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
3134 unsigned long __reserved11[2];
3135 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
3136 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
3137 unsigned long __reserved12[4];
3142 * TRAP: HV_FAST_TRAP
3143 * FUNCTION: HV_FAST_MMUSTAT_CONF
3144 * ARG0: real address
3146 * RET1: real address
3147 * ERRORS: ENORADDR Invalid real address
3148 * EBADALIGN Real address not aligned on 64-byte boundary
3149 * EBADTRAP API not supported on this processor
3151 * Enable MMU statistic gathering using the buffer at the given real
3152 * address on the current virtual CPU. The new buffer real address
3153 * is given in ARG1, and the previously specified buffer real address
3154 * is returned in RET1, or is returned as zero for the first invocation.
3156 * If the passed in real address argument is zero, this will disable
3157 * MMU statistic collection on the current virtual CPU. If an error is
3158 * returned then no statistics are collected.
3160 * The buffer contents should be initialized to all zeros before being
3161 * given to the hypervisor or else the statistics will be meaningless.
3163 #define HV_FAST_MMUSTAT_CONF 0x102
3166 * TRAP: HV_FAST_TRAP
3167 * FUNCTION: HV_FAST_MMUSTAT_INFO
3169 * RET1: real address
3170 * ERRORS: EBADTRAP API not supported on this processor
3172 * Return the current state and real address of the currently configured
3173 * MMU statistics buffer on the current virtual CPU.
3175 #define HV_FAST_MMUSTAT_INFO 0x103
3177 #ifndef __ASSEMBLY__
3178 unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
3179 unsigned long sun4v_mmustat_info(unsigned long *ra);
3182 /* NCS crypto services */
3184 /* ncs_request() sub-function numbers */
3185 #define HV_NCS_QCONF 0x01
3186 #define HV_NCS_QTAIL_UPDATE 0x02
3188 #ifndef __ASSEMBLY__
3189 struct hv_ncs_queue_entry {
3190 /* MAU Control Register */
3191 unsigned long mau_control;
3192 #define MAU_CONTROL_INV_PARITY 0x0000000000002000
3193 #define MAU_CONTROL_STRAND 0x0000000000001800
3194 #define MAU_CONTROL_BUSY 0x0000000000000400
3195 #define MAU_CONTROL_INT 0x0000000000000200
3196 #define MAU_CONTROL_OP 0x00000000000001c0
3197 #define MAU_CONTROL_OP_SHIFT 6
3198 #define MAU_OP_LOAD_MA_MEMORY 0x0
3199 #define MAU_OP_STORE_MA_MEMORY 0x1
3200 #define MAU_OP_MODULAR_MULT 0x2
3201 #define MAU_OP_MODULAR_REDUCE 0x3
3202 #define MAU_OP_MODULAR_EXP_LOOP 0x4
3203 #define MAU_CONTROL_LEN 0x000000000000003f
3204 #define MAU_CONTROL_LEN_SHIFT 0
3206 /* Real address of bytes to load or store bytes
3207 * into/out-of the MAU.
3209 unsigned long mau_mpa;
3211 /* Modular Arithmetic MA Offset Register. */
3212 unsigned long mau_ma;
3214 /* Modular Arithmetic N Prime Register. */
3215 unsigned long mau_np;
3218 struct hv_ncs_qconf_arg {
3219 unsigned long mid; /* MAU ID, 1 per core on Niagara */
3220 unsigned long base; /* Real address base of queue */
3221 unsigned long end; /* Real address end of queue */
3222 unsigned long num_ents; /* Number of entries in queue */
3225 struct hv_ncs_qtail_update_arg {
3226 unsigned long mid; /* MAU ID, 1 per core on Niagara */
3227 unsigned long tail; /* New tail index to use */
3228 unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */
3229 #define HV_NCS_SYNCFLAG_SYNC 0x00
3230 #define HV_NCS_SYNCFLAG_ASYNC 0x01
3235 * TRAP: HV_FAST_TRAP
3236 * FUNCTION: HV_FAST_NCS_REQUEST
3237 * ARG0: NCS sub-function
3238 * ARG1: sub-function argument real address
3239 * ARG2: size in bytes of sub-function argument
3242 * The MAU chip of the Niagara processor is not directly accessible
3243 * to privileged code, instead it is programmed indirectly via this
3246 * The interfaces defines a queue of MAU operations to perform.
3247 * Privileged code registers a queue with the hypervisor by invoking
3248 * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
3249 * base, end, and number of entries of the queue. Each queue entry
3250 * contains a MAU register struct block.
3252 * The privileged code then proceeds to add entries to the queue and
3253 * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only
3254 * synchronous operations are supported by the current hypervisor,
3255 * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
3256 * completion and return HV_EOK, or return an error code.
3258 * The real address of the sub-function argument must be aligned on at
3259 * least an 8-byte boundary.
3261 * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
3262 * offset, into the queue and must be less than or equal the 'num_ents'
3263 * argument given in the HV_NCS_QCONF call.
3265 #define HV_FAST_NCS_REQUEST 0x110
3267 #ifndef __ASSEMBLY__
3268 unsigned long sun4v_ncs_request(unsigned long request,
3269 unsigned long arg_ra,
3270 unsigned long arg_size);
3273 #define HV_FAST_FIRE_GET_PERFREG 0x120
3274 #define HV_FAST_FIRE_SET_PERFREG 0x121
3276 #define HV_FAST_REBOOT_DATA_SET 0x172
3278 #ifndef __ASSEMBLY__
3279 unsigned long sun4v_reboot_data_set(unsigned long ra,
3283 #define HV_FAST_VT_GET_PERFREG 0x184
3284 #define HV_FAST_VT_SET_PERFREG 0x185
3286 #ifndef __ASSEMBLY__
3287 unsigned long sun4v_vt_get_perfreg(unsigned long reg_num,
3288 unsigned long *reg_val);
3289 unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
3290 unsigned long reg_val);
3293 #define HV_FAST_T5_GET_PERFREG 0x1a8
3294 #define HV_FAST_T5_SET_PERFREG 0x1a9
3296 #ifndef __ASSEMBLY__
3297 unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,
3298 unsigned long *reg_val);
3299 unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,
3300 unsigned long reg_val);
3304 #define HV_FAST_M7_GET_PERFREG 0x43
3305 #define HV_FAST_M7_SET_PERFREG 0x44
3307 #ifndef __ASSEMBLY__
3308 unsigned long sun4v_m7_get_perfreg(unsigned long reg_num,
3309 unsigned long *reg_val);
3310 unsigned long sun4v_m7_set_perfreg(unsigned long reg_num,
3311 unsigned long reg_val);
3314 /* Function numbers for HV_CORE_TRAP. */
3315 #define HV_CORE_SET_VER 0x00
3316 #define HV_CORE_PUTCHAR 0x01
3317 #define HV_CORE_EXIT 0x02
3318 #define HV_CORE_GET_VER 0x03
3320 /* Hypervisor API groups for use with HV_CORE_SET_VER and
3323 #define HV_GRP_SUN4V 0x0000
3324 #define HV_GRP_CORE 0x0001
3325 #define HV_GRP_INTR 0x0002
3326 #define HV_GRP_SOFT_STATE 0x0003
3327 #define HV_GRP_TM 0x0080
3328 #define HV_GRP_PCI 0x0100
3329 #define HV_GRP_LDOM 0x0101
3330 #define HV_GRP_SVC_CHAN 0x0102
3331 #define HV_GRP_NCS 0x0103
3332 #define HV_GRP_RNG 0x0104
3333 #define HV_GRP_PBOOT 0x0105
3334 #define HV_GRP_TPM 0x0107
3335 #define HV_GRP_SDIO 0x0108
3336 #define HV_GRP_SDIO_ERR 0x0109
3337 #define HV_GRP_REBOOT_DATA 0x0110
3338 #define HV_GRP_ATU 0x0111
3339 #define HV_GRP_M7_PERF 0x0114
3340 #define HV_GRP_NIAG_PERF 0x0200
3341 #define HV_GRP_FIRE_PERF 0x0201
3342 #define HV_GRP_N2_CPU 0x0202
3343 #define HV_GRP_NIU 0x0204
3344 #define HV_GRP_VF_CPU 0x0205
3345 #define HV_GRP_KT_CPU 0x0209
3346 #define HV_GRP_VT_CPU 0x020c
3347 #define HV_GRP_T5_CPU 0x0211
3348 #define HV_GRP_DIAG 0x0300
3350 #ifndef __ASSEMBLY__
3351 unsigned long sun4v_get_version(unsigned long group,
3352 unsigned long *major,
3353 unsigned long *minor);
3354 unsigned long sun4v_set_version(unsigned long group,
3355 unsigned long major,
3356 unsigned long minor,
3357 unsigned long *actual_minor);
3359 int sun4v_hvapi_register(unsigned long group, unsigned long major,
3360 unsigned long *minor);
3361 void sun4v_hvapi_unregister(unsigned long group);
3362 int sun4v_hvapi_get(unsigned long group,
3363 unsigned long *major,
3364 unsigned long *minor);
3365 void sun4v_hvapi_init(void);
3368 #endif /* !(_SPARC64_HYPERVISOR_H) */
git.samba.org / sfrench / cifs-2.6.git / blob