Merge branch 'x86/cpufeature' into irq/numa
[sfrench/cifs-2.6.git] / arch / sh / oprofile / op_model_sh7750.c
1 /*
2  * arch/sh/oprofile/op_model_sh7750.c
3  *
4  * OProfile support for SH7750/SH7750S Performance Counters
5  *
6  * Copyright (C) 2003 - 2008  Paul Mundt
7  *
8  * This file is subject to the terms and conditions of the GNU General Public
9  * License.  See the file "COPYING" in the main directory of this archive
10  * for more details.
11  */
12 #include <linux/kernel.h>
13 #include <linux/oprofile.h>
14 #include <linux/profile.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/fs.h>
20 #include "op_impl.h"
21
22 #define PM_CR_BASE      0xff000084      /* 16-bit */
23 #define PM_CTR_BASE     0xff100004      /* 32-bit */
24
25 #define PMCR(n)         (PM_CR_BASE + ((n) * 0x04))
26 #define PMCTRH(n)       (PM_CTR_BASE + 0x00 + ((n) * 0x08))
27 #define PMCTRL(n)       (PM_CTR_BASE + 0x04 + ((n) * 0x08))
28
29 #define PMCR_PMM_MASK   0x0000003f
30
31 #define PMCR_CLKF       0x00000100
32 #define PMCR_PMCLR      0x00002000
33 #define PMCR_PMST       0x00004000
34 #define PMCR_PMEN       0x00008000
35
36 struct op_sh_model op_model_sh7750_ops;
37
38 #define NR_CNTRS        2
39
40 static struct sh7750_ppc_register_config {
41         unsigned int ctrl;
42         unsigned long cnt_hi;
43         unsigned long cnt_lo;
44 } regcache[NR_CNTRS];
45
46 /*
47  * There are a number of events supported by each counter (33 in total).
48  * Since we have 2 counters, each counter will take the event code as it
49  * corresponds to the PMCR PMM setting. Each counter can be configured
50  * independently.
51  *
52  *      Event Code      Description
53  *      ----------      -----------
54  *
55  *      0x01            Operand read access
56  *      0x02            Operand write access
57  *      0x03            UTLB miss
58  *      0x04            Operand cache read miss
59  *      0x05            Operand cache write miss
60  *      0x06            Instruction fetch (w/ cache)
61  *      0x07            Instruction TLB miss
62  *      0x08            Instruction cache miss
63  *      0x09            All operand accesses
64  *      0x0a            All instruction accesses
65  *      0x0b            OC RAM operand access
66  *      0x0d            On-chip I/O space access
67  *      0x0e            Operand access (r/w)
68  *      0x0f            Operand cache miss (r/w)
69  *      0x10            Branch instruction
70  *      0x11            Branch taken
71  *      0x12            BSR/BSRF/JSR
72  *      0x13            Instruction execution
73  *      0x14            Instruction execution in parallel
74  *      0x15            FPU Instruction execution
75  *      0x16            Interrupt
76  *      0x17            NMI
77  *      0x18            trapa instruction execution
78  *      0x19            UBCA match
79  *      0x1a            UBCB match
80  *      0x21            Instruction cache fill
81  *      0x22            Operand cache fill
82  *      0x23            Elapsed time
83  *      0x24            Pipeline freeze by I-cache miss
84  *      0x25            Pipeline freeze by D-cache miss
85  *      0x27            Pipeline freeze by branch instruction
86  *      0x28            Pipeline freeze by CPU register
87  *      0x29            Pipeline freeze by FPU
88  *
89  * Unfortunately we don't have a native exception or interrupt for counter
90  * overflow (although since these counters can run for 16.3 days without
91  * overflowing, it's not really necessary).
92  *
93  * OProfile on the other hand likes to have samples taken periodically, so
94  * for now we just piggyback the timer interrupt to get the expected
95  * behavior.
96  */
97
98 static int sh7750_timer_notify(struct pt_regs *regs)
99 {
100         oprofile_add_sample(regs, 0);
101         return 0;
102 }
103
104 static u64 sh7750_read_counter(int counter)
105 {
106         return (u64)((u64)(__raw_readl(PMCTRH(counter)) & 0xffff) << 32) |
107                            __raw_readl(PMCTRL(counter));
108 }
109
110 /*
111  * Files will be in a path like:
112  *
113  *  /<oprofilefs mount point>/<counter number>/<file>
114  *
115  * So when dealing with <file>, we look to the parent dentry for the counter
116  * number.
117  */
118 static inline int to_counter(struct file *file)
119 {
120         const unsigned char *name = file->f_path.dentry->d_parent->d_name.name;
121
122         return (int)simple_strtol(name, NULL, 10);
123 }
124
125 /*
126  * XXX: We have 48-bit counters, so we're probably going to want something
127  * more along the lines of oprofilefs_ullong_to_user().. Truncating to
128  * unsigned long works fine for now though, as long as we don't attempt to
129  * profile for too horribly long.
130  */
131 static ssize_t sh7750_read_count(struct file *file, char __user *buf,
132                                  size_t count, loff_t *ppos)
133 {
134         int counter = to_counter(file);
135         u64 val = sh7750_read_counter(counter);
136
137         return oprofilefs_ulong_to_user((unsigned long)val, buf, count, ppos);
138 }
139
140 static ssize_t sh7750_write_count(struct file *file, const char __user *buf,
141                                   size_t count, loff_t *ppos)
142 {
143         int counter = to_counter(file);
144         unsigned long val;
145
146         if (oprofilefs_ulong_from_user(&val, buf, count))
147                 return -EFAULT;
148
149         /*
150          * Any write will clear the counter, although only 0 should be
151          * written for this purpose, as we do not support setting the
152          * counter to an arbitrary value.
153          */
154         WARN_ON(val != 0);
155
156         __raw_writew(__raw_readw(PMCR(counter)) | PMCR_PMCLR, PMCR(counter));
157
158         return count;
159 }
160
161 static const struct file_operations count_fops = {
162         .read           = sh7750_read_count,
163         .write          = sh7750_write_count,
164 };
165
166 static int sh7750_ppc_create_files(struct super_block *sb, struct dentry *dir)
167 {
168         return oprofilefs_create_file(sb, dir, "count", &count_fops);
169 }
170
171 static void sh7750_ppc_reg_setup(struct op_counter_config *ctr)
172 {
173         unsigned int counters = op_model_sh7750_ops.num_counters;
174         int i;
175
176         for (i = 0; i < counters; i++) {
177                 regcache[i].ctrl        = 0;
178                 regcache[i].cnt_hi      = 0;
179                 regcache[i].cnt_lo      = 0;
180
181                 if (!ctr[i].enabled)
182                         continue;
183
184                 regcache[i].ctrl |= ctr[i].event | PMCR_PMEN | PMCR_PMST;
185                 regcache[i].cnt_hi = (unsigned long)((ctr->count >> 32) & 0xffff);
186                 regcache[i].cnt_lo = (unsigned long)(ctr->count & 0xffffffff);
187         }
188 }
189
190 static void sh7750_ppc_cpu_setup(void *args)
191 {
192         unsigned int counters = op_model_sh7750_ops.num_counters;
193         int i;
194
195         for (i = 0; i < counters; i++) {
196                 __raw_writew(0, PMCR(i));
197                 __raw_writel(regcache[i].cnt_hi, PMCTRH(i));
198                 __raw_writel(regcache[i].cnt_lo, PMCTRL(i));
199         }
200 }
201
202 static void sh7750_ppc_cpu_start(void *args)
203 {
204         unsigned int counters = op_model_sh7750_ops.num_counters;
205         int i;
206
207         for (i = 0; i < counters; i++)
208                 __raw_writew(regcache[i].ctrl, PMCR(i));
209 }
210
211 static void sh7750_ppc_cpu_stop(void *args)
212 {
213         unsigned int counters = op_model_sh7750_ops.num_counters;
214         int i;
215
216         /* Disable the counters */
217         for (i = 0; i < counters; i++)
218                 __raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i));
219 }
220
221 static inline void sh7750_ppc_reset(void)
222 {
223         unsigned int counters = op_model_sh7750_ops.num_counters;
224         int i;
225
226         /* Clear the counters */
227         for (i = 0; i < counters; i++)
228                 __raw_writew(__raw_readw(PMCR(i)) | PMCR_PMCLR, PMCR(i));
229 }
230
231 static int sh7750_ppc_init(void)
232 {
233         sh7750_ppc_reset();
234
235         return register_timer_hook(sh7750_timer_notify);
236 }
237
238 static void sh7750_ppc_exit(void)
239 {
240         unregister_timer_hook(sh7750_timer_notify);
241
242         sh7750_ppc_reset();
243 }
244
245 struct op_sh_model op_model_sh7750_ops = {
246         .cpu_type       = "sh/sh7750",
247         .num_counters   = NR_CNTRS,
248         .reg_setup      = sh7750_ppc_reg_setup,
249         .cpu_setup      = sh7750_ppc_cpu_setup,
250         .cpu_start      = sh7750_ppc_cpu_start,
251         .cpu_stop       = sh7750_ppc_cpu_stop,
252         .init           = sh7750_ppc_init,
253         .exit           = sh7750_ppc_exit,
254         .create_files   = sh7750_ppc_create_files,
255 };