arch/sh/kernel/cpu/sh4a/setup-sh7786.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH7786 Setup
   4  *
   5  * Copyright (C) 2009 - 2011  Renesas Solutions Corp.
   6  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   7  * Paul Mundt <paul.mundt@renesas.com>
   8  *
   9  * Based on SH7785 Setup
  10  *
  11  *  Copyright (C) 2007  Paul Mundt
  12  */
  13 #include <linux/platform_device.h>
  14 #include <linux/init.h>
  15 #include <linux/serial.h>
  16 #include <linux/serial_sci.h>
  17 #include <linux/io.h>
  18 #include <linux/mm.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/sh_timer.h>
  21 #include <linux/sh_dma.h>
  22 #include <linux/sh_intc.h>
  23 #include <linux/usb/ohci_pdriver.h>
  24 #include <cpu/dma-register.h>
  25 #include <asm/mmzone.h>
  26
  27 static struct plat_sci_port scif0_platform_data = {
  28         .scscr          = SCSCR_REIE | SCSCR_CKE1,
  29         .type           = PORT_SCIF,
  30         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  31 };
  32
  33 static struct resource scif0_resources[] = {
  34         DEFINE_RES_MEM(0xffea0000, 0x100),
  35         DEFINE_RES_IRQ(evt2irq(0x700)),
  36         DEFINE_RES_IRQ(evt2irq(0x720)),
  37         DEFINE_RES_IRQ(evt2irq(0x760)),
  38         DEFINE_RES_IRQ(evt2irq(0x740)),
  39 };
  40
  41 static struct platform_device scif0_device = {
  42         .name           = "sh-sci",
  43         .id             = 0,
  44         .resource       = scif0_resources,
  45         .num_resources  = ARRAY_SIZE(scif0_resources),
  46         .dev            = {
  47                 .platform_data  = &scif0_platform_data,
  48         },
  49 };
  50
  51 /*
  52  * The rest of these all have multiplexed IRQs
  53  */
  54 static struct plat_sci_port scif1_platform_data = {
  55         .scscr          = SCSCR_REIE | SCSCR_CKE1,
  56         .type           = PORT_SCIF,
  57         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  58 };
  59
  60 static struct resource scif1_resources[] = {
  61         DEFINE_RES_MEM(0xffeb0000, 0x100),
  62         DEFINE_RES_IRQ(evt2irq(0x780)),
  63 };
  64
  65 static struct resource scif1_demux_resources[] = {
  66         DEFINE_RES_MEM(0xffeb0000, 0x100),
  67         /* Placeholders, see sh7786_devices_setup() */
  68         DEFINE_RES_IRQ(0),
  69         DEFINE_RES_IRQ(0),
  70         DEFINE_RES_IRQ(0),
  71         DEFINE_RES_IRQ(0),
  72 };
  73
  74 static struct platform_device scif1_device = {
  75         .name           = "sh-sci",
  76         .id             = 1,
  77         .resource       = scif1_resources,
  78         .num_resources  = ARRAY_SIZE(scif1_resources),
  79         .dev            = {
  80                 .platform_data  = &scif1_platform_data,
  81         },
  82 };
  83
  84 static struct plat_sci_port scif2_platform_data = {
  85         .scscr          = SCSCR_REIE | SCSCR_CKE1,
  86         .type           = PORT_SCIF,
  87         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  88 };
  89
  90 static struct resource scif2_resources[] = {
  91         DEFINE_RES_MEM(0xffec0000, 0x100),
  92         DEFINE_RES_IRQ(evt2irq(0x840)),
  93 };
  94
  95 static struct platform_device scif2_device = {
  96         .name           = "sh-sci",
  97         .id             = 2,
  98         .resource       = scif2_resources,
  99         .num_resources  = ARRAY_SIZE(scif2_resources),
 100         .dev            = {
 101                 .platform_data  = &scif2_platform_data,
 102         },
 103 };
 104
 105 static struct plat_sci_port scif3_platform_data = {
 106         .scscr          = SCSCR_REIE | SCSCR_CKE1,
 107         .type           = PORT_SCIF,
 108         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 109 };
 110
 111 static struct resource scif3_resources[] = {
 112         DEFINE_RES_MEM(0xffed0000, 0x100),
 113         DEFINE_RES_IRQ(evt2irq(0x860)),
 114 };
 115
 116 static struct platform_device scif3_device = {
 117         .name           = "sh-sci",
 118         .id             = 3,
 119         .resource       = scif3_resources,
 120         .num_resources  = ARRAY_SIZE(scif3_resources),
 121         .dev            = {
 122                 .platform_data  = &scif3_platform_data,
 123         },
 124 };
 125
 126 static struct plat_sci_port scif4_platform_data = {
 127         .scscr          = SCSCR_REIE | SCSCR_CKE1,
 128         .type           = PORT_SCIF,
 129         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 130 };
 131
 132 static struct resource scif4_resources[] = {
 133         DEFINE_RES_MEM(0xffee0000, 0x100),
 134         DEFINE_RES_IRQ(evt2irq(0x880)),
 135 };
 136
 137 static struct platform_device scif4_device = {
 138         .name           = "sh-sci",
 139         .id             = 4,
 140         .resource       = scif4_resources,
 141         .num_resources  = ARRAY_SIZE(scif4_resources),
 142         .dev            = {
 143                 .platform_data  = &scif4_platform_data,
 144         },
 145 };
 146
 147 static struct plat_sci_port scif5_platform_data = {
 148         .scscr          = SCSCR_REIE | SCSCR_CKE1,
 149         .type           = PORT_SCIF,
 150         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 151 };
 152
 153 static struct resource scif5_resources[] = {
 154         DEFINE_RES_MEM(0xffef0000, 0x100),
 155         DEFINE_RES_IRQ(evt2irq(0x8a0)),
 156 };
 157
 158 static struct platform_device scif5_device = {
 159         .name           = "sh-sci",
 160         .id             = 5,
 161         .resource       = scif5_resources,
 162         .num_resources  = ARRAY_SIZE(scif5_resources),
 163         .dev            = {
 164                 .platform_data  = &scif5_platform_data,
 165         },
 166 };
 167
 168 static struct sh_timer_config tmu0_platform_data = {
 169         .channels_mask = 7,
 170 };
 171
 172 static struct resource tmu0_resources[] = {
 173         DEFINE_RES_MEM(0xffd80000, 0x30),
 174         DEFINE_RES_IRQ(evt2irq(0x400)),
 175         DEFINE_RES_IRQ(evt2irq(0x420)),
 176         DEFINE_RES_IRQ(evt2irq(0x440)),
 177 };
 178
 179 static struct platform_device tmu0_device = {
 180         .name           = "sh-tmu",
 181         .id             = 0,
 182         .dev = {
 183                 .platform_data  = &tmu0_platform_data,
 184         },
 185         .resource       = tmu0_resources,
 186         .num_resources  = ARRAY_SIZE(tmu0_resources),
 187 };
 188
 189 static struct sh_timer_config tmu1_platform_data = {
 190         .channels_mask = 7,
 191 };
 192
 193 static struct resource tmu1_resources[] = {
 194         DEFINE_RES_MEM(0xffda0000, 0x2c),
 195         DEFINE_RES_IRQ(evt2irq(0x480)),
 196         DEFINE_RES_IRQ(evt2irq(0x4a0)),
 197         DEFINE_RES_IRQ(evt2irq(0x4c0)),
 198 };
 199
 200 static struct platform_device tmu1_device = {
 201         .name           = "sh-tmu",
 202         .id             = 1,
 203         .dev = {
 204                 .platform_data  = &tmu1_platform_data,
 205         },
 206         .resource       = tmu1_resources,
 207         .num_resources  = ARRAY_SIZE(tmu1_resources),
 208 };
 209
 210 static struct sh_timer_config tmu2_platform_data = {
 211         .channels_mask = 7,
 212 };
 213
 214 static struct resource tmu2_resources[] = {
 215         DEFINE_RES_MEM(0xffdc0000, 0x2c),
 216         DEFINE_RES_IRQ(evt2irq(0x7a0)),
 217         DEFINE_RES_IRQ(evt2irq(0x7a0)),
 218         DEFINE_RES_IRQ(evt2irq(0x7a0)),
 219 };
 220
 221 static struct platform_device tmu2_device = {
 222         .name           = "sh-tmu",
 223         .id             = 2,
 224         .dev = {
 225                 .platform_data  = &tmu2_platform_data,
 226         },
 227         .resource       = tmu2_resources,
 228         .num_resources  = ARRAY_SIZE(tmu2_resources),
 229 };
 230
 231 static struct sh_timer_config tmu3_platform_data = {
 232         .channels_mask = 7,
 233 };
 234
 235 static struct resource tmu3_resources[] = {
 236         DEFINE_RES_MEM(0xffde0000, 0x2c),
 237         DEFINE_RES_IRQ(evt2irq(0x7c0)),
 238         DEFINE_RES_IRQ(evt2irq(0x7c0)),
 239         DEFINE_RES_IRQ(evt2irq(0x7c0)),
 240 };
 241
 242 static struct platform_device tmu3_device = {
 243         .name           = "sh-tmu",
 244         .id             = 3,
 245         .dev = {
 246                 .platform_data  = &tmu3_platform_data,
 247         },
 248         .resource       = tmu3_resources,
 249         .num_resources  = ARRAY_SIZE(tmu3_resources),
 250 };
 251
 252 static const struct sh_dmae_channel dmac0_channels[] = {
 253         {
 254                 .offset = 0,
 255                 .dmars = 0,
 256                 .dmars_bit = 0,
 257         }, {
 258                 .offset = 0x10,
 259                 .dmars = 0,
 260                 .dmars_bit = 8,
 261         }, {
 262                 .offset = 0x20,
 263                 .dmars = 4,
 264                 .dmars_bit = 0,
 265         }, {
 266                 .offset = 0x30,
 267                 .dmars = 4,
 268                 .dmars_bit = 8,
 269         }, {
 270                 .offset = 0x50,
 271                 .dmars = 8,
 272                 .dmars_bit = 0,
 273         }, {
 274                 .offset = 0x60,
 275                 .dmars = 8,
 276                 .dmars_bit = 8,
 277         }
 278 };
 279
 280 static const unsigned int ts_shift[] = TS_SHIFT;
 281
 282 static struct sh_dmae_pdata dma0_platform_data = {
 283         .channel        = dmac0_channels,
 284         .channel_num    = ARRAY_SIZE(dmac0_channels),
 285         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 286         .ts_low_mask    = CHCR_TS_LOW_MASK,
 287         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 288         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 289         .ts_shift       = ts_shift,
 290         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 291         .dmaor_init     = DMAOR_INIT,
 292 };
 293
 294 /* Resource order important! */
 295 static struct resource dmac0_resources[] = {
 296         {
 297                 /* Channel registers and DMAOR */
 298                 .start  = 0xfe008020,
 299                 .end    = 0xfe00808f,
 300                 .flags  = IORESOURCE_MEM,
 301         }, {
 302                 /* DMARSx */
 303                 .start  = 0xfe009000,
 304                 .end    = 0xfe00900b,
 305                 .flags  = IORESOURCE_MEM,
 306         }, {
 307                 .name   = "error_irq",
 308                 .start  = evt2irq(0x5c0),
 309                 .end    = evt2irq(0x5c0),
 310                 .flags  = IORESOURCE_IRQ,
 311         }, {
 312                 /* IRQ for channels 0-5 */
 313                 .start  = evt2irq(0x500),
 314                 .end    = evt2irq(0x5a0),
 315                 .flags  = IORESOURCE_IRQ,
 316         },
 317 };
 318
 319 static struct platform_device dma0_device = {
 320         .name           = "sh-dma-engine",
 321         .id             = 0,
 322         .resource       = dmac0_resources,
 323         .num_resources  = ARRAY_SIZE(dmac0_resources),
 324         .dev            = {
 325                 .platform_data  = &dma0_platform_data,
 326         },
 327 };
 328
 329 #define USB_EHCI_START 0xffe70000
 330 #define USB_OHCI_START 0xffe70400
 331
 332 static struct resource usb_ehci_resources[] = {
 333         [0] = {
 334                 .start  = USB_EHCI_START,
 335                 .end    = USB_EHCI_START + 0x3ff,
 336                 .flags  = IORESOURCE_MEM,
 337         },
 338         [1] = {
 339                 .start  = evt2irq(0xba0),
 340                 .end    = evt2irq(0xba0),
 341                 .flags  = IORESOURCE_IRQ,
 342         },
 343 };
 344
 345 static struct platform_device usb_ehci_device = {
 346         .name           = "sh_ehci",
 347         .id             = -1,
 348         .dev = {
 349                 .dma_mask               = &usb_ehci_device.dev.coherent_dma_mask,
 350                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 351         },
 352         .num_resources  = ARRAY_SIZE(usb_ehci_resources),
 353         .resource       = usb_ehci_resources,
 354 };
 355
 356 static struct resource usb_ohci_resources[] = {
 357         [0] = {
 358                 .start  = USB_OHCI_START,
 359                 .end    = USB_OHCI_START + 0x3ff,
 360                 .flags  = IORESOURCE_MEM,
 361         },
 362         [1] = {
 363                 .start  = evt2irq(0xba0),
 364                 .end    = evt2irq(0xba0),
 365                 .flags  = IORESOURCE_IRQ,
 366         },
 367 };
 368
 369 static struct usb_ohci_pdata usb_ohci_pdata;
 370
 371 static struct platform_device usb_ohci_device = {
 372         .name           = "ohci-platform",
 373         .id             = -1,
 374         .dev = {
 375                 .dma_mask               = &usb_ohci_device.dev.coherent_dma_mask,
 376                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 377                 .platform_data          = &usb_ohci_pdata,
 378         },
 379         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 380         .resource       = usb_ohci_resources,
 381 };
 382
 383 static struct platform_device *sh7786_early_devices[] __initdata = {
 384         &scif0_device,
 385         &scif1_device,
 386         &scif2_device,
 387         &scif3_device,
 388         &scif4_device,
 389         &scif5_device,
 390         &tmu0_device,
 391         &tmu1_device,
 392         &tmu2_device,
 393 };
 394
 395 static struct platform_device *sh7786_devices[] __initdata = {
 396         &dma0_device,
 397         &usb_ehci_device,
 398         &usb_ohci_device,
 399 };
 400
 401 /*
 402  * Please call this function if your platform board
 403  * use external clock for USB
 404  * */
 405 #define USBCTL0         0xffe70858
 406 #define CLOCK_MODE_MASK 0xffffff7f
 407 #define EXT_CLOCK_MODE  0x00000080
 408
 409 void __init sh7786_usb_use_exclock(void)
 410 {
 411         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
 412         __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
 413 }
 414
 415 #define USBINITREG1     0xffe70094
 416 #define USBINITREG2     0xffe7009c
 417 #define USBINITVAL1     0x00ff0040
 418 #define USBINITVAL2     0x00000001
 419
 420 #define USBPCTL1        0xffe70804
 421 #define USBST           0xffe70808
 422 #define PHY_ENB         0x00000001
 423 #define PLL_ENB         0x00000002
 424 #define PHY_RST         0x00000004
 425 #define ACT_PLL_STATUS  0xc0000000
 426
 427 static void __init sh7786_usb_setup(void)
 428 {
 429         int i = 1000000;
 430
 431         /*
 432          * USB initial settings
 433          *
 434          * The following settings are necessary
 435          * for using the USB modules.
 436          *
 437          * see "USB Initial Settings" for detail
 438          */
 439         __raw_writel(USBINITVAL1, USBINITREG1);
 440         __raw_writel(USBINITVAL2, USBINITREG2);
 441
 442         /*
 443          * Set the PHY and PLL enable bit
 444          */
 445         __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
 446         while (i--) {
 447                 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
 448                         /* Set the PHY RST bit */
 449                         __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
 450                         printk(KERN_INFO "sh7786 usb setup done\n");
 451                         break;
 452                 }
 453                 cpu_relax();
 454         }
 455 }
 456
 457 enum {
 458         UNUSED = 0,
 459
 460         /* interrupt sources */
 461         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 462         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 463         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 464         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 465
 466         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 467         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 468         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 469         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 470
 471         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 472         WDT,
 473         TMU0_0, TMU0_1, TMU0_2, TMU0_3,
 474         TMU1_0, TMU1_1, TMU1_2,
 475         DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 476         HUDI1, HUDI0,
 477         DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 478         HPB_0, HPB_1, HPB_2,
 479         SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 480         SCIF1,
 481         TMU2, TMU3,
 482         SCIF2, SCIF3, SCIF4, SCIF5,
 483         Eth_0, Eth_1,
 484         PCIeC0_0, PCIeC0_1, PCIeC0_2,
 485         PCIeC1_0, PCIeC1_1, PCIeC1_2,
 486         USB,
 487         I2C0, I2C1,
 488         DU,
 489         SSI0, SSI1, SSI2, SSI3,
 490         PCIeC2_0, PCIeC2_1, PCIeC2_2,
 491         HAC0, HAC1,
 492         FLCTL,
 493         HSPI,
 494         GPIO0, GPIO1,
 495         Thermal,
 496         INTICI0, INTICI1, INTICI2, INTICI3,
 497         INTICI4, INTICI5, INTICI6, INTICI7,
 498
 499         /* Muxed sub-events */
 500         TXI1, BRI1, RXI1, ERI1,
 501 };
 502
 503 static struct intc_vect sh7786_vectors[] __initdata = {
 504         INTC_VECT(WDT, 0x3e0),
 505         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
 506         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
 507         INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
 508         INTC_VECT(TMU1_2, 0x4c0),
 509         INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
 510         INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
 511         INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
 512         INTC_VECT(DMAC0_6, 0x5c0),
 513         INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
 514         INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
 515         INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
 516         INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
 517         INTC_VECT(HPB_2, 0x6e0),
 518         INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
 519         INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
 520         INTC_VECT(SCIF1, 0x780),
 521         INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
 522         INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
 523         INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
 524         INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
 525         INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
 526         INTC_VECT(PCIeC0_2, 0xb20),
 527         INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
 528         INTC_VECT(PCIeC1_2, 0xb80),
 529         INTC_VECT(USB, 0xba0),
 530         INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
 531         INTC_VECT(DU, 0xd00),
 532         INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
 533         INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
 534         INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
 535         INTC_VECT(PCIeC2_2, 0xde0),
 536         INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
 537         INTC_VECT(FLCTL, 0xe40),
 538         INTC_VECT(HSPI, 0xe80),
 539         INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
 540         INTC_VECT(Thermal, 0xee0),
 541         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
 542         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
 543         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
 544         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 545 };
 546
 547 #define CnINTMSK0       0xfe410030
 548 #define CnINTMSK1       0xfe410040
 549 #define CnINTMSKCLR0    0xfe410050
 550 #define CnINTMSKCLR1    0xfe410060
 551 #define CnINT2MSKR0     0xfe410a20
 552 #define CnINT2MSKR1     0xfe410a24
 553 #define CnINT2MSKR2     0xfe410a28
 554 #define CnINT2MSKR3     0xfe410a2c
 555 #define CnINT2MSKCR0    0xfe410a30
 556 #define CnINT2MSKCR1    0xfe410a34
 557 #define CnINT2MSKCR2    0xfe410a38
 558 #define CnINT2MSKCR3    0xfe410a3c
 559 #define INTMSK2         0xfe410068
 560 #define INTMSKCLR2      0xfe41006c
 561
 562 #define INTDISTCR0      0xfe4100b0
 563 #define INTDISTCR1      0xfe4100b4
 564 #define INT2DISTCR0     0xfe410900
 565 #define INT2DISTCR1     0xfe410904
 566 #define INT2DISTCR2     0xfe410908
 567 #define INT2DISTCR3     0xfe41090c
 568
 569 static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
 570         { CnINTMSK0, CnINTMSKCLR0, 32,
 571           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
 572             INTC_SMP_BALANCING(INTDISTCR0) },
 573         { INTMSK2, INTMSKCLR2, 32,
 574           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 575             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 576             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 577             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 578             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 579             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 580             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 581             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 582         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
 583           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 584             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
 585             INTC_SMP_BALANCING(INT2DISTCR0) },
 586         { CnINT2MSKR1, CnINT2MSKCR1, 32,
 587           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
 588             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 589             HUDI1, HUDI0,
 590             DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 591             HPB_0, HPB_1, HPB_2,
 592             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 593             SCIF1,
 594             TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
 595         { CnINT2MSKR2, CnINT2MSKCR2, 32,
 596           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
 597             Eth_0, Eth_1,
 598             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 599             PCIeC0_0, PCIeC0_1, PCIeC0_2,
 600             PCIeC1_0, PCIeC1_1, PCIeC1_2,
 601             USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
 602         { CnINT2MSKR3, CnINT2MSKCR3, 32,
 603           { 0, 0, 0, 0, 0, 0,
 604             I2C0, I2C1,
 605             DU, SSI0, SSI1, SSI2, SSI3,
 606             PCIeC2_0, PCIeC2_1, PCIeC2_2,
 607             HAC0, HAC1,
 608             FLCTL, 0,
 609             HSPI, GPIO0, GPIO1, Thermal,
 610             0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
 611 };
 612
 613 static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
 614         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 615                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 616         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
 617         { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
 618                                                  TMU0_2, TMU0_3 } },
 619         { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
 620                                                  TMU1_2, 0 } },
 621         { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
 622                                                  DMAC0_2, DMAC0_3 } },
 623         { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
 624                                                  DMAC0_6, HUDI1 } },
 625         { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
 626                                                  DMAC1_1, DMAC1_2 } },
 627         { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
 628                                                  HPB_1, HPB_2 } },
 629         { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
 630                                                  SCIF0_2, SCIF0_3 } },
 631         { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
 632         { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
 633         { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
 634                                                   Eth_0, Eth_1 } },
 635         { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
 636         { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
 637         { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
 638         { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
 639         { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
 640                                                   PCIeC1_0, PCIeC1_1 } },
 641         { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
 642         { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
 643         { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
 644         { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
 645         { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
 646                                                   PCIeC2_1, PCIeC2_2 } },
 647         { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
 648         { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
 649                                                   GPIO1, Thermal } },
 650         { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
 651         { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
 652         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
 653           { INTICI7, INTICI6, INTICI5, INTICI4,
 654             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
 655 };
 656
 657 static struct intc_subgroup sh7786_subgroups[] __initdata = {
 658         { 0xfe410c20, 32, SCIF1,
 659           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 660             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
 661 };
 662
 663 static struct intc_desc sh7786_intc_desc __initdata = {
 664         .name           = "sh7786",
 665         .hw             = {
 666                 .vectors        = sh7786_vectors,
 667                 .nr_vectors     = ARRAY_SIZE(sh7786_vectors),
 668                 .mask_regs      = sh7786_mask_registers,
 669                 .nr_mask_regs   = ARRAY_SIZE(sh7786_mask_registers),
 670                 .subgroups      = sh7786_subgroups,
 671                 .nr_subgroups   = ARRAY_SIZE(sh7786_subgroups),
 672                 .prio_regs      = sh7786_prio_registers,
 673                 .nr_prio_regs   = ARRAY_SIZE(sh7786_prio_registers),
 674         },
 675 };
 676
 677 /* Support for external interrupt pins in IRQ mode */
 678 static struct intc_vect vectors_irq0123[] __initdata = {
 679         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
 680         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
 681 };
 682
 683 static struct intc_vect vectors_irq4567[] __initdata = {
 684         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
 685         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 686 };
 687
 688 static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
 689         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 690                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 691 };
 692
 693 static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
 694         { 0xfe410024, 0, 32, /* INTREQ */
 695           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 696 };
 697
 698 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
 699                              vectors_irq0123, NULL, sh7786_mask_registers,
 700                              sh7786_prio_registers, sh7786_sense_registers,
 701                              sh7786_ack_registers);
 702
 703 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
 704                              vectors_irq4567, NULL, sh7786_mask_registers,
 705                              sh7786_prio_registers, sh7786_sense_registers,
 706                              sh7786_ack_registers);
 707
 708 /* External interrupt pins in IRL mode */
 709
 710 static struct intc_vect vectors_irl0123[] __initdata = {
 711         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 712         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 713         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 714         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 715         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 716         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 717         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 718         INTC_VECT(IRL0_HHHL, 0x3c0),
 719 };
 720
 721 static struct intc_vect vectors_irl4567[] __initdata = {
 722         INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
 723         INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
 724         INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
 725         INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
 726         INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
 727         INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
 728         INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
 729         INTC_VECT(IRL4_HHHL, 0xac0),
 730 };
 731
 732 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
 733                          NULL, sh7786_mask_registers, NULL, NULL);
 734
 735 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 736                          NULL, sh7786_mask_registers, NULL, NULL);
 737
 738 #define INTC_ICR0       0xfe410000
 739 #define INTC_INTMSK0    CnINTMSK0
 740 #define INTC_INTMSK1    CnINTMSK1
 741 #define INTC_INTMSK2    INTMSK2
 742 #define INTC_INTMSKCLR1 CnINTMSKCLR1
 743 #define INTC_INTMSKCLR2 INTMSKCLR2
 744
 745 void __init plat_irq_setup(void)
 746 {
 747         /* disable IRQ3-0 + IRQ7-4 */
 748         __raw_writel(0xff000000, INTC_INTMSK0);
 749
 750         /* disable IRL3-0 + IRL7-4 */
 751         __raw_writel(0xc0000000, INTC_INTMSK1);
 752         __raw_writel(0xfffefffe, INTC_INTMSK2);
 753
 754         /* select IRL mode for IRL3-0 + IRL7-4 */
 755         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 756
 757         register_intc_controller(&sh7786_intc_desc);
 758 }
 759
 760 void __init plat_irq_setup_pins(int mode)
 761 {
 762         switch (mode) {
 763         case IRQ_MODE_IRQ7654:
 764                 /* select IRQ mode for IRL7-4 */
 765                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 766                 register_intc_controller(&intc_desc_irq4567);
 767                 break;
 768         case IRQ_MODE_IRQ3210:
 769                 /* select IRQ mode for IRL3-0 */
 770                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 771                 register_intc_controller(&intc_desc_irq0123);
 772                 break;
 773         case IRQ_MODE_IRL7654:
 774                 /* enable IRL7-4 but don't provide any masking */
 775                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 776                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 777                 break;
 778         case IRQ_MODE_IRL3210:
 779                 /* enable IRL0-3 but don't provide any masking */
 780                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 781                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 782                 break;
 783         case IRQ_MODE_IRL7654_MASK:
 784                 /* enable IRL7-4 and mask using cpu intc controller */
 785                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 786                 register_intc_controller(&intc_desc_irl4567);
 787                 break;
 788         case IRQ_MODE_IRL3210_MASK:
 789                 /* enable IRL0-3 and mask using cpu intc controller */
 790                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 791                 register_intc_controller(&intc_desc_irl0123);
 792                 break;
 793         default:
 794                 BUG();
 795         }
 796 }
 797
 798 void __init plat_mem_setup(void)
 799 {
 800 }
 801
 802 static int __init sh7786_devices_setup(void)
 803 {
 804         int ret, irq;
 805
 806         sh7786_usb_setup();
 807
 808         /*
 809          * De-mux SCIF1 IRQs if possible
 810          */
 811         irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
 812         if (irq > 0) {
 813                 scif1_demux_resources[1].start =
 814                         intc_irq_lookup(sh7786_intc_desc.name, ERI1);
 815                 scif1_demux_resources[2].start =
 816                         intc_irq_lookup(sh7786_intc_desc.name, RXI1);
 817                 scif1_demux_resources[3].start = irq;
 818                 scif1_demux_resources[4].start =
 819                         intc_irq_lookup(sh7786_intc_desc.name, BRI1);
 820
 821                 scif1_device.resource = scif1_demux_resources;
 822                 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
 823         }
 824
 825         ret = platform_add_devices(sh7786_early_devices,
 826                                    ARRAY_SIZE(sh7786_early_devices));
 827         if (unlikely(ret != 0))
 828                 return ret;
 829
 830         return platform_add_devices(sh7786_devices,
 831                                     ARRAY_SIZE(sh7786_devices));
 832 }
 833 arch_initcall(sh7786_devices_setup);
 834
 835 void __init plat_early_device_setup(void)
 836 {
 837         early_platform_add_devices(sh7786_early_devices,
 838                                    ARRAY_SIZE(sh7786_early_devices));
 839 }