arch/sh/kernel/cpu/sh4a/setup-sh7780.c

   1 /*
   2  * SH7780 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/io.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16
  17 #include <asm/dmaengine.h>
  18
  19 #include <cpu/dma-register.h>
  20
  21 static struct plat_sci_port scif0_platform_data = {
  22         .mapbase        = 0xffe00000,
  23         .flags          = UPF_BOOT_AUTOCONF,
  24         .type           = PORT_SCIF,
  25         .irqs           = { 40, 40, 40, 40 },
  26 };
  27
  28 static struct platform_device scif0_device = {
  29         .name           = "sh-sci",
  30         .id             = 0,
  31         .dev            = {
  32                 .platform_data  = &scif0_platform_data,
  33         },
  34 };
  35
  36 static struct plat_sci_port scif1_platform_data = {
  37         .mapbase        = 0xffe10000,
  38         .flags          = UPF_BOOT_AUTOCONF,
  39         .type           = PORT_SCIF,
  40         .irqs           = { 76, 76, 76, 76 },
  41 };
  42
  43 static struct platform_device scif1_device = {
  44         .name           = "sh-sci",
  45         .id             = 1,
  46         .dev            = {
  47                 .platform_data  = &scif1_platform_data,
  48         },
  49 };
  50
  51 static struct sh_timer_config tmu0_platform_data = {
  52         .channel_offset = 0x04,
  53         .timer_bit = 0,
  54         .clockevent_rating = 200,
  55 };
  56
  57 static struct resource tmu0_resources[] = {
  58         [0] = {
  59                 .start  = 0xffd80008,
  60                 .end    = 0xffd80013,
  61                 .flags  = IORESOURCE_MEM,
  62         },
  63         [1] = {
  64                 .start  = 28,
  65                 .flags  = IORESOURCE_IRQ,
  66         },
  67 };
  68
  69 static struct platform_device tmu0_device = {
  70         .name           = "sh_tmu",
  71         .id             = 0,
  72         .dev = {
  73                 .platform_data  = &tmu0_platform_data,
  74         },
  75         .resource       = tmu0_resources,
  76         .num_resources  = ARRAY_SIZE(tmu0_resources),
  77 };
  78
  79 static struct sh_timer_config tmu1_platform_data = {
  80         .channel_offset = 0x10,
  81         .timer_bit = 1,
  82         .clocksource_rating = 200,
  83 };
  84
  85 static struct resource tmu1_resources[] = {
  86         [0] = {
  87                 .start  = 0xffd80014,
  88                 .end    = 0xffd8001f,
  89                 .flags  = IORESOURCE_MEM,
  90         },
  91         [1] = {
  92                 .start  = 29,
  93                 .flags  = IORESOURCE_IRQ,
  94         },
  95 };
  96
  97 static struct platform_device tmu1_device = {
  98         .name           = "sh_tmu",
  99         .id             = 1,
 100         .dev = {
 101                 .platform_data  = &tmu1_platform_data,
 102         },
 103         .resource       = tmu1_resources,
 104         .num_resources  = ARRAY_SIZE(tmu1_resources),
 105 };
 106
 107 static struct sh_timer_config tmu2_platform_data = {
 108         .channel_offset = 0x1c,
 109         .timer_bit = 2,
 110 };
 111
 112 static struct resource tmu2_resources[] = {
 113         [0] = {
 114                 .start  = 0xffd80020,
 115                 .end    = 0xffd8002f,
 116                 .flags  = IORESOURCE_MEM,
 117         },
 118         [1] = {
 119                 .start  = 30,
 120                 .flags  = IORESOURCE_IRQ,
 121         },
 122 };
 123
 124 static struct platform_device tmu2_device = {
 125         .name           = "sh_tmu",
 126         .id             = 2,
 127         .dev = {
 128                 .platform_data  = &tmu2_platform_data,
 129         },
 130         .resource       = tmu2_resources,
 131         .num_resources  = ARRAY_SIZE(tmu2_resources),
 132 };
 133
 134 static struct sh_timer_config tmu3_platform_data = {
 135         .channel_offset = 0x04,
 136         .timer_bit = 0,
 137 };
 138
 139 static struct resource tmu3_resources[] = {
 140         [0] = {
 141                 .start  = 0xffdc0008,
 142                 .end    = 0xffdc0013,
 143                 .flags  = IORESOURCE_MEM,
 144         },
 145         [1] = {
 146                 .start  = 96,
 147                 .flags  = IORESOURCE_IRQ,
 148         },
 149 };
 150
 151 static struct platform_device tmu3_device = {
 152         .name           = "sh_tmu",
 153         .id             = 3,
 154         .dev = {
 155                 .platform_data  = &tmu3_platform_data,
 156         },
 157         .resource       = tmu3_resources,
 158         .num_resources  = ARRAY_SIZE(tmu3_resources),
 159 };
 160
 161 static struct sh_timer_config tmu4_platform_data = {
 162         .channel_offset = 0x10,
 163         .timer_bit = 1,
 164 };
 165
 166 static struct resource tmu4_resources[] = {
 167         [0] = {
 168                 .start  = 0xffdc0014,
 169                 .end    = 0xffdc001f,
 170                 .flags  = IORESOURCE_MEM,
 171         },
 172         [1] = {
 173                 .start  = 97,
 174                 .flags  = IORESOURCE_IRQ,
 175         },
 176 };
 177
 178 static struct platform_device tmu4_device = {
 179         .name           = "sh_tmu",
 180         .id             = 4,
 181         .dev = {
 182                 .platform_data  = &tmu4_platform_data,
 183         },
 184         .resource       = tmu4_resources,
 185         .num_resources  = ARRAY_SIZE(tmu4_resources),
 186 };
 187
 188 static struct sh_timer_config tmu5_platform_data = {
 189         .channel_offset = 0x1c,
 190         .timer_bit = 2,
 191 };
 192
 193 static struct resource tmu5_resources[] = {
 194         [0] = {
 195                 .start  = 0xffdc0020,
 196                 .end    = 0xffdc002b,
 197                 .flags  = IORESOURCE_MEM,
 198         },
 199         [1] = {
 200                 .start  = 98,
 201                 .flags  = IORESOURCE_IRQ,
 202         },
 203 };
 204
 205 static struct platform_device tmu5_device = {
 206         .name           = "sh_tmu",
 207         .id             = 5,
 208         .dev = {
 209                 .platform_data  = &tmu5_platform_data,
 210         },
 211         .resource       = tmu5_resources,
 212         .num_resources  = ARRAY_SIZE(tmu5_resources),
 213 };
 214
 215 static struct resource rtc_resources[] = {
 216         [0] = {
 217                 .start  = 0xffe80000,
 218                 .end    = 0xffe80000 + 0x58 - 1,
 219                 .flags  = IORESOURCE_IO,
 220         },
 221         [1] = {
 222                 /* Shared Period/Carry/Alarm IRQ */
 223                 .start  = 20,
 224                 .flags  = IORESOURCE_IRQ,
 225         },
 226 };
 227
 228 static struct platform_device rtc_device = {
 229         .name           = "sh-rtc",
 230         .id             = -1,
 231         .num_resources  = ARRAY_SIZE(rtc_resources),
 232         .resource       = rtc_resources,
 233 };
 234
 235 /* DMA */
 236 static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
 237         {
 238                 .offset = 0,
 239                 .dmars = 0,
 240                 .dmars_bit = 0,
 241         }, {
 242                 .offset = 0x10,
 243                 .dmars = 0,
 244                 .dmars_bit = 8,
 245         }, {
 246                 .offset = 0x20,
 247                 .dmars = 4,
 248                 .dmars_bit = 0,
 249         }, {
 250                 .offset = 0x30,
 251                 .dmars = 4,
 252                 .dmars_bit = 8,
 253         }, {
 254                 .offset = 0x50,
 255                 .dmars = 8,
 256                 .dmars_bit = 0,
 257         }, {
 258                 .offset = 0x60,
 259                 .dmars = 8,
 260                 .dmars_bit = 8,
 261         }
 262 };
 263
 264 static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
 265         {
 266                 .offset = 0,
 267         }, {
 268                 .offset = 0x10,
 269         }, {
 270                 .offset = 0x20,
 271         }, {
 272                 .offset = 0x30,
 273         }, {
 274                 .offset = 0x50,
 275         }, {
 276                 .offset = 0x60,
 277         }
 278 };
 279
 280 static const unsigned int ts_shift[] = TS_SHIFT;
 281
 282 static struct sh_dmae_pdata dma0_platform_data = {
 283         .channel        = sh7780_dmae0_channels,
 284         .channel_num    = ARRAY_SIZE(sh7780_dmae0_channels),
 285         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 286         .ts_low_mask    = CHCR_TS_LOW_MASK,
 287         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 288         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 289         .ts_shift       = ts_shift,
 290         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 291         .dmaor_init     = DMAOR_INIT,
 292 };
 293
 294 static struct sh_dmae_pdata dma1_platform_data = {
 295         .channel        = sh7780_dmae1_channels,
 296         .channel_num    = ARRAY_SIZE(sh7780_dmae1_channels),
 297         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 298         .ts_low_mask    = CHCR_TS_LOW_MASK,
 299         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 300         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 301         .ts_shift       = ts_shift,
 302         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 303         .dmaor_init     = DMAOR_INIT,
 304 };
 305
 306 static struct resource sh7780_dmae0_resources[] = {
 307         [0] = {
 308                 /* Channel registers and DMAOR */
 309                 .start  = 0xfc808020,
 310                 .end    = 0xfc80808f,
 311                 .flags  = IORESOURCE_MEM,
 312         },
 313         [1] = {
 314                 /* DMARSx */
 315                 .start  = 0xfc809000,
 316                 .end    = 0xfc80900b,
 317                 .flags  = IORESOURCE_MEM,
 318         },
 319         {
 320                 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
 321                 .start  = 34,
 322                 .end    = 34,
 323                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 324         },
 325 };
 326
 327 static struct resource sh7780_dmae1_resources[] = {
 328         [0] = {
 329                 /* Channel registers and DMAOR */
 330                 .start  = 0xfc818020,
 331                 .end    = 0xfc81808f,
 332                 .flags  = IORESOURCE_MEM,
 333         },
 334         /* DMAC1 has no DMARS */
 335         {
 336                 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
 337                 .start  = 46,
 338                 .end    = 46,
 339                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 340         },
 341 };
 342
 343 static struct platform_device dma0_device = {
 344         .name           = "sh-dma-engine",
 345         .id             = 0,
 346         .resource       = sh7780_dmae0_resources,
 347         .num_resources  = ARRAY_SIZE(sh7780_dmae0_resources),
 348         .dev            = {
 349                 .platform_data  = &dma0_platform_data,
 350         },
 351 };
 352
 353 static struct platform_device dma1_device = {
 354         .name           = "sh-dma-engine",
 355         .id             = 1,
 356         .resource       = sh7780_dmae1_resources,
 357         .num_resources  = ARRAY_SIZE(sh7780_dmae1_resources),
 358         .dev            = {
 359                 .platform_data  = &dma1_platform_data,
 360         },
 361 };
 362
 363 static struct platform_device *sh7780_devices[] __initdata = {
 364         &scif0_device,
 365         &scif1_device,
 366         &tmu0_device,
 367         &tmu1_device,
 368         &tmu2_device,
 369         &tmu3_device,
 370         &tmu4_device,
 371         &tmu5_device,
 372         &rtc_device,
 373         &dma0_device,
 374         &dma1_device,
 375 };
 376
 377 static int __init sh7780_devices_setup(void)
 378 {
 379         return platform_add_devices(sh7780_devices,
 380                                     ARRAY_SIZE(sh7780_devices));
 381 }
 382 arch_initcall(sh7780_devices_setup);
 383 static struct platform_device *sh7780_early_devices[] __initdata = {
 384         &scif0_device,
 385         &scif1_device,
 386         &tmu0_device,
 387         &tmu1_device,
 388         &tmu2_device,
 389         &tmu3_device,
 390         &tmu4_device,
 391         &tmu5_device,
 392 };
 393
 394 void __init plat_early_device_setup(void)
 395 {
 396         early_platform_add_devices(sh7780_early_devices,
 397                                    ARRAY_SIZE(sh7780_early_devices));
 398 }
 399
 400 enum {
 401         UNUSED = 0,
 402
 403         /* interrupt sources */
 404
 405         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 406         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 407         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 408         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 409
 410         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 411         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 412         HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
 413         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 414         SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
 415
 416         /* interrupt groups */
 417
 418         TMU012, TMU345,
 419 };
 420
 421 static struct intc_vect vectors[] __initdata = {
 422         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 423         INTC_VECT(RTC, 0x4c0),
 424         INTC_VECT(WDT, 0x560),
 425         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 426         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 427         INTC_VECT(HUDI, 0x600),
 428         INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
 429         INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
 430         INTC_VECT(DMAC0, 0x6c0),
 431         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 432         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 433         INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
 434         INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
 435         INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
 436         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 437         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 438         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 439         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 440         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 441         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 442         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 443         INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
 444         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 445         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 446         INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
 447         INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
 448         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 449         INTC_VECT(TMU5, 0xe40),
 450         INTC_VECT(SSI, 0xe80),
 451         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 452         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 453         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 454         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 455 };
 456
 457 static struct intc_group groups[] __initdata = {
 458         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 459         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 460 };
 461
 462 static struct intc_mask_reg mask_registers[] __initdata = {
 463         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 464           { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
 465             SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 466             PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
 467             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 468 };
 469
 470 static struct intc_prio_reg prio_registers[] __initdata = {
 471         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 472                                                  TMU2, TMU2_TICPI } },
 473         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 474         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 475         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
 476         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 477                                                  PCISERR, PCIINTA, } },
 478         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 479                                                  PCIINTD, PCIC5 } },
 480         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
 481         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
 482 };
 483
 484 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
 485                          mask_registers, prio_registers, NULL);
 486
 487 /* Support for external interrupt pins in IRQ mode */
 488
 489 static struct intc_vect irq_vectors[] __initdata = {
 490         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 491         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 492         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 493         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 494 };
 495
 496 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 497         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 498           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 499 };
 500
 501 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 502         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 503                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 504 };
 505
 506 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 507         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 508                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 509 };
 510
 511 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 512         { 0xffd00024, 0, 32, /* INTREQ */
 513           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 514 };
 515
 516 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
 517                              NULL, irq_mask_registers, irq_prio_registers,
 518                              irq_sense_registers, irq_ack_registers);
 519
 520 /* External interrupt pins in IRL mode */
 521
 522 static struct intc_vect irl_vectors[] __initdata = {
 523         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 524         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 525         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 526         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 527         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 528         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 529         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 530         INTC_VECT(IRL_HHHL, 0x3c0),
 531 };
 532
 533 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 534         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 535           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 536             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 537             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 538             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 539 };
 540
 541 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 542         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 543           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 544             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 545             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 546             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 547             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 548 };
 549
 550 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 551                          NULL, irl7654_mask_registers, NULL, NULL);
 552
 553 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 554                          NULL, irl3210_mask_registers, NULL, NULL);
 555
 556 #define INTC_ICR0       0xffd00000
 557 #define INTC_INTMSK0    0xffd00044
 558 #define INTC_INTMSK1    0xffd00048
 559 #define INTC_INTMSK2    0xffd40080
 560 #define INTC_INTMSKCLR1 0xffd00068
 561 #define INTC_INTMSKCLR2 0xffd40084
 562
 563 void __init plat_irq_setup(void)
 564 {
 565         /* disable IRQ7-0 */
 566         __raw_writel(0xff000000, INTC_INTMSK0);
 567
 568         /* disable IRL3-0 + IRL7-4 */
 569         __raw_writel(0xc0000000, INTC_INTMSK1);
 570         __raw_writel(0xfffefffe, INTC_INTMSK2);
 571
 572         /* select IRL mode for IRL3-0 + IRL7-4 */
 573         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 574
 575         /* disable holding function, ie enable "SH-4 Mode" */
 576         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 577
 578         register_intc_controller(&intc_desc);
 579 }
 580
 581 void __init plat_irq_setup_pins(int mode)
 582 {
 583         switch (mode) {
 584         case IRQ_MODE_IRQ:
 585                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 586                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 587                 register_intc_controller(&intc_irq_desc);
 588                 break;
 589         case IRQ_MODE_IRL7654:
 590                 /* enable IRL7-4 but don't provide any masking */
 591                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 592                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 593                 break;
 594         case IRQ_MODE_IRL3210:
 595                 /* enable IRL0-3 but don't provide any masking */
 596                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 597                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 598                 break;
 599         case IRQ_MODE_IRL7654_MASK:
 600                 /* enable IRL7-4 and mask using cpu intc controller */
 601                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 602                 register_intc_controller(&intc_irl7654_desc);
 603                 break;
 604         case IRQ_MODE_IRL3210_MASK:
 605                 /* enable IRL0-3 and mask using cpu intc controller */
 606                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 607                 register_intc_controller(&intc_irl3210_desc);
 608                 break;
 609         default:
 610                 BUG();
 611         }
 612 }