arch/sh/kernel/cpu/sh4a/setup-sh7770.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH7770 Setup
   4  *
   5  *  Copyright (C) 2006 - 2008  Paul Mundt
   6  */
   7 #include <linux/platform_device.h>
   8 #include <linux/init.h>
   9 #include <linux/serial.h>
  10 #include <linux/serial_sci.h>
  11 #include <linux/sh_timer.h>
  12 #include <linux/sh_intc.h>
  13 #include <linux/io.h>
  14 #include <asm/platform_early.h>
  15
  16 static struct plat_sci_port scif0_platform_data = {
  17         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  18         .type           = PORT_SCIF,
  19 };
  20
  21 static struct resource scif0_resources[] = {
  22         DEFINE_RES_MEM(0xff923000, 0x100),
  23         DEFINE_RES_IRQ(evt2irq(0x9a0)),
  24 };
  25
  26 static struct platform_device scif0_device = {
  27         .name           = "sh-sci",
  28         .id             = 0,
  29         .resource       = scif0_resources,
  30         .num_resources  = ARRAY_SIZE(scif0_resources),
  31         .dev            = {
  32                 .platform_data  = &scif0_platform_data,
  33         },
  34 };
  35
  36 static struct plat_sci_port scif1_platform_data = {
  37         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  38         .type           = PORT_SCIF,
  39 };
  40
  41 static struct resource scif1_resources[] = {
  42         DEFINE_RES_MEM(0xff924000, 0x100),
  43         DEFINE_RES_IRQ(evt2irq(0x9c0)),
  44 };
  45
  46 static struct platform_device scif1_device = {
  47         .name           = "sh-sci",
  48         .id             = 1,
  49         .resource       = scif1_resources,
  50         .num_resources  = ARRAY_SIZE(scif1_resources),
  51         .dev            = {
  52                 .platform_data  = &scif1_platform_data,
  53         },
  54 };
  55
  56 static struct plat_sci_port scif2_platform_data = {
  57         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  58         .type           = PORT_SCIF,
  59 };
  60
  61 static struct resource scif2_resources[] = {
  62         DEFINE_RES_MEM(0xff925000, 0x100),
  63         DEFINE_RES_IRQ(evt2irq(0x9e0)),
  64 };
  65
  66 static struct platform_device scif2_device = {
  67         .name           = "sh-sci",
  68         .id             = 2,
  69         .resource       = scif2_resources,
  70         .num_resources  = ARRAY_SIZE(scif2_resources),
  71         .dev            = {
  72                 .platform_data  = &scif2_platform_data,
  73         },
  74 };
  75
  76 static struct plat_sci_port scif3_platform_data = {
  77         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  78         .type           = PORT_SCIF,
  79 };
  80
  81 static struct resource scif3_resources[] = {
  82         DEFINE_RES_MEM(0xff926000, 0x100),
  83         DEFINE_RES_IRQ(evt2irq(0xa00)),
  84 };
  85
  86 static struct platform_device scif3_device = {
  87         .name           = "sh-sci",
  88         .id             = 3,
  89         .resource       = scif3_resources,
  90         .num_resources  = ARRAY_SIZE(scif3_resources),
  91         .dev            = {
  92                 .platform_data  = &scif3_platform_data,
  93         },
  94 };
  95
  96 static struct plat_sci_port scif4_platform_data = {
  97         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  98         .type           = PORT_SCIF,
  99 };
 100
 101 static struct resource scif4_resources[] = {
 102         DEFINE_RES_MEM(0xff927000, 0x100),
 103         DEFINE_RES_IRQ(evt2irq(0xa20)),
 104 };
 105
 106 static struct platform_device scif4_device = {
 107         .name           = "sh-sci",
 108         .id             = 4,
 109         .resource       = scif4_resources,
 110         .num_resources  = ARRAY_SIZE(scif4_resources),
 111         .dev            = {
 112                 .platform_data  = &scif4_platform_data,
 113         },
 114 };
 115
 116 static struct plat_sci_port scif5_platform_data = {
 117         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 118         .type           = PORT_SCIF,
 119 };
 120
 121 static struct resource scif5_resources[] = {
 122         DEFINE_RES_MEM(0xff928000, 0x100),
 123         DEFINE_RES_IRQ(evt2irq(0xa40)),
 124 };
 125
 126 static struct platform_device scif5_device = {
 127         .name           = "sh-sci",
 128         .id             = 5,
 129         .resource       = scif5_resources,
 130         .num_resources  = ARRAY_SIZE(scif5_resources),
 131         .dev            = {
 132                 .platform_data  = &scif5_platform_data,
 133         },
 134 };
 135
 136 static struct plat_sci_port scif6_platform_data = {
 137         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 138         .type           = PORT_SCIF,
 139 };
 140
 141 static struct resource scif6_resources[] = {
 142         DEFINE_RES_MEM(0xff929000, 0x100),
 143         DEFINE_RES_IRQ(evt2irq(0xa60)),
 144 };
 145
 146 static struct platform_device scif6_device = {
 147         .name           = "sh-sci",
 148         .id             = 6,
 149         .resource       = scif6_resources,
 150         .num_resources  = ARRAY_SIZE(scif6_resources),
 151         .dev            = {
 152                 .platform_data  = &scif6_platform_data,
 153         },
 154 };
 155
 156 static struct plat_sci_port scif7_platform_data = {
 157         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 158         .type           = PORT_SCIF,
 159 };
 160
 161 static struct resource scif7_resources[] = {
 162         DEFINE_RES_MEM(0xff92a000, 0x100),
 163         DEFINE_RES_IRQ(evt2irq(0xa80)),
 164 };
 165
 166 static struct platform_device scif7_device = {
 167         .name           = "sh-sci",
 168         .id             = 7,
 169         .resource       = scif7_resources,
 170         .num_resources  = ARRAY_SIZE(scif7_resources),
 171         .dev            = {
 172                 .platform_data  = &scif7_platform_data,
 173         },
 174 };
 175
 176 static struct plat_sci_port scif8_platform_data = {
 177         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 178         .type           = PORT_SCIF,
 179 };
 180
 181 static struct resource scif8_resources[] = {
 182         DEFINE_RES_MEM(0xff92b000, 0x100),
 183         DEFINE_RES_IRQ(evt2irq(0xaa0)),
 184 };
 185
 186 static struct platform_device scif8_device = {
 187         .name           = "sh-sci",
 188         .id             = 8,
 189         .resource       = scif8_resources,
 190         .num_resources  = ARRAY_SIZE(scif8_resources),
 191         .dev            = {
 192                 .platform_data  = &scif8_platform_data,
 193         },
 194 };
 195
 196 static struct plat_sci_port scif9_platform_data = {
 197         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 198         .type           = PORT_SCIF,
 199 };
 200
 201 static struct resource scif9_resources[] = {
 202         DEFINE_RES_MEM(0xff92c000, 0x100),
 203         DEFINE_RES_IRQ(evt2irq(0xac0)),
 204 };
 205
 206 static struct platform_device scif9_device = {
 207         .name           = "sh-sci",
 208         .id             = 9,
 209         .resource       = scif9_resources,
 210         .num_resources  = ARRAY_SIZE(scif9_resources),
 211         .dev            = {
 212                 .platform_data  = &scif9_platform_data,
 213         },
 214 };
 215
 216 static struct sh_timer_config tmu0_platform_data = {
 217         .channels_mask = 7,
 218 };
 219
 220 static struct resource tmu0_resources[] = {
 221         DEFINE_RES_MEM(0xffd80000, 0x30),
 222         DEFINE_RES_IRQ(evt2irq(0x400)),
 223         DEFINE_RES_IRQ(evt2irq(0x420)),
 224         DEFINE_RES_IRQ(evt2irq(0x440)),
 225 };
 226
 227 static struct platform_device tmu0_device = {
 228         .name           = "sh-tmu",
 229         .id             = 0,
 230         .dev = {
 231                 .platform_data  = &tmu0_platform_data,
 232         },
 233         .resource       = tmu0_resources,
 234         .num_resources  = ARRAY_SIZE(tmu0_resources),
 235 };
 236
 237 static struct sh_timer_config tmu1_platform_data = {
 238         .channels_mask = 7,
 239 };
 240
 241 static struct resource tmu1_resources[] = {
 242         DEFINE_RES_MEM(0xffd81000, 0x30),
 243         DEFINE_RES_IRQ(evt2irq(0x460)),
 244         DEFINE_RES_IRQ(evt2irq(0x480)),
 245         DEFINE_RES_IRQ(evt2irq(0x4a0)),
 246 };
 247
 248 static struct platform_device tmu1_device = {
 249         .name           = "sh-tmu",
 250         .id             = 1,
 251         .dev = {
 252                 .platform_data  = &tmu1_platform_data,
 253         },
 254         .resource       = tmu1_resources,
 255         .num_resources  = ARRAY_SIZE(tmu1_resources),
 256 };
 257
 258 static struct sh_timer_config tmu2_platform_data = {
 259         .channels_mask = 7,
 260 };
 261
 262 static struct resource tmu2_resources[] = {
 263         DEFINE_RES_MEM(0xffd82000, 0x2c),
 264         DEFINE_RES_IRQ(evt2irq(0x4c0)),
 265         DEFINE_RES_IRQ(evt2irq(0x4e0)),
 266         DEFINE_RES_IRQ(evt2irq(0x500)),
 267 };
 268
 269 static struct platform_device tmu2_device = {
 270         .name           = "sh-tmu",
 271         .id             = 2,
 272         .dev = {
 273                 .platform_data  = &tmu2_platform_data,
 274         },
 275         .resource       = tmu2_resources,
 276         .num_resources  = ARRAY_SIZE(tmu2_resources),
 277 };
 278
 279 static struct platform_device *sh7770_devices[] __initdata = {
 280         &scif0_device,
 281         &scif1_device,
 282         &scif2_device,
 283         &scif3_device,
 284         &scif4_device,
 285         &scif5_device,
 286         &scif6_device,
 287         &scif7_device,
 288         &scif8_device,
 289         &scif9_device,
 290         &tmu0_device,
 291         &tmu1_device,
 292         &tmu2_device,
 293 };
 294
 295 static int __init sh7770_devices_setup(void)
 296 {
 297         return platform_add_devices(sh7770_devices,
 298                                     ARRAY_SIZE(sh7770_devices));
 299 }
 300 arch_initcall(sh7770_devices_setup);
 301
 302 static struct platform_device *sh7770_early_devices[] __initdata = {
 303         &scif0_device,
 304         &scif1_device,
 305         &scif2_device,
 306         &scif3_device,
 307         &scif4_device,
 308         &scif5_device,
 309         &scif6_device,
 310         &scif7_device,
 311         &scif8_device,
 312         &scif9_device,
 313         &tmu0_device,
 314         &tmu1_device,
 315         &tmu2_device,
 316 };
 317
 318 void __init plat_early_device_setup(void)
 319 {
 320         sh_early_platform_add_devices(sh7770_early_devices,
 321                                    ARRAY_SIZE(sh7770_early_devices));
 322 }
 323
 324 enum {
 325         UNUSED = 0,
 326
 327         /* interrupt sources */
 328         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 329         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 330         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 331         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 332
 333         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
 334
 335         GPIO,
 336         TMU0, TMU1, TMU2, TMU2_TICPI,
 337         TMU3, TMU4, TMU5, TMU5_TICPI,
 338         TMU6, TMU7, TMU8,
 339         HAC, IPI, SPDIF, HUDI, I2C,
 340         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 341         I2S0, I2S1, I2S2, I2S3,
 342         SRC_RX, SRC_TX, SRC_SPDIF,
 343         DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
 344         GFX3D_MBX, GFX3D_DMAC,
 345         EXBUS_ATA,
 346         SPI0, SPI1,
 347         SCIF089, SCIF1234, SCIF567,
 348         ADC,
 349         BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 350         BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 351         BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
 352
 353         /* interrupt groups */
 354         TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
 355 };
 356
 357 static struct intc_vect vectors[] __initdata = {
 358         INTC_VECT(GPIO, 0x3e0),
 359         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 360         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
 361         INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
 362         INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
 363         INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
 364         INTC_VECT(TMU8, 0x540),
 365         INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
 366         INTC_VECT(SPDIF, 0x5e0),
 367         INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
 368         INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
 369         INTC_VECT(DMAC0_DMINT2, 0x680),
 370         INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
 371         INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
 372         INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
 373         INTC_VECT(SRC_SPDIF, 0x760),
 374         INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
 375         INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
 376         INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
 377         INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
 378         INTC_VECT(GFX2D, 0x8c0),
 379         INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
 380         INTC_VECT(EXBUS_ATA, 0x940),
 381         INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
 382         INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
 383         INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
 384         INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
 385         INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
 386         INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
 387         INTC_VECT(ADC, 0xb20),
 388         INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
 389         INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
 390         INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
 391         INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
 392         INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
 393         INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
 394         INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
 395         INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
 396         INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
 397         INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
 398         INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
 399         INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
 400         INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
 401         INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
 402         INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
 403         INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
 404 };
 405
 406 static struct intc_group groups[] __initdata = {
 407         INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 408                    TMU5_TICPI, TMU6, TMU7, TMU8),
 409         INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
 410         INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
 411         INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
 412         INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
 413         INTC_GROUP(SPI, SPI0, SPI1),
 414         INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
 415         INTC_GROUP(BBDMAC,
 416                    BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 417                    BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 418                    BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
 419 };
 420
 421 static struct intc_mask_reg mask_registers[] __initdata = {
 422         { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
 423           { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
 424             GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
 425             DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
 426 };
 427
 428 static struct intc_prio_reg prio_registers[] __initdata = {
 429         { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
 430         { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
 431         { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
 432         { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
 433         { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
 434         { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
 435         { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
 436         { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
 437         { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
 438           { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
 439         { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
 440           { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
 441         { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
 442           { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
 443         { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
 444           { TMU1, TMU2, TMU2_TICPI, TMU3 } },
 445         { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
 446           { TMU4, TMU5, TMU5_TICPI, TMU6 } },
 447         { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
 448           { TMU7, TMU8 } },
 449 };
 450
 451 static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
 452                          mask_registers, prio_registers, NULL);
 453
 454 /* Support for external interrupt pins in IRQ mode */
 455 static struct intc_vect irq_vectors[] __initdata = {
 456         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 457         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 458         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 459 };
 460
 461 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 462         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 463           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
 464 };
 465
 466 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 467         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 468                                                IRQ4, IRQ5, } },
 469 };
 470
 471 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 472         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 473                                             IRQ4, IRQ5, } },
 474 };
 475
 476 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
 477                          NULL, irq_mask_registers, irq_prio_registers,
 478                          irq_sense_registers);
 479
 480 /* External interrupt pins in IRL mode */
 481 static struct intc_vect irl_vectors[] __initdata = {
 482         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 483         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 484         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 485         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 486         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 487         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 488         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 489         INTC_VECT(IRL_HHHL, 0x3c0),
 490 };
 491
 492 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 493         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 494           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 495             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 496             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 497             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 498 };
 499
 500 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 501         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 502           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 503             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 504             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 505             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 506             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 507 };
 508
 509 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 510                          NULL, irl7654_mask_registers, NULL, NULL);
 511
 512 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 513                          NULL, irl3210_mask_registers, NULL, NULL);
 514
 515 #define INTC_ICR0       0xffd00000
 516 #define INTC_INTMSK0    0xffd00044
 517 #define INTC_INTMSK1    0xffd00048
 518 #define INTC_INTMSK2    0xffd40080
 519 #define INTC_INTMSKCLR1 0xffd00068
 520 #define INTC_INTMSKCLR2 0xffd40084
 521
 522 void __init plat_irq_setup(void)
 523 {
 524         /* disable IRQ7-0 */
 525         __raw_writel(0xff000000, INTC_INTMSK0);
 526
 527         /* disable IRL3-0 + IRL7-4 */
 528         __raw_writel(0xc0000000, INTC_INTMSK1);
 529         __raw_writel(0xfffefffe, INTC_INTMSK2);
 530
 531         /* select IRL mode for IRL3-0 + IRL7-4 */
 532         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 533
 534         /* disable holding function, ie enable "SH-4 Mode" */
 535         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 536
 537         register_intc_controller(&intc_desc);
 538 }
 539
 540 void __init plat_irq_setup_pins(int mode)
 541 {
 542         switch (mode) {
 543         case IRQ_MODE_IRQ:
 544                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 545                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 546                 register_intc_controller(&intc_irq_desc);
 547                 break;
 548         case IRQ_MODE_IRL7654:
 549                 /* enable IRL7-4 but don't provide any masking */
 550                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 551                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 552                 break;
 553         case IRQ_MODE_IRL3210:
 554                 /* enable IRL0-3 but don't provide any masking */
 555                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 556                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 557                 break;
 558         case IRQ_MODE_IRL7654_MASK:
 559                 /* enable IRL7-4 and mask using cpu intc controller */
 560                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 561                 register_intc_controller(&intc_irl7654_desc);
 562                 break;
 563         case IRQ_MODE_IRL3210_MASK:
 564                 /* enable IRL0-3 and mask using cpu intc controller */
 565                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 566                 register_intc_controller(&intc_irl3210_desc);
 567                 break;
 568         default:
 569                 BUG();
 570         }
 571 }