6 /* Can be used to override the logic in pci_scan_bus for skipping
7 already-configured bus numbers - to be used for buggy BIOSes
8 or architectures with incomplete PCI setup by the loader */
10 #define pcibios_assign_all_busses() 1
13 * A board can define one or more PCI channels that represent built-in (or
14 * external) PCI controllers.
17 struct pci_channel *next;
19 struct pci_ops *pci_ops;
20 struct resource *io_resource;
21 struct resource *mem_resource;
23 unsigned long io_offset;
24 unsigned long mem_offset;
26 unsigned long reg_base;
28 unsigned long io_map_base;
31 extern void register_pci_controller(struct pci_channel *hose);
33 extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
38 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
39 enum pci_mmap_state mmap_state, int write_combine);
40 extern void pcibios_set_master(struct pci_dev *dev);
42 static inline void pcibios_penalize_isa_irq(int irq, int active)
44 /* We don't do dynamic PCI IRQ allocation */
47 /* Dynamic DMA mapping stuff.
48 * SuperH has everything mapped statically like x86.
51 /* The PCI address space does equal the physical memory
52 * address space. The networking and block device layers use
53 * this boolean for bounce buffer decisions.
55 #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
57 /* pci_unmap_{single,page} being a nop depends upon the
60 #ifdef CONFIG_DMA_NONCOHERENT
61 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME;
62 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME;
63 #define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
64 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
65 #define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
66 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
68 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
69 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
70 #define pci_unmap_addr(PTR, ADDR_NAME) (0)
71 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
72 #define pci_unmap_len(PTR, LEN_NAME) (0)
73 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
78 * None of the SH PCI controllers support MWI, it is always treated as a
79 * direct memory write.
81 #define PCI_DISABLE_MWI
83 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
84 enum pci_dma_burst_strategy *strat,
85 unsigned long *strategy_parameter)
87 unsigned long cacheline_size;
90 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
93 cacheline_size = L1_CACHE_BYTES;
95 cacheline_size = byte << 2;
97 *strat = PCI_DMA_BURST_MULTIPLE;
98 *strategy_parameter = cacheline_size;
102 #ifdef CONFIG_SUPERH32
104 * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
105 * at the end of the address space in a special non-translatable area.
107 #define PCI_MEM_FIXED_START 0xfd000000
108 #define PCI_MEM_FIXED_END (PCI_MEM_FIXED_START + 0x01000000)
110 #define is_pci_memory_fixed_range(s, e) \
111 ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
113 #define is_pci_memory_fixed_range(s, e) (0)
116 /* Board-specific fixup routines. */
117 int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
119 extern void pcibios_resource_to_bus(struct pci_dev *dev,
120 struct pci_bus_region *region, struct resource *res);
122 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
123 struct pci_bus_region *region);
125 /* Chances are this interrupt is wired PC-style ... */
126 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
128 return channel ? 15 : 14;
131 /* generic DMA-mapping stuff */
132 #include <asm-generic/pci-dma-compat.h>
134 #endif /* __KERNEL__ */
135 #endif /* __ASM_SH_PCI_H */