d42b14cc72a4516efa4c976a8e84ad47b97cbaa2
[sfrench/cifs-2.6.git] / arch / s390 / kernel / irq.c
1 /*
2  *    Copyright IBM Corp. 2004, 2011
3  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
4  *               Holger Smolinski <Holger.Smolinski@de.ibm.com>,
5  *               Thomas Spatzier <tspat@de.ibm.com>,
6  *
7  * This file contains interrupt related functions.
8  */
9
10 #include <linux/kernel_stat.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/proc_fs.h>
14 #include <linux/profile.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/ftrace.h>
18 #include <linux/errno.h>
19 #include <linux/slab.h>
20 #include <linux/cpu.h>
21 #include <linux/irq.h>
22 #include <asm/irq_regs.h>
23 #include <asm/cputime.h>
24 #include <asm/lowcore.h>
25 #include <asm/irq.h>
26 #include <asm/hw_irq.h>
27 #include "entry.h"
28
29 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
30 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
31
32 struct irq_class {
33         char *name;
34         char *desc;
35 };
36
37 /*
38  * The list of "main" irq classes on s390. This is the list of interrupts
39  * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
40  * Historically only external and I/O interrupts have been part of /proc/stat.
41  * We can't add the split external and I/O sub classes since the first field
42  * in the "intr" line in /proc/stat is supposed to be the sum of all other
43  * fields.
44  * Since the external and I/O interrupt fields are already sums we would end
45  * up with having a sum which accounts each interrupt twice.
46  */
47 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
48         [EXT_INTERRUPT]  = {.name = "EXT"},
49         [IO_INTERRUPT]   = {.name = "I/O"},
50         [THIN_INTERRUPT] = {.name = "AIO"},
51 };
52
53 /*
54  * The list of split external and I/O interrupts that appear only in
55  * /proc/interrupts.
56  * In addition this list contains non external / I/O events like NMIs.
57  */
58 static const struct irq_class irqclass_sub_desc[NR_ARCH_IRQS] = {
59         [IRQEXT_CLK] = {.name = "CLK", .desc = "[EXT] Clock Comparator"},
60         [IRQEXT_EXC] = {.name = "EXC", .desc = "[EXT] External Call"},
61         [IRQEXT_EMS] = {.name = "EMS", .desc = "[EXT] Emergency Signal"},
62         [IRQEXT_TMR] = {.name = "TMR", .desc = "[EXT] CPU Timer"},
63         [IRQEXT_TLA] = {.name = "TAL", .desc = "[EXT] Timing Alert"},
64         [IRQEXT_PFL] = {.name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
65         [IRQEXT_DSD] = {.name = "DSD", .desc = "[EXT] DASD Diag"},
66         [IRQEXT_VRT] = {.name = "VRT", .desc = "[EXT] Virtio"},
67         [IRQEXT_SCP] = {.name = "SCP", .desc = "[EXT] Service Call"},
68         [IRQEXT_IUC] = {.name = "IUC", .desc = "[EXT] IUCV"},
69         [IRQEXT_CMS] = {.name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
70         [IRQEXT_CMC] = {.name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
71         [IRQEXT_CMR] = {.name = "CMR", .desc = "[EXT] CPU-Measurement: RI"},
72         [IRQIO_CIO]  = {.name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
73         [IRQIO_QAI]  = {.name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"},
74         [IRQIO_DAS]  = {.name = "DAS", .desc = "[I/O] DASD"},
75         [IRQIO_C15]  = {.name = "C15", .desc = "[I/O] 3215"},
76         [IRQIO_C70]  = {.name = "C70", .desc = "[I/O] 3270"},
77         [IRQIO_TAP]  = {.name = "TAP", .desc = "[I/O] Tape"},
78         [IRQIO_VMR]  = {.name = "VMR", .desc = "[I/O] Unit Record Devices"},
79         [IRQIO_LCS]  = {.name = "LCS", .desc = "[I/O] LCS"},
80         [IRQIO_CLW]  = {.name = "CLW", .desc = "[I/O] CLAW"},
81         [IRQIO_CTC]  = {.name = "CTC", .desc = "[I/O] CTC"},
82         [IRQIO_APB]  = {.name = "APB", .desc = "[I/O] AP Bus"},
83         [IRQIO_ADM]  = {.name = "ADM", .desc = "[I/O] EADM Subchannel"},
84         [IRQIO_CSC]  = {.name = "CSC", .desc = "[I/O] CHSC Subchannel"},
85         [IRQIO_PCI]  = {.name = "PCI", .desc = "[I/O] PCI Interrupt" },
86         [IRQIO_MSI]  = {.name = "MSI", .desc = "[I/O] MSI Interrupt" },
87         [IRQIO_VIR]  = {.name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
88         [IRQIO_VAI]  = {.name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"},
89         [NMI_NMI]    = {.name = "NMI", .desc = "[NMI] Machine Check"},
90         [CPU_RST]    = {.name = "RST", .desc = "[CPU] CPU Restart"},
91 };
92
93 void __init init_IRQ(void)
94 {
95         irq_reserve_irqs(0, THIN_INTERRUPT);
96         init_cio_interrupts();
97         init_airq_interrupts();
98         init_ext_interrupts();
99 }
100
101 void do_IRQ(struct pt_regs *regs, int irq)
102 {
103         struct pt_regs *old_regs;
104
105         old_regs = set_irq_regs(regs);
106         irq_enter();
107         if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
108                 /* Serve timer interrupts first. */
109                 clock_comparator_work();
110         generic_handle_irq(irq);
111         irq_exit();
112         set_irq_regs(old_regs);
113 }
114
115 /*
116  * show_interrupts is needed by /proc/interrupts.
117  */
118 int show_interrupts(struct seq_file *p, void *v)
119 {
120         int irq = *(loff_t *) v;
121         int cpu;
122
123         get_online_cpus();
124         if (irq == 0) {
125                 seq_puts(p, "           ");
126                 for_each_online_cpu(cpu)
127                         seq_printf(p, "CPU%d       ", cpu);
128                 seq_putc(p, '\n');
129                 goto out;
130         }
131         if (irq < NR_IRQS) {
132                 if (irq >= NR_IRQS_BASE)
133                         goto out;
134                 seq_printf(p, "%s: ", irqclass_main_desc[irq].name);
135                 for_each_online_cpu(cpu)
136                         seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
137                 seq_putc(p, '\n');
138                 goto out;
139         }
140         for (irq = 0; irq < NR_ARCH_IRQS; irq++) {
141                 seq_printf(p, "%s: ", irqclass_sub_desc[irq].name);
142                 for_each_online_cpu(cpu)
143                         seq_printf(p, "%10u ",
144                                    per_cpu(irq_stat, cpu).irqs[irq]);
145                 if (irqclass_sub_desc[irq].desc)
146                         seq_printf(p, "  %s", irqclass_sub_desc[irq].desc);
147                 seq_putc(p, '\n');
148         }
149 out:
150         put_online_cpus();
151         return 0;
152 }
153
154 int arch_show_interrupts(struct seq_file *p, int prec)
155 {
156         return 0;
157 }
158
159 /*
160  * Switch to the asynchronous interrupt stack for softirq execution.
161  */
162 void do_softirq_own_stack(void)
163 {
164         unsigned long old, new;
165
166         /* Get current stack pointer. */
167         asm volatile("la %0,0(15)" : "=a" (old));
168         /* Check against async. stack address range. */
169         new = S390_lowcore.async_stack;
170         if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) {
171                 /* Need to switch to the async. stack. */
172                 new -= STACK_FRAME_OVERHEAD;
173                 ((struct stack_frame *) new)->back_chain = old;
174                 asm volatile("   la    15,0(%0)\n"
175                              "   basr  14,%2\n"
176                              "   la    15,0(%1)\n"
177                              : : "a" (new), "a" (old),
178                                  "a" (__do_softirq)
179                              : "0", "1", "2", "3", "4", "5", "14",
180                                "cc", "memory" );
181         } else {
182                 /* We are already on the async stack. */
183                 __do_softirq();
184         }
185 }
186
187 /*
188  * ext_int_hash[index] is the list head for all external interrupts that hash
189  * to this index.
190  */
191 static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
192
193 struct ext_int_info {
194         ext_int_handler_t handler;
195         struct hlist_node entry;
196         struct rcu_head rcu;
197         u16 code;
198 };
199
200 /* ext_int_hash_lock protects the handler lists for external interrupts */
201 static DEFINE_SPINLOCK(ext_int_hash_lock);
202
203 static inline int ext_hash(u16 code)
204 {
205         BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
206
207         return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
208 }
209
210 int register_external_interrupt(u16 code, ext_int_handler_t handler)
211 {
212         struct ext_int_info *p;
213         unsigned long flags;
214         int index;
215
216         p = kmalloc(sizeof(*p), GFP_ATOMIC);
217         if (!p)
218                 return -ENOMEM;
219         p->code = code;
220         p->handler = handler;
221         index = ext_hash(code);
222
223         spin_lock_irqsave(&ext_int_hash_lock, flags);
224         hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
225         spin_unlock_irqrestore(&ext_int_hash_lock, flags);
226         return 0;
227 }
228 EXPORT_SYMBOL(register_external_interrupt);
229
230 int unregister_external_interrupt(u16 code, ext_int_handler_t handler)
231 {
232         struct ext_int_info *p;
233         unsigned long flags;
234         int index = ext_hash(code);
235
236         spin_lock_irqsave(&ext_int_hash_lock, flags);
237         hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
238                 if (p->code == code && p->handler == handler) {
239                         hlist_del_rcu(&p->entry);
240                         kfree_rcu(p, rcu);
241                 }
242         }
243         spin_unlock_irqrestore(&ext_int_hash_lock, flags);
244         return 0;
245 }
246 EXPORT_SYMBOL(unregister_external_interrupt);
247
248 static irqreturn_t do_ext_interrupt(int irq, void *dummy)
249 {
250         struct pt_regs *regs = get_irq_regs();
251         struct ext_code ext_code;
252         struct ext_int_info *p;
253         int index;
254
255         ext_code = *(struct ext_code *) &regs->int_code;
256         if (ext_code.code != 0x1004)
257                 __get_cpu_var(s390_idle).nohz_delay = 1;
258
259         index = ext_hash(ext_code.code);
260         rcu_read_lock();
261         hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
262                 if (unlikely(p->code != ext_code.code))
263                         continue;
264                 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
265         }
266         rcu_read_unlock();
267         return IRQ_HANDLED;
268 }
269
270 static struct irqaction external_interrupt = {
271         .name    = "EXT",
272         .handler = do_ext_interrupt,
273 };
274
275 void __init init_ext_interrupts(void)
276 {
277         int idx;
278
279         for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
280                 INIT_HLIST_HEAD(&ext_int_hash[idx]);
281
282         irq_set_chip_and_handler(EXT_INTERRUPT,
283                                  &dummy_irq_chip, handle_percpu_irq);
284         setup_irq(EXT_INTERRUPT, &external_interrupt);
285 }
286
287 static DEFINE_SPINLOCK(irq_subclass_lock);
288 static unsigned char irq_subclass_refcount[64];
289
290 void irq_subclass_register(enum irq_subclass subclass)
291 {
292         spin_lock(&irq_subclass_lock);
293         if (!irq_subclass_refcount[subclass])
294                 ctl_set_bit(0, subclass);
295         irq_subclass_refcount[subclass]++;
296         spin_unlock(&irq_subclass_lock);
297 }
298 EXPORT_SYMBOL(irq_subclass_register);
299
300 void irq_subclass_unregister(enum irq_subclass subclass)
301 {
302         spin_lock(&irq_subclass_lock);
303         irq_subclass_refcount[subclass]--;
304         if (!irq_subclass_refcount[subclass])
305                 ctl_clear_bit(0, subclass);
306         spin_unlock(&irq_subclass_lock);
307 }
308 EXPORT_SYMBOL(irq_subclass_unregister);