arch/ppc/platforms/lopec.c

   1 /*
   2  * Setup routines for the Motorola LoPEC.
   3  *
   4  * Author: Dan Cox
   5  * Maintainer: Tom Rini <trini@kernel.crashing.org>
   6  *
   7  * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12
  13 #include <linux/config.h>
  14 #include <linux/types.h>
  15 #include <linux/delay.h>
  16 #include <linux/pci_ids.h>
  17 #include <linux/ioport.h>
  18 #include <linux/init.h>
  19 #include <linux/ide.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/initrd.h>
  22 #include <linux/console.h>
  23 #include <linux/root_dev.h>
  24 #include <linux/pci.h>
  25
  26 #include <asm/machdep.h>
  27 #include <asm/pci-bridge.h>
  28 #include <asm/io.h>
  29 #include <asm/open_pic.h>
  30 #include <asm/i8259.h>
  31 #include <asm/todc.h>
  32 #include <asm/bootinfo.h>
  33 #include <asm/mpc10x.h>
  34 #include <asm/hw_irq.h>
  35 #include <asm/prep_nvram.h>
  36 #include <asm/kgdb.h>
  37
  38 /*
  39  * Define all of the IRQ senses and polarities.  Taken from the
  40  * LoPEC Programmer's Reference Guide.
  41  */
  42 static u_char lopec_openpic_initsenses[16] __initdata = {
  43         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 0 */
  44         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 1 */
  45         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 2 */
  46         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 3 */
  47         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 4 */
  48         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 5 */
  49         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 6 */
  50         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 7 */
  51         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 8 */
  52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 9 */
  53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 10 */
  54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 11 */
  55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 12 */
  56         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 13 */
  57         (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),       /* IRQ 14 */
  58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE)       /* IRQ 15 */
  59 };
  60
  61 static inline int __init
  62 lopec_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  63 {
  64         int irq;
  65         static char pci_irq_table[][4] = {
  66                 {16, 0, 0, 0}, /* ID 11 - Winbond */
  67                 {22, 0, 0, 0}, /* ID 12 - SCSI */
  68                 {0, 0, 0, 0}, /* ID 13 - nothing */
  69                 {17, 0, 0, 0}, /* ID 14 - 82559 Ethernet */
  70                 {27, 0, 0, 0}, /* ID 15 - USB */
  71                 {23, 0, 0, 0}, /* ID 16 - PMC slot 1 */
  72                 {24, 0, 0, 0}, /* ID 17 - PMC slot 2 */
  73                 {25, 0, 0, 0}, /* ID 18 - PCI slot */
  74                 {0, 0, 0, 0}, /* ID 19 - nothing */
  75                 {0, 0, 0, 0}, /* ID 20 - nothing */
  76                 {0, 0, 0, 0}, /* ID 21 - nothing */
  77                 {0, 0, 0, 0}, /* ID 22 - nothing */
  78                 {0, 0, 0, 0}, /* ID 23 - nothing */
  79                 {0, 0, 0, 0}, /* ID 24 - PMC slot 1b */
  80                 {0, 0, 0, 0}, /* ID 25 - nothing */
  81                 {0, 0, 0, 0}  /* ID 26 - PMC Slot 2b */
  82         };
  83         const long min_idsel = 11, max_idsel = 26, irqs_per_slot = 4;
  84
  85         irq = PCI_IRQ_TABLE_LOOKUP;
  86         if (!irq)
  87                 return 0;
  88
  89         return irq;
  90 }
  91
  92 static void __init
  93 lopec_setup_winbond_83553(struct pci_controller *hose)
  94 {
  95         int devfn;
  96
  97         devfn = PCI_DEVFN(11,0);
  98
  99         /* IDE interrupt routing (primary 14, secondary 15) */
 100         early_write_config_byte(hose, 0, devfn, 0x43, 0xef);
 101         /* PCI interrupt routing */
 102         early_write_config_word(hose, 0, devfn, 0x44, 0x0000);
 103
 104         /* ISA-PCI address decoder */
 105         early_write_config_byte(hose, 0, devfn, 0x48, 0xf0);
 106
 107         /* RTC, kb, not used in PPC */
 108         early_write_config_byte(hose, 0, devfn, 0x4d, 0x00);
 109         early_write_config_byte(hose, 0, devfn, 0x4e, 0x04);
 110         devfn = PCI_DEVFN(11, 1);
 111         early_write_config_byte(hose, 0, devfn, 0x09, 0x8f);
 112         early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
 113 }
 114
 115 static void __init
 116 lopec_find_bridges(void)
 117 {
 118         struct pci_controller *hose;
 119
 120         hose = pcibios_alloc_controller();
 121         if (!hose)
 122                 return;
 123
 124         hose->first_busno = 0;
 125         hose->last_busno = 0xff;
 126
 127         if (mpc10x_bridge_init(hose, MPC10X_MEM_MAP_B, MPC10X_MEM_MAP_B,
 128                                 MPC10X_MAPB_EUMB_BASE) == 0) {
 129
 130                 hose->mem_resources[0].end = 0xffffffff;
 131                 lopec_setup_winbond_83553(hose);
 132                 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 133                 ppc_md.pci_swizzle = common_swizzle;
 134                 ppc_md.pci_map_irq = lopec_map_irq;
 135         }
 136 }
 137
 138 static int
 139 lopec_show_cpuinfo(struct seq_file *m)
 140 {
 141         seq_printf(m, "machine\t\t: Motorola LoPEC\n");
 142         return 0;
 143 }
 144
 145 static void
 146 lopec_restart(char *cmd)
 147 {
 148 #define LOPEC_SYSSTAT1 0xffe00000
 149         /* force a hard reset, if possible */
 150         unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1);
 151         reg |= 0x80;
 152         *((unsigned char *) LOPEC_SYSSTAT1) = reg;
 153
 154         local_irq_disable();
 155         while(1);
 156 #undef LOPEC_SYSSTAT1
 157 }
 158
 159 static void
 160 lopec_halt(void)
 161 {
 162         local_irq_disable();
 163         while(1);
 164 }
 165
 166 static void
 167 lopec_power_off(void)
 168 {
 169         lopec_halt();
 170 }
 171
 172 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 173 int lopec_ide_ports_known = 0;
 174 static unsigned long lopec_ide_regbase[MAX_HWIFS];
 175 static unsigned long lopec_ide_ctl_regbase[MAX_HWIFS];
 176 static unsigned long lopec_idedma_regbase;
 177
 178 static void
 179 lopec_ide_probe(void)
 180 {
 181         struct pci_dev *dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
 182                                               PCI_DEVICE_ID_WINBOND_82C105,
 183                                               NULL);
 184         lopec_ide_ports_known = 1;
 185
 186         if (dev) {
 187                 lopec_ide_regbase[0] = dev->resource[0].start;
 188                 lopec_ide_regbase[1] = dev->resource[2].start;
 189                 lopec_ide_ctl_regbase[0] = dev->resource[1].start;
 190                 lopec_ide_ctl_regbase[1] = dev->resource[3].start;
 191                 lopec_idedma_regbase = dev->resource[4].start;
 192                 pci_dev_put(dev);
 193         }
 194 }
 195
 196 static int
 197 lopec_ide_default_irq(unsigned long base)
 198 {
 199         if (lopec_ide_ports_known == 0)
 200                 lopec_ide_probe();
 201
 202         if (base == lopec_ide_regbase[0])
 203                 return 14;
 204         else if (base == lopec_ide_regbase[1])
 205                 return 15;
 206         else
 207                 return 0;
 208 }
 209
 210 static unsigned long
 211 lopec_ide_default_io_base(int index)
 212 {
 213         if (lopec_ide_ports_known == 0)
 214                 lopec_ide_probe();
 215         return lopec_ide_regbase[index];
 216 }
 217
 218 static void __init
 219 lopec_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data,
 220                           unsigned long ctl, int *irq)
 221 {
 222         unsigned long reg = data;
 223         uint alt_status_base;
 224         int i;
 225
 226         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
 227                 hw->io_ports[i] = reg++;
 228
 229         if (data == lopec_ide_regbase[0]) {
 230                 alt_status_base = lopec_ide_ctl_regbase[0] + 2;
 231                 hw->irq = 14;
 232         } else if (data == lopec_ide_regbase[1]) {
 233                 alt_status_base = lopec_ide_ctl_regbase[1] + 2;
 234                 hw->irq = 15;
 235         } else {
 236                 alt_status_base = 0;
 237                 hw->irq = 0;
 238         }
 239
 240         if (ctl)
 241                 hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
 242         else
 243                 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
 244
 245         if (irq != NULL)
 246                 *irq = hw->irq;
 247
 248 }
 249 #endif /* BLK_DEV_IDE */
 250
 251 static void __init
 252 lopec_init_IRQ(void)
 253 {
 254         int i;
 255
 256         /*
 257          * Provide the open_pic code with the correct table of interrupts.
 258          */
 259         OpenPIC_InitSenses = lopec_openpic_initsenses;
 260         OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
 261
 262         mpc10x_set_openpic();
 263
 264         /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
 265         openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
 266                         &i8259_irq);
 267
 268         /*
 269          * The EPIC allows for a read in the range of 0xFEF00000 ->
 270          * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
 271          */
 272         i8259_init(0xfef00000, 0);
 273 }
 274
 275 static int __init
 276 lopec_request_io(void)
 277 {
 278         outb(0x00, 0x4d0);
 279         outb(0xc0, 0x4d1);
 280
 281         request_region(0x00, 0x20, "dma1");
 282         request_region(0x20, 0x20, "pic1");
 283         request_region(0x40, 0x20, "timer");
 284         request_region(0x80, 0x10, "dma page reg");
 285         request_region(0xa0, 0x20, "pic2");
 286         request_region(0xc0, 0x20, "dma2");
 287
 288         return 0;
 289 }
 290
 291 device_initcall(lopec_request_io);
 292
 293 static void __init
 294 lopec_map_io(void)
 295 {
 296         io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
 297         io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
 298 }
 299
 300 /*
 301  * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
 302  */
 303 static __inline__ void
 304 lopec_set_bat(void)
 305 {
 306         mb();
 307         mtspr(SPRN_DBAT1U, 0xf8000ffe);
 308         mtspr(SPRN_DBAT1L, 0xf800002a);
 309         mb();
 310 }
 311
 312 TODC_ALLOC();
 313
 314 static void __init
 315 lopec_setup_arch(void)
 316 {
 317
 318         TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
 319                   ioremap(0xffe80000, 0x8000), 8);
 320
 321         loops_per_jiffy = 100000000/HZ;
 322
 323         lopec_find_bridges();
 324
 325 #ifdef CONFIG_BLK_DEV_INITRD
 326         if (initrd_start)
 327                 ROOT_DEV = Root_RAM0;
 328         else
 329 #elif defined(CONFIG_ROOT_NFS)
 330                 ROOT_DEV = Root_NFS;
 331 #elif defined(CONFIG_BLK_DEV_IDEDISK)
 332                 ROOT_DEV = Root_HDA1;
 333 #else
 334                 ROOT_DEV = Root_SDA1;
 335 #endif
 336
 337 #ifdef CONFIG_PPCBUG_NVRAM
 338         /* Read in NVRAM data */
 339         init_prep_nvram();
 340
 341         /* if no bootargs, look in NVRAM */
 342         if ( cmd_line[0] == '\0' ) {
 343                 char *bootargs;
 344                  bootargs = prep_nvram_get_var("bootargs");
 345                  if (bootargs != NULL) {
 346                          strcpy(cmd_line, bootargs);
 347                          /* again.. */
 348                          strcpy(saved_command_line, cmd_line);
 349                 }
 350         }
 351 #endif
 352 }
 353
 354 void __init
 355 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 356               unsigned long r6, unsigned long r7)
 357 {
 358         parse_bootinfo(find_bootinfo());
 359         lopec_set_bat();
 360
 361         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
 362         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
 363         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
 364         ISA_DMA_THRESHOLD = 0x00ffffff;
 365         DMA_MODE_READ = 0x44;
 366         DMA_MODE_WRITE = 0x48;
 367         ppc_do_canonicalize_irqs = 1;
 368
 369         ppc_md.setup_arch = lopec_setup_arch;
 370         ppc_md.show_cpuinfo = lopec_show_cpuinfo;
 371         ppc_md.init_IRQ = lopec_init_IRQ;
 372         ppc_md.get_irq = openpic_get_irq;
 373
 374         ppc_md.restart = lopec_restart;
 375         ppc_md.power_off = lopec_power_off;
 376         ppc_md.halt = lopec_halt;
 377
 378         ppc_md.setup_io_mappings = lopec_map_io;
 379
 380         ppc_md.time_init = todc_time_init;
 381         ppc_md.set_rtc_time = todc_set_rtc_time;
 382         ppc_md.get_rtc_time = todc_get_rtc_time;
 383         ppc_md.calibrate_decr = todc_calibrate_decr;
 384
 385         ppc_md.nvram_read_val = todc_direct_read_val;
 386         ppc_md.nvram_write_val = todc_direct_write_val;
 387
 388 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 389         ppc_ide_md.default_irq = lopec_ide_default_irq;
 390         ppc_ide_md.default_io_base = lopec_ide_default_io_base;
 391         ppc_ide_md.ide_init_hwif = lopec_ide_init_hwif_ports;
 392 #endif
 393 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 394         ppc_md.progress = gen550_progress;
 395 #endif
 396 }