arch/ppc/platforms/hdpu.c

   1 /*
   2  * Board setup routines for the Sky Computers HDPU Compute Blade.
   3  *
   4  * Written by Brian Waite <waite@skycomputers.com>
   5  *
   6  * Based on code done by - Mark A. Greer <mgreer@mvista.com>
   7  *                         Rabeeh Khoury - rabeeh@galileo.co.il
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16
  17 #include <linux/pci.h>
  18 #include <linux/delay.h>
  19 #include <linux/irq.h>
  20 #include <linux/ide.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <linux/initrd.h>
  25 #include <linux/root_dev.h>
  26 #include <linux/smp.h>
  27
  28 #include <asm/time.h>
  29 #include <asm/machdep.h>
  30 #include <asm/todc.h>
  31 #include <asm/mv64x60.h>
  32 #include <asm/ppcboot.h>
  33 #include <platforms/hdpu.h>
  34 #include <linux/mv643xx.h>
  35 #include <linux/hdpu_features.h>
  36 #include <linux/device.h>
  37 #include <linux/mtd/physmap.h>
  38
  39 #define BOARD_VENDOR    "Sky Computers"
  40 #define BOARD_MACHINE   "HDPU-CB-A"
  41
  42 bd_t ppcboot_bd;
  43 int ppcboot_bd_valid = 0;
  44
  45 static mv64x60_handle_t bh;
  46
  47 extern char cmd_line[];
  48
  49 unsigned long hdpu_find_end_of_memory(void);
  50 void hdpu_mpsc_progress(char *s, unsigned short hex);
  51 void hdpu_heartbeat(void);
  52
  53 static void parse_bootinfo(unsigned long r3,
  54                            unsigned long r4, unsigned long r5,
  55                            unsigned long r6, unsigned long r7);
  56 static void hdpu_set_l1pe(void);
  57 static void hdpu_cpustate_set(unsigned char new_state);
  58 #ifdef CONFIG_SMP
  59 static DEFINE_SPINLOCK(timebase_lock);
  60 static unsigned int timebase_upper = 0, timebase_lower = 0;
  61 extern int smp_tb_synchronized;
  62
  63 void __devinit hdpu_tben_give(void);
  64 void __devinit hdpu_tben_take(void);
  65 #endif
  66
  67 static int __init
  68 hdpu_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  69 {
  70         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
  71
  72         if (hose->index == 0) {
  73                 static char pci_irq_table[][4] = {
  74                         {HDPU_PCI_0_IRQ, 0, 0, 0},
  75                         {HDPU_PCI_0_IRQ, 0, 0, 0},
  76                 };
  77
  78                 const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
  79                 return PCI_IRQ_TABLE_LOOKUP;
  80         } else {
  81                 static char pci_irq_table[][4] = {
  82                         {HDPU_PCI_1_IRQ, 0, 0, 0},
  83                 };
  84
  85                 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
  86                 return PCI_IRQ_TABLE_LOOKUP;
  87         }
  88 }
  89
  90 static void __init hdpu_intr_setup(void)
  91 {
  92         mv64x60_write(&bh, MV64x60_GPP_IO_CNTL,
  93                       (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
  94                        (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) |
  95                        (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) |
  96                        (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) |
  97                        (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29)));
  98
  99         /* XXXX Erranum FEr PCI-#8 */
 100         mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1 << 5) | (1 << 9));
 101         mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1 << 5) | (1 << 9));
 102
 103         /*
 104          * Dismiss and then enable interrupt on GPP interrupt cause
 105          * for CPU #0
 106          */
 107         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~((1 << 8) | (1 << 13)));
 108         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1 << 8) | (1 << 13));
 109
 110         /*
 111          * Dismiss and then enable interrupt on CPU #0 high cause reg
 112          * BIT25 summarizes GPP interrupts 8-15
 113          */
 114         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1 << 25));
 115 }
 116
 117 static void __init hdpu_setup_peripherals(void)
 118 {
 119         unsigned int val;
 120
 121         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 122                                  HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
 123         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 124
 125         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
 126                                  HDPU_TBEN_BASE, HDPU_TBEN_SIZE, 0);
 127         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 128
 129         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 130                                  HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE, 0);
 131         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 132
 133         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 134                                  HDPU_INTERNAL_SRAM_BASE,
 135                                  HDPU_INTERNAL_SRAM_SIZE, 0);
 136         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 137
 138         bh.ci->disable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
 139         mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, 0, 0, 0);
 140
 141         mv64x60_clr_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, (1 << 3));
 142         mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
 143         mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
 144                          ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
 145
 146         /* Enable pipelining */
 147         mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13));
 148         /* Enable Snoop Pipelineing */
 149         mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24));
 150
 151         /*
 152          * Change DRAM read buffer assignment.
 153          * Assign read buffer 0 dedicated only for CPU,
 154          * and the rest read buffer 1.
 155          */
 156         val = mv64x60_read(&bh, MV64360_SDRAM_CONFIG);
 157         val = val & 0x03ffffff;
 158         val = val | 0xf8000000;
 159         mv64x60_write(&bh, MV64360_SDRAM_CONFIG, val);
 160
 161         /*
 162          * Configure internal SRAM -
 163          * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set
 164          * Parity enabled.
 165          * Parity error propagation
 166          * Arbitration not parked for CPU only
 167          * Other bits are reserved.
 168          */
 169 #ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
 170         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 171 #else
 172         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
 173 #endif
 174
 175         hdpu_intr_setup();
 176 }
 177
 178 static void __init hdpu_setup_bridge(void)
 179 {
 180         struct mv64x60_setup_info si;
 181         int i;
 182
 183         memset(&si, 0, sizeof(si));
 184
 185         si.phys_reg_base = HDPU_BRIDGE_REG_BASE;
 186         si.pci_0.enable_bus = 1;
 187         si.pci_0.pci_io.cpu_base = HDPU_PCI0_IO_START_PROC_ADDR;
 188         si.pci_0.pci_io.pci_base_hi = 0;
 189         si.pci_0.pci_io.pci_base_lo = HDPU_PCI0_IO_START_PCI_ADDR;
 190         si.pci_0.pci_io.size = HDPU_PCI0_IO_SIZE;
 191         si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
 192         si.pci_0.pci_mem[0].cpu_base = HDPU_PCI0_MEM_START_PROC_ADDR;
 193         si.pci_0.pci_mem[0].pci_base_hi = HDPU_PCI0_MEM_START_PCI_HI_ADDR;
 194         si.pci_0.pci_mem[0].pci_base_lo = HDPU_PCI0_MEM_START_PCI_LO_ADDR;
 195         si.pci_0.pci_mem[0].size = HDPU_PCI0_MEM_SIZE;
 196         si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
 197         si.pci_0.pci_cmd_bits = 0;
 198         si.pci_0.latency_timer = 0x80;
 199
 200         si.pci_1.enable_bus = 1;
 201         si.pci_1.pci_io.cpu_base = HDPU_PCI1_IO_START_PROC_ADDR;
 202         si.pci_1.pci_io.pci_base_hi = 0;
 203         si.pci_1.pci_io.pci_base_lo = HDPU_PCI1_IO_START_PCI_ADDR;
 204         si.pci_1.pci_io.size = HDPU_PCI1_IO_SIZE;
 205         si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
 206         si.pci_1.pci_mem[0].cpu_base = HDPU_PCI1_MEM_START_PROC_ADDR;
 207         si.pci_1.pci_mem[0].pci_base_hi = HDPU_PCI1_MEM_START_PCI_HI_ADDR;
 208         si.pci_1.pci_mem[0].pci_base_lo = HDPU_PCI1_MEM_START_PCI_LO_ADDR;
 209         si.pci_1.pci_mem[0].size = HDPU_PCI1_MEM_SIZE;
 210         si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
 211         si.pci_1.pci_cmd_bits = 0;
 212         si.pci_1.latency_timer = 0x80;
 213
 214         for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
 215 #if defined(CONFIG_NOT_COHERENT_CACHE)
 216                 si.cpu_prot_options[i] = 0;
 217                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
 218                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
 219                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
 220
 221                 si.pci_1.acc_cntl_options[i] =
 222                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 223                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 224                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 225                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 226
 227                 si.pci_0.acc_cntl_options[i] =
 228                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 229                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 230                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 231                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 232
 233 #else
 234                 si.cpu_prot_options[i] = 0;
 235                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; /* errata */
 236                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; /* errata */
 237                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; /* errata */
 238
 239                 si.pci_0.acc_cntl_options[i] =
 240                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 241                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 242                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 243                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 244
 245                 si.pci_1.acc_cntl_options[i] =
 246                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 247                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 248                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 249                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 250 #endif
 251         }
 252
 253         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI);
 254
 255         /* Lookup PCI host bridges */
 256         mv64x60_init(&bh, &si);
 257         pci_dram_offset = 0;    /* System mem at same addr on PCI & cpu bus */
 258         ppc_md.pci_swizzle = common_swizzle;
 259         ppc_md.pci_map_irq = hdpu_map_irq;
 260
 261         mv64x60_set_bus(&bh, 0, 0);
 262         bh.hose_a->first_busno = 0;
 263         bh.hose_a->last_busno = 0xff;
 264         bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
 265
 266         bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
 267         mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
 268         bh.hose_b->last_busno = 0xff;
 269         bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
 270                 bh.hose_b->first_busno);
 271
 272         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 273
 274         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
 275         /*
 276          * Enabling of PCI internal-vs-external arbitration
 277          * is a platform- and errata-dependent decision.
 278          */
 279         return;
 280 }
 281
 282 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
 283 static void __init hdpu_early_serial_map(void)
 284 {
 285 #ifdef  CONFIG_KGDB
 286         static char first_time = 1;
 287
 288 #if defined(CONFIG_KGDB_TTYS0)
 289 #define KGDB_PORT 0
 290 #elif defined(CONFIG_KGDB_TTYS1)
 291 #define KGDB_PORT 1
 292 #else
 293 #error "Invalid kgdb_tty port"
 294 #endif
 295
 296         if (first_time) {
 297                 gt_early_mpsc_init(KGDB_PORT,
 298                                    B9600 | CS8 | CREAD | HUPCL | CLOCAL);
 299                 first_time = 0;
 300         }
 301
 302         return;
 303 #endif
 304 }
 305 #endif
 306
 307 static void hdpu_init2(void)
 308 {
 309         return;
 310 }
 311
 312 #if defined(CONFIG_MV643XX_ETH)
 313 static void __init hdpu_fixup_eth_pdata(struct platform_device *pd)
 314 {
 315
 316         struct mv643xx_eth_platform_data *eth_pd;
 317         eth_pd = pd->dev.platform_data;
 318
 319         eth_pd->port_serial_control =
 320             mv64x60_read(&bh, MV643XX_ETH_PORT_SERIAL_CONTROL_REG(pd->id) & ~1);
 321
 322         eth_pd->force_phy_addr = 1;
 323         eth_pd->phy_addr = pd->id;
 324         eth_pd->tx_queue_size = 400;
 325         eth_pd->rx_queue_size = 800;
 326 }
 327 #endif
 328
 329 static void __init hdpu_fixup_mpsc_pdata(struct platform_device *pd)
 330 {
 331
 332         struct mpsc_pdata *pdata;
 333
 334         pdata = (struct mpsc_pdata *)pd->dev.platform_data;
 335
 336         pdata->max_idle = 40;
 337         if (ppcboot_bd_valid)
 338                 pdata->default_baud = ppcboot_bd.bi_baudrate;
 339         else
 340                 pdata->default_baud = HDPU_DEFAULT_BAUD;
 341         pdata->brg_clk_src = HDPU_MPSC_CLK_SRC;
 342         pdata->brg_clk_freq = HDPU_MPSC_CLK_FREQ;
 343 }
 344
 345 #if defined(CONFIG_HDPU_FEATURES)
 346 static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd)
 347 {
 348         struct platform_device *pds[1];
 349         pds[0] = pd;
 350         mv64x60_pd_fixup(&bh, pds, 1);
 351 }
 352 #endif
 353
 354 static int __init hdpu_platform_notify(struct device *dev)
 355 {
 356         static struct {
 357                 char *bus_id;
 358                 void ((*rtn) (struct platform_device * pdev));
 359         } dev_map[] = {
 360                 {
 361                 MPSC_CTLR_NAME ".0", hdpu_fixup_mpsc_pdata},
 362 #if defined(CONFIG_MV643XX_ETH)
 363                 {
 364                 MV643XX_ETH_NAME ".0", hdpu_fixup_eth_pdata},
 365 #endif
 366 #if defined(CONFIG_HDPU_FEATURES)
 367                 {
 368                 HDPU_CPUSTATE_NAME ".0", hdpu_fixup_cpustate_pdata},
 369 #endif
 370         };
 371         struct platform_device *pdev;
 372         int i;
 373
 374         if (dev && dev->bus_id)
 375                 for (i = 0; i < ARRAY_SIZE(dev_map); i++)
 376                         if (!strncmp(dev->bus_id, dev_map[i].bus_id,
 377                                      BUS_ID_SIZE)) {
 378
 379                                 pdev = container_of(dev,
 380                                                     struct platform_device,
 381                                                     dev);
 382                                 dev_map[i].rtn(pdev);
 383                         }
 384
 385         return 0;
 386 }
 387
 388 static void __init hdpu_setup_arch(void)
 389 {
 390         if (ppc_md.progress)
 391                 ppc_md.progress("hdpu_setup_arch: enter", 0);
 392 #ifdef CONFIG_BLK_DEV_INITRD
 393         if (initrd_start)
 394                 ROOT_DEV = Root_RAM0;
 395         else
 396 #endif
 397 #ifdef  CONFIG_ROOT_NFS
 398                 ROOT_DEV = Root_NFS;
 399 #else
 400                 ROOT_DEV = Root_SDA2;
 401 #endif
 402
 403         ppc_md.heartbeat = hdpu_heartbeat;
 404
 405         ppc_md.heartbeat_reset = HZ;
 406         ppc_md.heartbeat_count = 1;
 407
 408         if (ppc_md.progress)
 409                 ppc_md.progress("hdpu_setup_arch: Enabling L2 cache", 0);
 410
 411         /* Enable L1 Parity Bits */
 412         hdpu_set_l1pe();
 413
 414         /* Enable L2 and L3 caches (if 745x) */
 415         _set_L2CR(0x80080000);
 416
 417         if (ppc_md.progress)
 418                 ppc_md.progress("hdpu_setup_arch: enter", 0);
 419
 420         hdpu_setup_bridge();
 421
 422         hdpu_setup_peripherals();
 423
 424 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
 425         hdpu_early_serial_map();
 426 #endif
 427
 428         printk("SKY HDPU Compute Blade \n");
 429
 430         if (ppc_md.progress)
 431                 ppc_md.progress("hdpu_setup_arch: exit", 0);
 432
 433         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_OK);
 434         return;
 435 }
 436 static void __init hdpu_init_irq(void)
 437 {
 438         mv64360_init_irq();
 439 }
 440
 441 static void __init hdpu_set_l1pe()
 442 {
 443         unsigned long ictrl;
 444         asm volatile ("mfspr %0, 1011":"=r" (ictrl):);
 445         ictrl |= ICTRL_EICE | ICTRL_EDC | ICTRL_EICP;
 446         asm volatile ("mtspr 1011, %0"::"r" (ictrl));
 447 }
 448
 449 /*
 450  * Set BAT 1 to map 0xf1000000 to end of physical memory space.
 451  */
 452 static __inline__ void hdpu_set_bat(void)
 453 {
 454         mb();
 455         mtspr(SPRN_DBAT1U, 0xf10001fe);
 456         mtspr(SPRN_DBAT1L, 0xf100002a);
 457         mb();
 458
 459         return;
 460 }
 461
 462 unsigned long __init hdpu_find_end_of_memory(void)
 463 {
 464         return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 465                                     MV64x60_TYPE_MV64360);
 466 }
 467
 468 static void hdpu_reset_board(void)
 469 {
 470         volatile int infinite = 1;
 471
 472         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_RESET);
 473
 474         local_irq_disable();
 475
 476         /* Clear all the LEDs */
 477         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) |
 478                                                    (1 << 5) | (1 << 6)));
 479
 480         /* disable and invalidate the L2 cache */
 481         _set_L2CR(0);
 482         _set_L2CR(0x200000);
 483
 484         /* flush and disable L1 I/D cache */
 485         __asm__ __volatile__
 486             ("\n"
 487              "mfspr   3,1008\n"
 488              "ori       5,5,0xcc00\n"
 489              "ori       4,3,0xc00\n"
 490              "andc      5,3,5\n"
 491              "sync\n"
 492              "mtspr     1008,4\n"
 493              "isync\n" "sync\n" "mtspr  1008,5\n" "isync\n" "sync\n");
 494
 495         /* Hit the reset bit */
 496         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 3));
 497
 498         while (infinite)
 499                 infinite = infinite;
 500
 501         return;
 502 }
 503
 504 static void hdpu_restart(char *cmd)
 505 {
 506         volatile ulong i = 10000000;
 507
 508         hdpu_reset_board();
 509
 510         while (i-- > 0) ;
 511         panic("restart failed\n");
 512 }
 513
 514 static void hdpu_halt(void)
 515 {
 516         local_irq_disable();
 517
 518         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_HALT);
 519
 520         /* Clear all the LEDs */
 521         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) | (1 << 5) |
 522                                                    (1 << 6)));
 523         while (1) ;
 524         /* NOTREACHED */
 525 }
 526
 527 static void hdpu_power_off(void)
 528 {
 529         hdpu_halt();
 530         /* NOTREACHED */
 531 }
 532
 533 static int hdpu_show_cpuinfo(struct seq_file *m)
 534 {
 535         uint pvid;
 536
 537         pvid = mfspr(SPRN_PVR);
 538         seq_printf(m, "vendor\t\t: Sky Computers\n");
 539         seq_printf(m, "machine\t\t: HDPU Compute Blade\n");
 540         seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
 541                    pvid, (pvid & (1 << 15) ? "IBM" : "Motorola"));
 542
 543         return 0;
 544 }
 545
 546 static void __init hdpu_calibrate_decr(void)
 547 {
 548         ulong freq;
 549
 550         if (ppcboot_bd_valid)
 551                 freq = ppcboot_bd.bi_busfreq / 4;
 552         else
 553                 freq = 133000000;
 554
 555         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
 556                freq / 1000000, freq % 1000000);
 557
 558         tb_ticks_per_jiffy = freq / HZ;
 559         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 560
 561         return;
 562 }
 563
 564 static void parse_bootinfo(unsigned long r3,
 565                            unsigned long r4, unsigned long r5,
 566                            unsigned long r6, unsigned long r7)
 567 {
 568         bd_t *bd = NULL;
 569         char *cmdline_start = NULL;
 570         int cmdline_len = 0;
 571
 572         if (r3) {
 573                 if ((r3 & 0xf0000000) == 0)
 574                         r3 += KERNELBASE;
 575                 if ((r3 & 0xf0000000) == KERNELBASE) {
 576                         bd = (void *)r3;
 577
 578                         memcpy(&ppcboot_bd, bd, sizeof(ppcboot_bd));
 579                         ppcboot_bd_valid = 1;
 580                 }
 581         }
 582 #ifdef CONFIG_BLK_DEV_INITRD
 583         if (r4 && r5 && r5 > r4) {
 584                 if ((r4 & 0xf0000000) == 0)
 585                         r4 += KERNELBASE;
 586                 if ((r5 & 0xf0000000) == 0)
 587                         r5 += KERNELBASE;
 588                 if ((r4 & 0xf0000000) == KERNELBASE) {
 589                         initrd_start = r4;
 590                         initrd_end = r5;
 591                         initrd_below_start_ok = 1;
 592                 }
 593         }
 594 #endif                          /* CONFIG_BLK_DEV_INITRD */
 595
 596         if (r6 && r7 && r7 > r6) {
 597                 if ((r6 & 0xf0000000) == 0)
 598                         r6 += KERNELBASE;
 599                 if ((r7 & 0xf0000000) == 0)
 600                         r7 += KERNELBASE;
 601                 if ((r6 & 0xf0000000) == KERNELBASE) {
 602                         cmdline_start = (void *)r6;
 603                         cmdline_len = (r7 - r6);
 604                         strncpy(cmd_line, cmdline_start, cmdline_len);
 605                 }
 606         }
 607 }
 608
 609 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 610 static void
 611 hdpu_ide_request_region(ide_ioreg_t from, unsigned int extent, const char *name)
 612 {
 613         request_region(from, extent, name);
 614         return;
 615 }
 616
 617 static void hdpu_ide_release_region(ide_ioreg_t from, unsigned int extent)
 618 {
 619         release_region(from, extent);
 620         return;
 621 }
 622
 623 static void __init
 624 hdpu_ide_pci_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
 625                              ide_ioreg_t ctrl_port, int *irq)
 626 {
 627         struct pci_dev *dev;
 628
 629         pci_for_each_dev(dev) {
 630                 if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) ||
 631                     ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)) {
 632                         hw->irq = dev->irq;
 633
 634                         if (irq != NULL) {
 635                                 *irq = dev->irq;
 636                         }
 637                 }
 638         }
 639
 640         return;
 641 }
 642 #endif
 643
 644 void hdpu_heartbeat(void)
 645 {
 646         if (mv64x60_read(&bh, MV64x60_GPP_VALUE) & (1 << 5))
 647                 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 5));
 648         else
 649                 mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, (1 << 5));
 650
 651         ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
 652
 653 }
 654
 655 static void __init hdpu_map_io(void)
 656 {
 657         io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO);
 658 }
 659
 660 #ifdef CONFIG_SMP
 661 char hdpu_smp0[] = "SMP Cpu #0";
 662 char hdpu_smp1[] = "SMP Cpu #1";
 663
 664 static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id,
 665                                              struct pt_regs *regs)
 666 {
 667         volatile unsigned int doorbell;
 668
 669         doorbell = mv64x60_read(&bh, MV64360_CPU0_DOORBELL);
 670
 671         /* Ack the doorbell interrupts */
 672         mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, doorbell);
 673
 674         if (doorbell & 1) {
 675                 smp_message_recv(0, regs);
 676         }
 677         if (doorbell & 2) {
 678                 smp_message_recv(1, regs);
 679         }
 680         if (doorbell & 4) {
 681                 smp_message_recv(2, regs);
 682         }
 683         if (doorbell & 8) {
 684                 smp_message_recv(3, regs);
 685         }
 686         return IRQ_HANDLED;
 687 }
 688
 689 static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id,
 690                                              struct pt_regs *regs)
 691 {
 692         volatile unsigned int doorbell;
 693
 694         doorbell = mv64x60_read(&bh, MV64360_CPU1_DOORBELL);
 695
 696         /* Ack the doorbell interrupts */
 697         mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, doorbell);
 698
 699         if (doorbell & 1) {
 700                 smp_message_recv(0, regs);
 701         }
 702         if (doorbell & 2) {
 703                 smp_message_recv(1, regs);
 704         }
 705         if (doorbell & 4) {
 706                 smp_message_recv(2, regs);
 707         }
 708         if (doorbell & 8) {
 709                 smp_message_recv(3, regs);
 710         }
 711         return IRQ_HANDLED;
 712 }
 713
 714 static void smp_hdpu_CPU_two(void)
 715 {
 716         __asm__ __volatile__
 717             ("\n"
 718              "lis     3,0x0000\n"
 719              "ori     3,3,0x00c0\n"
 720              "mtspr   26, 3\n" "li      4,0\n" "mtspr   27,4\n" "rfi");
 721
 722 }
 723
 724 static int smp_hdpu_probe(void)
 725 {
 726         int *cpu_count_reg;
 727         int num_cpus = 0;
 728
 729         cpu_count_reg = ioremap(HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE);
 730         if (cpu_count_reg) {
 731                 num_cpus = (*cpu_count_reg >> 20) & 0x3;
 732                 iounmap(cpu_count_reg);
 733         }
 734
 735         /* Validate the bits in the CPLD. If we could not map the reg, return 2.
 736          * If the register reported 0 or 3, return 2.
 737          * Older CPLD revisions set these bits to all ones (val = 3).
 738          */
 739         if ((num_cpus < 1) || (num_cpus > 2)) {
 740                 printk
 741                     ("Unable to determine the number of processors %d . deafulting to 2.\n",
 742                      num_cpus);
 743                 num_cpus = 2;
 744         }
 745         return num_cpus;
 746 }
 747
 748 static void
 749 smp_hdpu_message_pass(int target, int msg)
 750 {
 751         if (msg > 0x3) {
 752                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
 753                        smp_processor_id(), msg);
 754                 return;
 755         }
 756         switch (target) {
 757         case MSG_ALL:
 758                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
 759                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
 760                 break;
 761         case MSG_ALL_BUT_SELF:
 762                 if (smp_processor_id())
 763                         mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
 764                 else
 765                         mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
 766                 break;
 767         default:
 768                 if (target == 0)
 769                         mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
 770                 else
 771                         mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
 772                 break;
 773         }
 774 }
 775
 776 static void smp_hdpu_kick_cpu(int nr)
 777 {
 778         volatile unsigned int *bootaddr;
 779
 780         if (ppc_md.progress)
 781                 ppc_md.progress("smp_hdpu_kick_cpu", 0);
 782
 783         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_CPU1_KICK);
 784
 785        /* Disable BootCS. Must also reduce the windows size to zero. */
 786         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 787         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 0, 0, 0);
 788
 789         bootaddr = ioremap(HDPU_INTERNAL_SRAM_BASE, HDPU_INTERNAL_SRAM_SIZE);
 790         if (!bootaddr) {
 791                 if (ppc_md.progress)
 792                         ppc_md.progress("smp_hdpu_kick_cpu: ioremap failed", 0);
 793                 return;
 794         }
 795
 796         memcpy((void *)(bootaddr + 0x40), (void *)&smp_hdpu_CPU_two, 0x20);
 797
 798         /* map SRAM to 0xfff00000 */
 799         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 800
 801         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 802                                  0xfff00000, HDPU_INTERNAL_SRAM_SIZE, 0);
 803         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 804
 805         /* Enable CPU1 arbitration */
 806         mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1 << 9));
 807
 808         /*
 809          * Wait 100mSecond until other CPU has reached __secondary_start.
 810          * When it reaches, it is permittable to rever the SRAM mapping etc...
 811          */
 812         mdelay(100);
 813         *(unsigned long *)KERNELBASE = nr;
 814         asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
 815
 816         iounmap(bootaddr);
 817
 818         /* Set up window for internal sram (256KByte insize) */
 819         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 820         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 821                                  HDPU_INTERNAL_SRAM_BASE,
 822                                  HDPU_INTERNAL_SRAM_SIZE, 0);
 823         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 824         /*
 825          * Set up windows for embedded FLASH (using boot CS window).
 826          */
 827
 828         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 829         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 830                                  HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
 831         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 832 }
 833
 834 static void smp_hdpu_setup_cpu(int cpu_nr)
 835 {
 836         if (cpu_nr == 0) {
 837                 if (ppc_md.progress)
 838                         ppc_md.progress("smp_hdpu_setup_cpu 0", 0);
 839                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff);
 840                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff);
 841                 request_irq(60, hdpu_smp_cpu0_int_handler,
 842                             SA_INTERRUPT, hdpu_smp0, 0);
 843         }
 844
 845         if (cpu_nr == 1) {
 846                 if (ppc_md.progress)
 847                         ppc_md.progress("smp_hdpu_setup_cpu 1", 0);
 848
 849                 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR |
 850                                   CPUSTATE_KERNEL_CPU1_OK);
 851
 852                 /* Enable L1 Parity Bits */
 853                 hdpu_set_l1pe();
 854
 855                 /* Enable L2 cache */
 856                 _set_L2CR(0);
 857                 _set_L2CR(0x80080000);
 858
 859                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0);
 860                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff);
 861                 request_irq(28, hdpu_smp_cpu1_int_handler,
 862                             SA_INTERRUPT, hdpu_smp1, 0);
 863         }
 864
 865 }
 866
 867 void __devinit hdpu_tben_give()
 868 {
 869         volatile unsigned long *val = 0;
 870
 871         /* By writing 0 to the TBEN_BASE, the timebases is frozen */
 872         val = ioremap(HDPU_TBEN_BASE, 4);
 873         *val = 0;
 874         mb();
 875
 876         spin_lock(&timebase_lock);
 877         timebase_upper = get_tbu();
 878         timebase_lower = get_tbl();
 879         spin_unlock(&timebase_lock);
 880
 881         while (timebase_upper || timebase_lower)
 882                 barrier();
 883
 884         /* By writing 1 to the TBEN_BASE, the timebases is thawed */
 885         *val = 1;
 886         mb();
 887
 888         iounmap(val);
 889
 890 }
 891
 892 void __devinit hdpu_tben_take()
 893 {
 894         while (!(timebase_upper || timebase_lower))
 895                 barrier();
 896
 897         spin_lock(&timebase_lock);
 898         set_tb(timebase_upper, timebase_lower);
 899         timebase_upper = 0;
 900         timebase_lower = 0;
 901         spin_unlock(&timebase_lock);
 902 }
 903
 904 static struct smp_ops_t hdpu_smp_ops = {
 905         .message_pass = smp_hdpu_message_pass,
 906         .probe = smp_hdpu_probe,
 907         .kick_cpu = smp_hdpu_kick_cpu,
 908         .setup_cpu = smp_hdpu_setup_cpu,
 909         .give_timebase = hdpu_tben_give,
 910         .take_timebase = hdpu_tben_take,
 911 };
 912 #endif                          /* CONFIG_SMP */
 913
 914 void __init
 915 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 916               unsigned long r6, unsigned long r7)
 917 {
 918         parse_bootinfo(r3, r4, r5, r6, r7);
 919
 920         isa_mem_base = 0;
 921
 922         ppc_md.setup_arch = hdpu_setup_arch;
 923         ppc_md.init = hdpu_init2;
 924         ppc_md.show_cpuinfo = hdpu_show_cpuinfo;
 925         ppc_md.init_IRQ = hdpu_init_irq;
 926         ppc_md.get_irq = mv64360_get_irq;
 927         ppc_md.restart = hdpu_restart;
 928         ppc_md.power_off = hdpu_power_off;
 929         ppc_md.halt = hdpu_halt;
 930         ppc_md.find_end_of_memory = hdpu_find_end_of_memory;
 931         ppc_md.calibrate_decr = hdpu_calibrate_decr;
 932         ppc_md.setup_io_mappings = hdpu_map_io;
 933
 934         bh.p_base = CONFIG_MV64X60_NEW_BASE;
 935         bh.v_base = (unsigned long *)bh.p_base;
 936
 937         hdpu_set_bat();
 938
 939 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
 940         ppc_md.progress = hdpu_mpsc_progress;   /* embedded UART */
 941         mv64x60_progress_init(bh.p_base);
 942 #endif                          /* CONFIG_SERIAL_TEXT_DEBUG */
 943
 944 #ifdef CONFIG_SMP
 945         smp_ops = &hdpu_smp_ops;
 946 #endif                          /* CONFIG_SMP */
 947
 948 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
 949         platform_notify = hdpu_platform_notify;
 950 #endif
 951         return;
 952 }
 953
 954 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 955 /* SMP safe version of the serial text debug routine. Uses Semaphore 0 */
 956 void hdpu_mpsc_progress(char *s, unsigned short hex)
 957 {
 958         while (mv64x60_read(&bh, MV64360_WHO_AM_I) !=
 959                mv64x60_read(&bh, MV64360_SEMAPHORE_0)) {
 960         }
 961         mv64x60_mpsc_progress(s, hex);
 962         mv64x60_write(&bh, MV64360_SEMAPHORE_0, 0xff);
 963 }
 964 #endif
 965
 966 static void hdpu_cpustate_set(unsigned char new_state)
 967 {
 968         unsigned int state = (new_state << 21);
 969         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (0xff << 21));
 970         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, state);
 971 }
 972
 973 #ifdef CONFIG_MTD_PHYSMAP
 974 static struct mtd_partition hdpu_partitions[] = {
 975         {
 976          .name = "Root FS",
 977          .size = 0x03400000,
 978          .offset = 0,
 979          .mask_flags = 0,
 980          },{
 981          .name = "User FS",
 982          .size = 0x00800000,
 983          .offset = 0x03400000,
 984          .mask_flags = 0,
 985          },{
 986          .name = "Kernel Image",
 987          .size = 0x002C0000,
 988          .offset = 0x03C00000,
 989          .mask_flags = 0,
 990          },{
 991          .name = "bootEnv",
 992          .size = 0x00040000,
 993          .offset = 0x03EC0000,
 994          .mask_flags = 0,
 995          },{
 996          .name = "bootROM",
 997          .size = 0x00100000,
 998          .offset = 0x03F00000,
 999          .mask_flags = 0,
1000          }
1001 };
1002
1003 static int __init hdpu_setup_mtd(void)
1004 {
1005
1006         physmap_set_partitions(hdpu_partitions, 5);
1007         return 0;
1008 }
1009
1010 arch_initcall(hdpu_setup_mtd);
1011 #endif
1012
1013 #ifdef CONFIG_HDPU_FEATURES
1014
1015 static struct resource hdpu_cpustate_resources[] = {
1016         [0] = {
1017                .name = "addr base",
1018                .start = MV64x60_GPP_VALUE_SET,
1019                .end = MV64x60_GPP_VALUE_CLR + 1,
1020                .flags = IORESOURCE_MEM,
1021                },
1022 };
1023
1024 static struct resource hdpu_nexus_resources[] = {
1025         [0] = {
1026                .name = "nexus register",
1027                .start = HDPU_NEXUS_ID_BASE,
1028                .end = HDPU_NEXUS_ID_BASE + HDPU_NEXUS_ID_SIZE,
1029                .flags = IORESOURCE_MEM,
1030                },
1031 };
1032
1033 static struct platform_device hdpu_cpustate_device = {
1034         .name = HDPU_CPUSTATE_NAME,
1035         .id = 0,
1036         .num_resources = ARRAY_SIZE(hdpu_cpustate_resources),
1037         .resource = hdpu_cpustate_resources,
1038 };
1039
1040 static struct platform_device hdpu_nexus_device = {
1041         .name = HDPU_NEXUS_NAME,
1042         .id = 0,
1043         .num_resources = ARRAY_SIZE(hdpu_nexus_resources),
1044         .resource = hdpu_nexus_resources,
1045 };
1046
1047 static int __init hdpu_add_pds(void)
1048 {
1049         platform_device_register(&hdpu_cpustate_device);
1050         platform_device_register(&hdpu_nexus_device);
1051         return 0;
1052 }
1053
1054 arch_initcall(hdpu_add_pds);
1055 #endif