arch/ppc/platforms/hdpu.c

   1
   2 /*
   3  * arch/ppc/platforms/hdpu_setup.c
   4  *
   5  * Board setup routines for the Sky Computers HDPU Compute Blade.
   6  *
   7  * Written by Brian Waite <waite@skycomputers.com>
   8  *
   9  * Based on code done by - Mark A. Greer <mgreer@mvista.com>
  10  *                         Rabeeh Khoury - rabeeh@galileo.co.il
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/pci.h>
  21 #include <linux/delay.h>
  22 #include <linux/irq.h>
  23 #include <linux/ide.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/platform_device.h>
  26
  27 #include <linux/initrd.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/smp.h>
  30
  31 #include <asm/time.h>
  32 #include <asm/machdep.h>
  33 #include <asm/todc.h>
  34 #include <asm/mv64x60.h>
  35 #include <asm/ppcboot.h>
  36 #include <platforms/hdpu.h>
  37 #include <linux/mv643xx.h>
  38 #include <linux/hdpu_features.h>
  39 #include <linux/device.h>
  40 #include <linux/mtd/physmap.h>
  41
  42 #define BOARD_VENDOR    "Sky Computers"
  43 #define BOARD_MACHINE   "HDPU-CB-A"
  44
  45 bd_t ppcboot_bd;
  46 int ppcboot_bd_valid = 0;
  47
  48 static mv64x60_handle_t bh;
  49
  50 extern char cmd_line[];
  51
  52 unsigned long hdpu_find_end_of_memory(void);
  53 void hdpu_mpsc_progress(char *s, unsigned short hex);
  54 void hdpu_heartbeat(void);
  55
  56 static void parse_bootinfo(unsigned long r3,
  57                            unsigned long r4, unsigned long r5,
  58                            unsigned long r6, unsigned long r7);
  59 static void hdpu_set_l1pe(void);
  60 static void hdpu_cpustate_set(unsigned char new_state);
  61 #ifdef CONFIG_SMP
  62 static DEFINE_SPINLOCK(timebase_lock);
  63 static unsigned int timebase_upper = 0, timebase_lower = 0;
  64 extern int smp_tb_synchronized;
  65
  66 void __devinit hdpu_tben_give(void);
  67 void __devinit hdpu_tben_take(void);
  68 #endif
  69
  70 static int __init
  71 hdpu_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  72 {
  73         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
  74
  75         if (hose->index == 0) {
  76                 static char pci_irq_table[][4] = {
  77                         {HDPU_PCI_0_IRQ, 0, 0, 0},
  78                         {HDPU_PCI_0_IRQ, 0, 0, 0},
  79                 };
  80
  81                 const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
  82                 return PCI_IRQ_TABLE_LOOKUP;
  83         } else {
  84                 static char pci_irq_table[][4] = {
  85                         {HDPU_PCI_1_IRQ, 0, 0, 0},
  86                 };
  87
  88                 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
  89                 return PCI_IRQ_TABLE_LOOKUP;
  90         }
  91 }
  92
  93 static void __init hdpu_intr_setup(void)
  94 {
  95         mv64x60_write(&bh, MV64x60_GPP_IO_CNTL,
  96                       (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
  97                        (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) |
  98                        (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) |
  99                        (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) |
 100                        (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29)));
 101
 102         /* XXXX Erranum FEr PCI-#8 */
 103         mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1 << 5) | (1 << 9));
 104         mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1 << 5) | (1 << 9));
 105
 106         /*
 107          * Dismiss and then enable interrupt on GPP interrupt cause
 108          * for CPU #0
 109          */
 110         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~((1 << 8) | (1 << 13)));
 111         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1 << 8) | (1 << 13));
 112
 113         /*
 114          * Dismiss and then enable interrupt on CPU #0 high cause reg
 115          * BIT25 summarizes GPP interrupts 8-15
 116          */
 117         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1 << 25));
 118 }
 119
 120 static void __init hdpu_setup_peripherals(void)
 121 {
 122         unsigned int val;
 123
 124         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 125                                  HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
 126         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 127
 128         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
 129                                  HDPU_TBEN_BASE, HDPU_TBEN_SIZE, 0);
 130         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 131
 132         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 133                                  HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE, 0);
 134         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 135
 136         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 137                                  HDPU_INTERNAL_SRAM_BASE,
 138                                  HDPU_INTERNAL_SRAM_SIZE, 0);
 139         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 140
 141         bh.ci->disable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
 142         mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, 0, 0, 0);
 143
 144         mv64x60_clr_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, (1 << 3));
 145         mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
 146         mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
 147                          ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
 148
 149         /* Enable pipelining */
 150         mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13));
 151         /* Enable Snoop Pipelineing */
 152         mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24));
 153
 154         /*
 155          * Change DRAM read buffer assignment.
 156          * Assign read buffer 0 dedicated only for CPU,
 157          * and the rest read buffer 1.
 158          */
 159         val = mv64x60_read(&bh, MV64360_SDRAM_CONFIG);
 160         val = val & 0x03ffffff;
 161         val = val | 0xf8000000;
 162         mv64x60_write(&bh, MV64360_SDRAM_CONFIG, val);
 163
 164         /*
 165          * Configure internal SRAM -
 166          * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set
 167          * Parity enabled.
 168          * Parity error propagation
 169          * Arbitration not parked for CPU only
 170          * Other bits are reserved.
 171          */
 172 #ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
 173         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 174 #else
 175         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
 176 #endif
 177
 178         hdpu_intr_setup();
 179 }
 180
 181 static void __init hdpu_setup_bridge(void)
 182 {
 183         struct mv64x60_setup_info si;
 184         int i;
 185
 186         memset(&si, 0, sizeof(si));
 187
 188         si.phys_reg_base = HDPU_BRIDGE_REG_BASE;
 189         si.pci_0.enable_bus = 1;
 190         si.pci_0.pci_io.cpu_base = HDPU_PCI0_IO_START_PROC_ADDR;
 191         si.pci_0.pci_io.pci_base_hi = 0;
 192         si.pci_0.pci_io.pci_base_lo = HDPU_PCI0_IO_START_PCI_ADDR;
 193         si.pci_0.pci_io.size = HDPU_PCI0_IO_SIZE;
 194         si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
 195         si.pci_0.pci_mem[0].cpu_base = HDPU_PCI0_MEM_START_PROC_ADDR;
 196         si.pci_0.pci_mem[0].pci_base_hi = HDPU_PCI0_MEM_START_PCI_HI_ADDR;
 197         si.pci_0.pci_mem[0].pci_base_lo = HDPU_PCI0_MEM_START_PCI_LO_ADDR;
 198         si.pci_0.pci_mem[0].size = HDPU_PCI0_MEM_SIZE;
 199         si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
 200         si.pci_0.pci_cmd_bits = 0;
 201         si.pci_0.latency_timer = 0x80;
 202
 203         si.pci_1.enable_bus = 1;
 204         si.pci_1.pci_io.cpu_base = HDPU_PCI1_IO_START_PROC_ADDR;
 205         si.pci_1.pci_io.pci_base_hi = 0;
 206         si.pci_1.pci_io.pci_base_lo = HDPU_PCI1_IO_START_PCI_ADDR;
 207         si.pci_1.pci_io.size = HDPU_PCI1_IO_SIZE;
 208         si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
 209         si.pci_1.pci_mem[0].cpu_base = HDPU_PCI1_MEM_START_PROC_ADDR;
 210         si.pci_1.pci_mem[0].pci_base_hi = HDPU_PCI1_MEM_START_PCI_HI_ADDR;
 211         si.pci_1.pci_mem[0].pci_base_lo = HDPU_PCI1_MEM_START_PCI_LO_ADDR;
 212         si.pci_1.pci_mem[0].size = HDPU_PCI1_MEM_SIZE;
 213         si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
 214         si.pci_1.pci_cmd_bits = 0;
 215         si.pci_1.latency_timer = 0x80;
 216
 217         for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
 218 #if defined(CONFIG_NOT_COHERENT_CACHE)
 219                 si.cpu_prot_options[i] = 0;
 220                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
 221                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
 222                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
 223
 224                 si.pci_1.acc_cntl_options[i] =
 225                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 226                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 227                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 228                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 229
 230                 si.pci_0.acc_cntl_options[i] =
 231                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 232                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 233                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 234                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 235
 236 #else
 237                 si.cpu_prot_options[i] = 0;
 238                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; /* errata */
 239                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; /* errata */
 240                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; /* errata */
 241
 242                 si.pci_0.acc_cntl_options[i] =
 243                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 244                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 245                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 246                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 247
 248                 si.pci_1.acc_cntl_options[i] =
 249                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 250                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 251                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 252                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 253 #endif
 254         }
 255
 256         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI);
 257
 258         /* Lookup PCI host bridges */
 259         mv64x60_init(&bh, &si);
 260         pci_dram_offset = 0;    /* System mem at same addr on PCI & cpu bus */
 261         ppc_md.pci_swizzle = common_swizzle;
 262         ppc_md.pci_map_irq = hdpu_map_irq;
 263
 264         mv64x60_set_bus(&bh, 0, 0);
 265         bh.hose_a->first_busno = 0;
 266         bh.hose_a->last_busno = 0xff;
 267         bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
 268
 269         bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
 270         mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
 271         bh.hose_b->last_busno = 0xff;
 272         bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
 273                 bh.hose_b->first_busno);
 274
 275         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 276
 277         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
 278         /*
 279          * Enabling of PCI internal-vs-external arbitration
 280          * is a platform- and errata-dependent decision.
 281          */
 282         return;
 283 }
 284
 285 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
 286 static void __init hdpu_early_serial_map(void)
 287 {
 288 #ifdef  CONFIG_KGDB
 289         static char first_time = 1;
 290
 291 #if defined(CONFIG_KGDB_TTYS0)
 292 #define KGDB_PORT 0
 293 #elif defined(CONFIG_KGDB_TTYS1)
 294 #define KGDB_PORT 1
 295 #else
 296 #error "Invalid kgdb_tty port"
 297 #endif
 298
 299         if (first_time) {
 300                 gt_early_mpsc_init(KGDB_PORT,
 301                                    B9600 | CS8 | CREAD | HUPCL | CLOCAL);
 302                 first_time = 0;
 303         }
 304
 305         return;
 306 #endif
 307 }
 308 #endif
 309
 310 static void hdpu_init2(void)
 311 {
 312         return;
 313 }
 314
 315 #if defined(CONFIG_MV643XX_ETH)
 316 static void __init hdpu_fixup_eth_pdata(struct platform_device *pd)
 317 {
 318
 319         struct mv643xx_eth_platform_data *eth_pd;
 320         eth_pd = pd->dev.platform_data;
 321
 322         eth_pd->port_serial_control =
 323             mv64x60_read(&bh, MV643XX_ETH_PORT_SERIAL_CONTROL_REG(pd->id) & ~1);
 324
 325         eth_pd->force_phy_addr = 1;
 326         eth_pd->phy_addr = pd->id;
 327         eth_pd->tx_queue_size = 400;
 328         eth_pd->rx_queue_size = 800;
 329 }
 330 #endif
 331
 332 static void __init hdpu_fixup_mpsc_pdata(struct platform_device *pd)
 333 {
 334
 335         struct mpsc_pdata *pdata;
 336
 337         pdata = (struct mpsc_pdata *)pd->dev.platform_data;
 338
 339         pdata->max_idle = 40;
 340         if (ppcboot_bd_valid)
 341                 pdata->default_baud = ppcboot_bd.bi_baudrate;
 342         else
 343                 pdata->default_baud = HDPU_DEFAULT_BAUD;
 344         pdata->brg_clk_src = HDPU_MPSC_CLK_SRC;
 345         pdata->brg_clk_freq = HDPU_MPSC_CLK_FREQ;
 346 }
 347
 348 #if defined(CONFIG_HDPU_FEATURES)
 349 static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd)
 350 {
 351         struct platform_device *pds[1];
 352         pds[0] = pd;
 353         mv64x60_pd_fixup(&bh, pds, 1);
 354 }
 355 #endif
 356
 357 static int __init hdpu_platform_notify(struct device *dev)
 358 {
 359         static struct {
 360                 char *bus_id;
 361                 void ((*rtn) (struct platform_device * pdev));
 362         } dev_map[] = {
 363                 {
 364                 MPSC_CTLR_NAME ".0", hdpu_fixup_mpsc_pdata},
 365 #if defined(CONFIG_MV643XX_ETH)
 366                 {
 367                 MV643XX_ETH_NAME ".0", hdpu_fixup_eth_pdata},
 368 #endif
 369 #if defined(CONFIG_HDPU_FEATURES)
 370                 {
 371                 HDPU_CPUSTATE_NAME ".0", hdpu_fixup_cpustate_pdata},
 372 #endif
 373         };
 374         struct platform_device *pdev;
 375         int i;
 376
 377         if (dev && dev->bus_id)
 378                 for (i = 0; i < ARRAY_SIZE(dev_map); i++)
 379                         if (!strncmp(dev->bus_id, dev_map[i].bus_id,
 380                                      BUS_ID_SIZE)) {
 381
 382                                 pdev = container_of(dev,
 383                                                     struct platform_device,
 384                                                     dev);
 385                                 dev_map[i].rtn(pdev);
 386                         }
 387
 388         return 0;
 389 }
 390
 391 static void __init hdpu_setup_arch(void)
 392 {
 393         if (ppc_md.progress)
 394                 ppc_md.progress("hdpu_setup_arch: enter", 0);
 395 #ifdef CONFIG_BLK_DEV_INITRD
 396         if (initrd_start)
 397                 ROOT_DEV = Root_RAM0;
 398         else
 399 #endif
 400 #ifdef  CONFIG_ROOT_NFS
 401                 ROOT_DEV = Root_NFS;
 402 #else
 403                 ROOT_DEV = Root_SDA2;
 404 #endif
 405
 406         ppc_md.heartbeat = hdpu_heartbeat;
 407
 408         ppc_md.heartbeat_reset = HZ;
 409         ppc_md.heartbeat_count = 1;
 410
 411         if (ppc_md.progress)
 412                 ppc_md.progress("hdpu_setup_arch: Enabling L2 cache", 0);
 413
 414         /* Enable L1 Parity Bits */
 415         hdpu_set_l1pe();
 416
 417         /* Enable L2 and L3 caches (if 745x) */
 418         _set_L2CR(0x80080000);
 419
 420         if (ppc_md.progress)
 421                 ppc_md.progress("hdpu_setup_arch: enter", 0);
 422
 423         hdpu_setup_bridge();
 424
 425         hdpu_setup_peripherals();
 426
 427 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
 428         hdpu_early_serial_map();
 429 #endif
 430
 431         printk("SKY HDPU Compute Blade \n");
 432
 433         if (ppc_md.progress)
 434                 ppc_md.progress("hdpu_setup_arch: exit", 0);
 435
 436         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_OK);
 437         return;
 438 }
 439 static void __init hdpu_init_irq(void)
 440 {
 441         mv64360_init_irq();
 442 }
 443
 444 static void __init hdpu_set_l1pe()
 445 {
 446         unsigned long ictrl;
 447         asm volatile ("mfspr %0, 1011":"=r" (ictrl):);
 448         ictrl |= ICTRL_EICE | ICTRL_EDC | ICTRL_EICP;
 449         asm volatile ("mtspr 1011, %0"::"r" (ictrl));
 450 }
 451
 452 /*
 453  * Set BAT 1 to map 0xf1000000 to end of physical memory space.
 454  */
 455 static __inline__ void hdpu_set_bat(void)
 456 {
 457         mb();
 458         mtspr(SPRN_DBAT1U, 0xf10001fe);
 459         mtspr(SPRN_DBAT1L, 0xf100002a);
 460         mb();
 461
 462         return;
 463 }
 464
 465 unsigned long __init hdpu_find_end_of_memory(void)
 466 {
 467         return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 468                                     MV64x60_TYPE_MV64360);
 469 }
 470
 471 static void hdpu_reset_board(void)
 472 {
 473         volatile int infinite = 1;
 474
 475         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_RESET);
 476
 477         local_irq_disable();
 478
 479         /* Clear all the LEDs */
 480         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) |
 481                                                    (1 << 5) | (1 << 6)));
 482
 483         /* disable and invalidate the L2 cache */
 484         _set_L2CR(0);
 485         _set_L2CR(0x200000);
 486
 487         /* flush and disable L1 I/D cache */
 488         __asm__ __volatile__
 489             ("\n"
 490              "mfspr   3,1008\n"
 491              "ori       5,5,0xcc00\n"
 492              "ori       4,3,0xc00\n"
 493              "andc      5,3,5\n"
 494              "sync\n"
 495              "mtspr     1008,4\n"
 496              "isync\n" "sync\n" "mtspr  1008,5\n" "isync\n" "sync\n");
 497
 498         /* Hit the reset bit */
 499         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 3));
 500
 501         while (infinite)
 502                 infinite = infinite;
 503
 504         return;
 505 }
 506
 507 static void hdpu_restart(char *cmd)
 508 {
 509         volatile ulong i = 10000000;
 510
 511         hdpu_reset_board();
 512
 513         while (i-- > 0) ;
 514         panic("restart failed\n");
 515 }
 516
 517 static void hdpu_halt(void)
 518 {
 519         local_irq_disable();
 520
 521         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_HALT);
 522
 523         /* Clear all the LEDs */
 524         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) | (1 << 5) |
 525                                                    (1 << 6)));
 526         while (1) ;
 527         /* NOTREACHED */
 528 }
 529
 530 static void hdpu_power_off(void)
 531 {
 532         hdpu_halt();
 533         /* NOTREACHED */
 534 }
 535
 536 static int hdpu_show_cpuinfo(struct seq_file *m)
 537 {
 538         uint pvid;
 539
 540         pvid = mfspr(SPRN_PVR);
 541         seq_printf(m, "vendor\t\t: Sky Computers\n");
 542         seq_printf(m, "machine\t\t: HDPU Compute Blade\n");
 543         seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
 544                    pvid, (pvid & (1 << 15) ? "IBM" : "Motorola"));
 545
 546         return 0;
 547 }
 548
 549 static void __init hdpu_calibrate_decr(void)
 550 {
 551         ulong freq;
 552
 553         if (ppcboot_bd_valid)
 554                 freq = ppcboot_bd.bi_busfreq / 4;
 555         else
 556                 freq = 133000000;
 557
 558         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
 559                freq / 1000000, freq % 1000000);
 560
 561         tb_ticks_per_jiffy = freq / HZ;
 562         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 563
 564         return;
 565 }
 566
 567 static void parse_bootinfo(unsigned long r3,
 568                            unsigned long r4, unsigned long r5,
 569                            unsigned long r6, unsigned long r7)
 570 {
 571         bd_t *bd = NULL;
 572         char *cmdline_start = NULL;
 573         int cmdline_len = 0;
 574
 575         if (r3) {
 576                 if ((r3 & 0xf0000000) == 0)
 577                         r3 += KERNELBASE;
 578                 if ((r3 & 0xf0000000) == KERNELBASE) {
 579                         bd = (void *)r3;
 580
 581                         memcpy(&ppcboot_bd, bd, sizeof(ppcboot_bd));
 582                         ppcboot_bd_valid = 1;
 583                 }
 584         }
 585 #ifdef CONFIG_BLK_DEV_INITRD
 586         if (r4 && r5 && r5 > r4) {
 587                 if ((r4 & 0xf0000000) == 0)
 588                         r4 += KERNELBASE;
 589                 if ((r5 & 0xf0000000) == 0)
 590                         r5 += KERNELBASE;
 591                 if ((r4 & 0xf0000000) == KERNELBASE) {
 592                         initrd_start = r4;
 593                         initrd_end = r5;
 594                         initrd_below_start_ok = 1;
 595                 }
 596         }
 597 #endif                          /* CONFIG_BLK_DEV_INITRD */
 598
 599         if (r6 && r7 && r7 > r6) {
 600                 if ((r6 & 0xf0000000) == 0)
 601                         r6 += KERNELBASE;
 602                 if ((r7 & 0xf0000000) == 0)
 603                         r7 += KERNELBASE;
 604                 if ((r6 & 0xf0000000) == KERNELBASE) {
 605                         cmdline_start = (void *)r6;
 606                         cmdline_len = (r7 - r6);
 607                         strncpy(cmd_line, cmdline_start, cmdline_len);
 608                 }
 609         }
 610 }
 611
 612 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 613 static void
 614 hdpu_ide_request_region(ide_ioreg_t from, unsigned int extent, const char *name)
 615 {
 616         request_region(from, extent, name);
 617         return;
 618 }
 619
 620 static void hdpu_ide_release_region(ide_ioreg_t from, unsigned int extent)
 621 {
 622         release_region(from, extent);
 623         return;
 624 }
 625
 626 static void __init
 627 hdpu_ide_pci_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
 628                              ide_ioreg_t ctrl_port, int *irq)
 629 {
 630         struct pci_dev *dev;
 631
 632         pci_for_each_dev(dev) {
 633                 if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) ||
 634                     ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)) {
 635                         hw->irq = dev->irq;
 636
 637                         if (irq != NULL) {
 638                                 *irq = dev->irq;
 639                         }
 640                 }
 641         }
 642
 643         return;
 644 }
 645 #endif
 646
 647 void hdpu_heartbeat(void)
 648 {
 649         if (mv64x60_read(&bh, MV64x60_GPP_VALUE) & (1 << 5))
 650                 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 5));
 651         else
 652                 mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, (1 << 5));
 653
 654         ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
 655
 656 }
 657
 658 static void __init hdpu_map_io(void)
 659 {
 660         io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO);
 661 }
 662
 663 #ifdef CONFIG_SMP
 664 char hdpu_smp0[] = "SMP Cpu #0";
 665 char hdpu_smp1[] = "SMP Cpu #1";
 666
 667 static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id,
 668                                              struct pt_regs *regs)
 669 {
 670         volatile unsigned int doorbell;
 671
 672         doorbell = mv64x60_read(&bh, MV64360_CPU0_DOORBELL);
 673
 674         /* Ack the doorbell interrupts */
 675         mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, doorbell);
 676
 677         if (doorbell & 1) {
 678                 smp_message_recv(0, regs);
 679         }
 680         if (doorbell & 2) {
 681                 smp_message_recv(1, regs);
 682         }
 683         if (doorbell & 4) {
 684                 smp_message_recv(2, regs);
 685         }
 686         if (doorbell & 8) {
 687                 smp_message_recv(3, regs);
 688         }
 689         return IRQ_HANDLED;
 690 }
 691
 692 static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id,
 693                                              struct pt_regs *regs)
 694 {
 695         volatile unsigned int doorbell;
 696
 697         doorbell = mv64x60_read(&bh, MV64360_CPU1_DOORBELL);
 698
 699         /* Ack the doorbell interrupts */
 700         mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, doorbell);
 701
 702         if (doorbell & 1) {
 703                 smp_message_recv(0, regs);
 704         }
 705         if (doorbell & 2) {
 706                 smp_message_recv(1, regs);
 707         }
 708         if (doorbell & 4) {
 709                 smp_message_recv(2, regs);
 710         }
 711         if (doorbell & 8) {
 712                 smp_message_recv(3, regs);
 713         }
 714         return IRQ_HANDLED;
 715 }
 716
 717 static void smp_hdpu_CPU_two(void)
 718 {
 719         __asm__ __volatile__
 720             ("\n"
 721              "lis     3,0x0000\n"
 722              "ori     3,3,0x00c0\n"
 723              "mtspr   26, 3\n" "li      4,0\n" "mtspr   27,4\n" "rfi");
 724
 725 }
 726
 727 static int smp_hdpu_probe(void)
 728 {
 729         int *cpu_count_reg;
 730         int num_cpus = 0;
 731
 732         cpu_count_reg = ioremap(HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE);
 733         if (cpu_count_reg) {
 734                 num_cpus = (*cpu_count_reg >> 20) & 0x3;
 735                 iounmap(cpu_count_reg);
 736         }
 737
 738         /* Validate the bits in the CPLD. If we could not map the reg, return 2.
 739          * If the register reported 0 or 3, return 2.
 740          * Older CPLD revisions set these bits to all ones (val = 3).
 741          */
 742         if ((num_cpus < 1) || (num_cpus > 2)) {
 743                 printk
 744                     ("Unable to determine the number of processors %d . deafulting to 2.\n",
 745                      num_cpus);
 746                 num_cpus = 2;
 747         }
 748         return num_cpus;
 749 }
 750
 751 static void
 752 smp_hdpu_message_pass(int target, int msg)
 753 {
 754         if (msg > 0x3) {
 755                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
 756                        smp_processor_id(), msg);
 757                 return;
 758         }
 759         switch (target) {
 760         case MSG_ALL:
 761                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
 762                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
 763                 break;
 764         case MSG_ALL_BUT_SELF:
 765                 if (smp_processor_id())
 766                         mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
 767                 else
 768                         mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
 769                 break;
 770         default:
 771                 if (target == 0)
 772                         mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
 773                 else
 774                         mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
 775                 break;
 776         }
 777 }
 778
 779 static void smp_hdpu_kick_cpu(int nr)
 780 {
 781         volatile unsigned int *bootaddr;
 782
 783         if (ppc_md.progress)
 784                 ppc_md.progress("smp_hdpu_kick_cpu", 0);
 785
 786         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_CPU1_KICK);
 787
 788        /* Disable BootCS. Must also reduce the windows size to zero. */
 789         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 790         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 0, 0, 0);
 791
 792         bootaddr = ioremap(HDPU_INTERNAL_SRAM_BASE, HDPU_INTERNAL_SRAM_SIZE);
 793         if (!bootaddr) {
 794                 if (ppc_md.progress)
 795                         ppc_md.progress("smp_hdpu_kick_cpu: ioremap failed", 0);
 796                 return;
 797         }
 798
 799         memcpy((void *)(bootaddr + 0x40), (void *)&smp_hdpu_CPU_two, 0x20);
 800
 801         /* map SRAM to 0xfff00000 */
 802         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 803
 804         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 805                                  0xfff00000, HDPU_INTERNAL_SRAM_SIZE, 0);
 806         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 807
 808         /* Enable CPU1 arbitration */
 809         mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1 << 9));
 810
 811         /*
 812          * Wait 100mSecond until other CPU has reached __secondary_start.
 813          * When it reaches, it is permittable to rever the SRAM mapping etc...
 814          */
 815         mdelay(100);
 816         *(unsigned long *)KERNELBASE = nr;
 817         asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
 818
 819         iounmap(bootaddr);
 820
 821         /* Set up window for internal sram (256KByte insize) */
 822         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 823         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 824                                  HDPU_INTERNAL_SRAM_BASE,
 825                                  HDPU_INTERNAL_SRAM_SIZE, 0);
 826         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 827         /*
 828          * Set up windows for embedded FLASH (using boot CS window).
 829          */
 830
 831         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 832         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 833                                  HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
 834         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 835 }
 836
 837 static void smp_hdpu_setup_cpu(int cpu_nr)
 838 {
 839         if (cpu_nr == 0) {
 840                 if (ppc_md.progress)
 841                         ppc_md.progress("smp_hdpu_setup_cpu 0", 0);
 842                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff);
 843                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff);
 844                 request_irq(60, hdpu_smp_cpu0_int_handler,
 845                             SA_INTERRUPT, hdpu_smp0, 0);
 846         }
 847
 848         if (cpu_nr == 1) {
 849                 if (ppc_md.progress)
 850                         ppc_md.progress("smp_hdpu_setup_cpu 1", 0);
 851
 852                 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR |
 853                                   CPUSTATE_KERNEL_CPU1_OK);
 854
 855                 /* Enable L1 Parity Bits */
 856                 hdpu_set_l1pe();
 857
 858                 /* Enable L2 cache */
 859                 _set_L2CR(0);
 860                 _set_L2CR(0x80080000);
 861
 862                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0);
 863                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff);
 864                 request_irq(28, hdpu_smp_cpu1_int_handler,
 865                             SA_INTERRUPT, hdpu_smp1, 0);
 866         }
 867
 868 }
 869
 870 void __devinit hdpu_tben_give()
 871 {
 872         volatile unsigned long *val = 0;
 873
 874         /* By writing 0 to the TBEN_BASE, the timebases is frozen */
 875         val = ioremap(HDPU_TBEN_BASE, 4);
 876         *val = 0;
 877         mb();
 878
 879         spin_lock(&timebase_lock);
 880         timebase_upper = get_tbu();
 881         timebase_lower = get_tbl();
 882         spin_unlock(&timebase_lock);
 883
 884         while (timebase_upper || timebase_lower)
 885                 barrier();
 886
 887         /* By writing 1 to the TBEN_BASE, the timebases is thawed */
 888         *val = 1;
 889         mb();
 890
 891         iounmap(val);
 892
 893 }
 894
 895 void __devinit hdpu_tben_take()
 896 {
 897         while (!(timebase_upper || timebase_lower))
 898                 barrier();
 899
 900         spin_lock(&timebase_lock);
 901         set_tb(timebase_upper, timebase_lower);
 902         timebase_upper = 0;
 903         timebase_lower = 0;
 904         spin_unlock(&timebase_lock);
 905 }
 906
 907 static struct smp_ops_t hdpu_smp_ops = {
 908         .message_pass = smp_hdpu_message_pass,
 909         .probe = smp_hdpu_probe,
 910         .kick_cpu = smp_hdpu_kick_cpu,
 911         .setup_cpu = smp_hdpu_setup_cpu,
 912         .give_timebase = hdpu_tben_give,
 913         .take_timebase = hdpu_tben_take,
 914 };
 915 #endif                          /* CONFIG_SMP */
 916
 917 void __init
 918 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 919               unsigned long r6, unsigned long r7)
 920 {
 921         parse_bootinfo(r3, r4, r5, r6, r7);
 922
 923         isa_mem_base = 0;
 924
 925         ppc_md.setup_arch = hdpu_setup_arch;
 926         ppc_md.init = hdpu_init2;
 927         ppc_md.show_cpuinfo = hdpu_show_cpuinfo;
 928         ppc_md.init_IRQ = hdpu_init_irq;
 929         ppc_md.get_irq = mv64360_get_irq;
 930         ppc_md.restart = hdpu_restart;
 931         ppc_md.power_off = hdpu_power_off;
 932         ppc_md.halt = hdpu_halt;
 933         ppc_md.find_end_of_memory = hdpu_find_end_of_memory;
 934         ppc_md.calibrate_decr = hdpu_calibrate_decr;
 935         ppc_md.setup_io_mappings = hdpu_map_io;
 936
 937         bh.p_base = CONFIG_MV64X60_NEW_BASE;
 938         bh.v_base = (unsigned long *)bh.p_base;
 939
 940         hdpu_set_bat();
 941
 942 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
 943         ppc_md.progress = hdpu_mpsc_progress;   /* embedded UART */
 944         mv64x60_progress_init(bh.p_base);
 945 #endif                          /* CONFIG_SERIAL_TEXT_DEBUG */
 946
 947 #ifdef CONFIG_SMP
 948         smp_ops = &hdpu_smp_ops;
 949 #endif                          /* CONFIG_SMP */
 950
 951 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
 952         platform_notify = hdpu_platform_notify;
 953 #endif
 954         return;
 955 }
 956
 957 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 958 /* SMP safe version of the serial text debug routine. Uses Semaphore 0 */
 959 void hdpu_mpsc_progress(char *s, unsigned short hex)
 960 {
 961         while (mv64x60_read(&bh, MV64360_WHO_AM_I) !=
 962                mv64x60_read(&bh, MV64360_SEMAPHORE_0)) {
 963         }
 964         mv64x60_mpsc_progress(s, hex);
 965         mv64x60_write(&bh, MV64360_SEMAPHORE_0, 0xff);
 966 }
 967 #endif
 968
 969 static void hdpu_cpustate_set(unsigned char new_state)
 970 {
 971         unsigned int state = (new_state << 21);
 972         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (0xff << 21));
 973         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, state);
 974 }
 975
 976 #ifdef CONFIG_MTD_PHYSMAP
 977 static struct mtd_partition hdpu_partitions[] = {
 978         {
 979          .name = "Root FS",
 980          .size = 0x03400000,
 981          .offset = 0,
 982          .mask_flags = 0,
 983          },{
 984          .name = "User FS",
 985          .size = 0x00800000,
 986          .offset = 0x03400000,
 987          .mask_flags = 0,
 988          },{
 989          .name = "Kernel Image",
 990          .size = 0x002C0000,
 991          .offset = 0x03C00000,
 992          .mask_flags = 0,
 993          },{
 994          .name = "bootEnv",
 995          .size = 0x00040000,
 996          .offset = 0x03EC0000,
 997          .mask_flags = 0,
 998          },{
 999          .name = "bootROM",
1000          .size = 0x00100000,
1001          .offset = 0x03F00000,
1002          .mask_flags = 0,
1003          }
1004 };
1005
1006 static int __init hdpu_setup_mtd(void)
1007 {
1008
1009         physmap_set_partitions(hdpu_partitions, 5);
1010         return 0;
1011 }
1012
1013 arch_initcall(hdpu_setup_mtd);
1014 #endif
1015
1016 #ifdef CONFIG_HDPU_FEATURES
1017
1018 static struct resource hdpu_cpustate_resources[] = {
1019         [0] = {
1020                .name = "addr base",
1021                .start = MV64x60_GPP_VALUE_SET,
1022                .end = MV64x60_GPP_VALUE_CLR + 1,
1023                .flags = IORESOURCE_MEM,
1024                },
1025 };
1026
1027 static struct resource hdpu_nexus_resources[] = {
1028         [0] = {
1029                .name = "nexus register",
1030                .start = HDPU_NEXUS_ID_BASE,
1031                .end = HDPU_NEXUS_ID_BASE + HDPU_NEXUS_ID_SIZE,
1032                .flags = IORESOURCE_MEM,
1033                },
1034 };
1035
1036 static struct platform_device hdpu_cpustate_device = {
1037         .name = HDPU_CPUSTATE_NAME,
1038         .id = 0,
1039         .num_resources = ARRAY_SIZE(hdpu_cpustate_resources),
1040         .resource = hdpu_cpustate_resources,
1041 };
1042
1043 static struct platform_device hdpu_nexus_device = {
1044         .name = HDPU_NEXUS_NAME,
1045         .id = 0,
1046         .num_resources = ARRAY_SIZE(hdpu_nexus_resources),
1047         .resource = hdpu_nexus_resources,
1048 };
1049
1050 static int __init hdpu_add_pds(void)
1051 {
1052         platform_device_register(&hdpu_cpustate_device);
1053         platform_device_register(&hdpu_nexus_device);
1054         return 0;
1055 }
1056
1057 arch_initcall(hdpu_add_pds);
1058 #endif