Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
[sfrench/cifs-2.6.git] / arch / ppc / platforms / hdpu.c
1 /*
2  * Board setup routines for the Sky Computers HDPU Compute Blade.
3  *
4  * Written by Brian Waite <waite@skycomputers.com>
5  *
6  * Based on code done by - Mark A. Greer <mgreer@mvista.com>
7  *                         Rabeeh Khoury - rabeeh@galileo.co.il
8  *
9  * This program is free software; you can redistribute  it and/or modify it
10  * under  the terms of  the GNU General  Public License as published by the
11  * Free Software Foundation;  either version 2 of the  License, or (at your
12  * option) any later version.
13  */
14
15 #include <linux/config.h>
16
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/irq.h>
20 #include <linux/ide.h>
21 #include <linux/seq_file.h>
22 #include <linux/platform_device.h>
23
24 #include <linux/initrd.h>
25 #include <linux/root_dev.h>
26 #include <linux/smp.h>
27
28 #include <asm/time.h>
29 #include <asm/machdep.h>
30 #include <asm/todc.h>
31 #include <asm/mv64x60.h>
32 #include <asm/ppcboot.h>
33 #include <platforms/hdpu.h>
34 #include <linux/mv643xx.h>
35 #include <linux/hdpu_features.h>
36 #include <linux/device.h>
37 #include <linux/mtd/physmap.h>
38
39 #define BOARD_VENDOR    "Sky Computers"
40 #define BOARD_MACHINE   "HDPU-CB-A"
41
42 bd_t ppcboot_bd;
43 int ppcboot_bd_valid = 0;
44
45 static mv64x60_handle_t bh;
46
47 extern char cmd_line[];
48
49 unsigned long hdpu_find_end_of_memory(void);
50 void hdpu_mpsc_progress(char *s, unsigned short hex);
51 void hdpu_heartbeat(void);
52
53 static void parse_bootinfo(unsigned long r3,
54                            unsigned long r4, unsigned long r5,
55                            unsigned long r6, unsigned long r7);
56 static void hdpu_set_l1pe(void);
57 static void hdpu_cpustate_set(unsigned char new_state);
58 #ifdef CONFIG_SMP
59 static DEFINE_SPINLOCK(timebase_lock);
60 static unsigned int timebase_upper = 0, timebase_lower = 0;
61 extern int smp_tb_synchronized;
62
63 void __devinit hdpu_tben_give(void);
64 void __devinit hdpu_tben_take(void);
65 #endif
66
67 static int __init
68 hdpu_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
69 {
70         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
71
72         if (hose->index == 0) {
73                 static char pci_irq_table[][4] = {
74                         {HDPU_PCI_0_IRQ, 0, 0, 0},
75                         {HDPU_PCI_0_IRQ, 0, 0, 0},
76                 };
77
78                 const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
79                 return PCI_IRQ_TABLE_LOOKUP;
80         } else {
81                 static char pci_irq_table[][4] = {
82                         {HDPU_PCI_1_IRQ, 0, 0, 0},
83                 };
84
85                 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
86                 return PCI_IRQ_TABLE_LOOKUP;
87         }
88 }
89
90 static void __init hdpu_intr_setup(void)
91 {
92         mv64x60_write(&bh, MV64x60_GPP_IO_CNTL,
93                       (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
94                        (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) |
95                        (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) |
96                        (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) |
97                        (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29)));
98
99         /* XXXX Erranum FEr PCI-#8 */
100         mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1 << 5) | (1 << 9));
101         mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1 << 5) | (1 << 9));
102
103         /*
104          * Dismiss and then enable interrupt on GPP interrupt cause
105          * for CPU #0
106          */
107         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~((1 << 8) | (1 << 13)));
108         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1 << 8) | (1 << 13));
109
110         /*
111          * Dismiss and then enable interrupt on CPU #0 high cause reg
112          * BIT25 summarizes GPP interrupts 8-15
113          */
114         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1 << 25));
115 }
116
117 static void __init hdpu_setup_peripherals(void)
118 {
119         unsigned int val;
120
121         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
122                                  HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
123         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
124
125         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
126                                  HDPU_TBEN_BASE, HDPU_TBEN_SIZE, 0);
127         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
128
129         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
130                                  HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE, 0);
131         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
132
133         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
134                                  HDPU_INTERNAL_SRAM_BASE,
135                                  HDPU_INTERNAL_SRAM_SIZE, 0);
136         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
137
138         bh.ci->disable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
139         mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, 0, 0, 0);
140
141         mv64x60_clr_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, (1 << 3));
142         mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
143         mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
144                          ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
145
146         /* Enable pipelining */
147         mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13));
148         /* Enable Snoop Pipelineing */
149         mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24));
150
151         /*
152          * Change DRAM read buffer assignment.
153          * Assign read buffer 0 dedicated only for CPU,
154          * and the rest read buffer 1.
155          */
156         val = mv64x60_read(&bh, MV64360_SDRAM_CONFIG);
157         val = val & 0x03ffffff;
158         val = val | 0xf8000000;
159         mv64x60_write(&bh, MV64360_SDRAM_CONFIG, val);
160
161         /*
162          * Configure internal SRAM -
163          * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set
164          * Parity enabled.
165          * Parity error propagation
166          * Arbitration not parked for CPU only
167          * Other bits are reserved.
168          */
169 #ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
170         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
171 #else
172         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
173 #endif
174
175         hdpu_intr_setup();
176 }
177
178 static void __init hdpu_setup_bridge(void)
179 {
180         struct mv64x60_setup_info si;
181         int i;
182
183         memset(&si, 0, sizeof(si));
184
185         si.phys_reg_base = HDPU_BRIDGE_REG_BASE;
186         si.pci_0.enable_bus = 1;
187         si.pci_0.pci_io.cpu_base = HDPU_PCI0_IO_START_PROC_ADDR;
188         si.pci_0.pci_io.pci_base_hi = 0;
189         si.pci_0.pci_io.pci_base_lo = HDPU_PCI0_IO_START_PCI_ADDR;
190         si.pci_0.pci_io.size = HDPU_PCI0_IO_SIZE;
191         si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
192         si.pci_0.pci_mem[0].cpu_base = HDPU_PCI0_MEM_START_PROC_ADDR;
193         si.pci_0.pci_mem[0].pci_base_hi = HDPU_PCI0_MEM_START_PCI_HI_ADDR;
194         si.pci_0.pci_mem[0].pci_base_lo = HDPU_PCI0_MEM_START_PCI_LO_ADDR;
195         si.pci_0.pci_mem[0].size = HDPU_PCI0_MEM_SIZE;
196         si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
197         si.pci_0.pci_cmd_bits = 0;
198         si.pci_0.latency_timer = 0x80;
199
200         si.pci_1.enable_bus = 1;
201         si.pci_1.pci_io.cpu_base = HDPU_PCI1_IO_START_PROC_ADDR;
202         si.pci_1.pci_io.pci_base_hi = 0;
203         si.pci_1.pci_io.pci_base_lo = HDPU_PCI1_IO_START_PCI_ADDR;
204         si.pci_1.pci_io.size = HDPU_PCI1_IO_SIZE;
205         si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
206         si.pci_1.pci_mem[0].cpu_base = HDPU_PCI1_MEM_START_PROC_ADDR;
207         si.pci_1.pci_mem[0].pci_base_hi = HDPU_PCI1_MEM_START_PCI_HI_ADDR;
208         si.pci_1.pci_mem[0].pci_base_lo = HDPU_PCI1_MEM_START_PCI_LO_ADDR;
209         si.pci_1.pci_mem[0].size = HDPU_PCI1_MEM_SIZE;
210         si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
211         si.pci_1.pci_cmd_bits = 0;
212         si.pci_1.latency_timer = 0x80;
213
214         for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
215 #if defined(CONFIG_NOT_COHERENT_CACHE)
216                 si.cpu_prot_options[i] = 0;
217                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
218                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
219                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
220
221                 si.pci_1.acc_cntl_options[i] =
222                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
223                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
224                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
225                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
226
227                 si.pci_0.acc_cntl_options[i] =
228                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
229                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
230                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
231                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
232
233 #else
234                 si.cpu_prot_options[i] = 0;
235                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; /* errata */
236                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; /* errata */
237                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; /* errata */
238
239                 si.pci_0.acc_cntl_options[i] =
240                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
241                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
242                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
243                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
244
245                 si.pci_1.acc_cntl_options[i] =
246                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
247                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
248                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
249                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
250 #endif
251         }
252
253         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI);
254
255         /* Lookup PCI host bridges */
256         mv64x60_init(&bh, &si);
257         pci_dram_offset = 0;    /* System mem at same addr on PCI & cpu bus */
258         ppc_md.pci_swizzle = common_swizzle;
259         ppc_md.pci_map_irq = hdpu_map_irq;
260
261         mv64x60_set_bus(&bh, 0, 0);
262         bh.hose_a->first_busno = 0;
263         bh.hose_a->last_busno = 0xff;
264         bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
265
266         bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
267         mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
268         bh.hose_b->last_busno = 0xff;
269         bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
270                 bh.hose_b->first_busno);
271
272         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
273
274         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
275         /*
276          * Enabling of PCI internal-vs-external arbitration
277          * is a platform- and errata-dependent decision.
278          */
279         return;
280 }
281
282 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
283 static void __init hdpu_early_serial_map(void)
284 {
285 #ifdef  CONFIG_KGDB
286         static char first_time = 1;
287
288 #if defined(CONFIG_KGDB_TTYS0)
289 #define KGDB_PORT 0
290 #elif defined(CONFIG_KGDB_TTYS1)
291 #define KGDB_PORT 1
292 #else
293 #error "Invalid kgdb_tty port"
294 #endif
295
296         if (first_time) {
297                 gt_early_mpsc_init(KGDB_PORT,
298                                    B9600 | CS8 | CREAD | HUPCL | CLOCAL);
299                 first_time = 0;
300         }
301
302         return;
303 #endif
304 }
305 #endif
306
307 static void hdpu_init2(void)
308 {
309         return;
310 }
311
312 #if defined(CONFIG_MV643XX_ETH)
313 static void __init hdpu_fixup_eth_pdata(struct platform_device *pd)
314 {
315
316         struct mv643xx_eth_platform_data *eth_pd;
317         eth_pd = pd->dev.platform_data;
318
319         eth_pd->force_phy_addr = 1;
320         eth_pd->phy_addr = pd->id;
321         eth_pd->speed = SPEED_100;
322         eth_pd->duplex = DUPLEX_FULL;
323         eth_pd->tx_queue_size = 400;
324         eth_pd->rx_queue_size = 800;
325 }
326 #endif
327
328 static void __init hdpu_fixup_mpsc_pdata(struct platform_device *pd)
329 {
330
331         struct mpsc_pdata *pdata;
332
333         pdata = (struct mpsc_pdata *)pd->dev.platform_data;
334
335         pdata->max_idle = 40;
336         if (ppcboot_bd_valid)
337                 pdata->default_baud = ppcboot_bd.bi_baudrate;
338         else
339                 pdata->default_baud = HDPU_DEFAULT_BAUD;
340         pdata->brg_clk_src = HDPU_MPSC_CLK_SRC;
341         pdata->brg_clk_freq = HDPU_MPSC_CLK_FREQ;
342 }
343
344 #if defined(CONFIG_HDPU_FEATURES)
345 static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd)
346 {
347         struct platform_device *pds[1];
348         pds[0] = pd;
349         mv64x60_pd_fixup(&bh, pds, 1);
350 }
351 #endif
352
353 static int hdpu_platform_notify(struct device *dev)
354 {
355         static struct {
356                 char *bus_id;
357                 void ((*rtn) (struct platform_device * pdev));
358         } dev_map[] = {
359                 {
360                 MPSC_CTLR_NAME ".0", hdpu_fixup_mpsc_pdata},
361 #if defined(CONFIG_MV643XX_ETH)
362                 {
363                 MV643XX_ETH_NAME ".0", hdpu_fixup_eth_pdata},
364 #endif
365 #if defined(CONFIG_HDPU_FEATURES)
366                 {
367                 HDPU_CPUSTATE_NAME ".0", hdpu_fixup_cpustate_pdata},
368 #endif
369         };
370         struct platform_device *pdev;
371         int i;
372
373         if (dev && dev->bus_id)
374                 for (i = 0; i < ARRAY_SIZE(dev_map); i++)
375                         if (!strncmp(dev->bus_id, dev_map[i].bus_id,
376                                      BUS_ID_SIZE)) {
377
378                                 pdev = container_of(dev,
379                                                     struct platform_device,
380                                                     dev);
381                                 dev_map[i].rtn(pdev);
382                         }
383
384         return 0;
385 }
386
387 static void __init hdpu_setup_arch(void)
388 {
389         if (ppc_md.progress)
390                 ppc_md.progress("hdpu_setup_arch: enter", 0);
391 #ifdef CONFIG_BLK_DEV_INITRD
392         if (initrd_start)
393                 ROOT_DEV = Root_RAM0;
394         else
395 #endif
396 #ifdef  CONFIG_ROOT_NFS
397                 ROOT_DEV = Root_NFS;
398 #else
399                 ROOT_DEV = Root_SDA2;
400 #endif
401
402         ppc_md.heartbeat = hdpu_heartbeat;
403
404         ppc_md.heartbeat_reset = HZ;
405         ppc_md.heartbeat_count = 1;
406
407         if (ppc_md.progress)
408                 ppc_md.progress("hdpu_setup_arch: Enabling L2 cache", 0);
409
410         /* Enable L1 Parity Bits */
411         hdpu_set_l1pe();
412
413         /* Enable L2 and L3 caches (if 745x) */
414         _set_L2CR(0x80080000);
415
416         if (ppc_md.progress)
417                 ppc_md.progress("hdpu_setup_arch: enter", 0);
418
419         hdpu_setup_bridge();
420
421         hdpu_setup_peripherals();
422
423 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
424         hdpu_early_serial_map();
425 #endif
426
427         printk("SKY HDPU Compute Blade \n");
428
429         if (ppc_md.progress)
430                 ppc_md.progress("hdpu_setup_arch: exit", 0);
431
432         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_OK);
433         return;
434 }
435 static void __init hdpu_init_irq(void)
436 {
437         mv64360_init_irq();
438 }
439
440 static void __init hdpu_set_l1pe()
441 {
442         unsigned long ictrl;
443         asm volatile ("mfspr %0, 1011":"=r" (ictrl):);
444         ictrl |= ICTRL_EICE | ICTRL_EDC | ICTRL_EICP;
445         asm volatile ("mtspr 1011, %0"::"r" (ictrl));
446 }
447
448 /*
449  * Set BAT 1 to map 0xf1000000 to end of physical memory space.
450  */
451 static __inline__ void hdpu_set_bat(void)
452 {
453         mb();
454         mtspr(SPRN_DBAT1U, 0xf10001fe);
455         mtspr(SPRN_DBAT1L, 0xf100002a);
456         mb();
457
458         return;
459 }
460
461 unsigned long __init hdpu_find_end_of_memory(void)
462 {
463         return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
464                                     MV64x60_TYPE_MV64360);
465 }
466
467 static void hdpu_reset_board(void)
468 {
469         volatile int infinite = 1;
470
471         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_RESET);
472
473         local_irq_disable();
474
475         /* Clear all the LEDs */
476         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) |
477                                                    (1 << 5) | (1 << 6)));
478
479         /* disable and invalidate the L2 cache */
480         _set_L2CR(0);
481         _set_L2CR(0x200000);
482
483         /* flush and disable L1 I/D cache */
484         __asm__ __volatile__
485             ("\n"
486              "mfspr   3,1008\n"
487              "ori       5,5,0xcc00\n"
488              "ori       4,3,0xc00\n"
489              "andc      5,3,5\n"
490              "sync\n"
491              "mtspr     1008,4\n"
492              "isync\n" "sync\n" "mtspr  1008,5\n" "isync\n" "sync\n");
493
494         /* Hit the reset bit */
495         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 3));
496
497         while (infinite)
498                 infinite = infinite;
499
500         return;
501 }
502
503 static void hdpu_restart(char *cmd)
504 {
505         volatile ulong i = 10000000;
506
507         hdpu_reset_board();
508
509         while (i-- > 0) ;
510         panic("restart failed\n");
511 }
512
513 static void hdpu_halt(void)
514 {
515         local_irq_disable();
516
517         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_HALT);
518
519         /* Clear all the LEDs */
520         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) | (1 << 5) |
521                                                    (1 << 6)));
522         while (1) ;
523         /* NOTREACHED */
524 }
525
526 static void hdpu_power_off(void)
527 {
528         hdpu_halt();
529         /* NOTREACHED */
530 }
531
532 static int hdpu_show_cpuinfo(struct seq_file *m)
533 {
534         uint pvid;
535
536         pvid = mfspr(SPRN_PVR);
537         seq_printf(m, "vendor\t\t: Sky Computers\n");
538         seq_printf(m, "machine\t\t: HDPU Compute Blade\n");
539         seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
540                    pvid, (pvid & (1 << 15) ? "IBM" : "Motorola"));
541
542         return 0;
543 }
544
545 static void __init hdpu_calibrate_decr(void)
546 {
547         ulong freq;
548
549         if (ppcboot_bd_valid)
550                 freq = ppcboot_bd.bi_busfreq / 4;
551         else
552                 freq = 133000000;
553
554         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
555                freq / 1000000, freq % 1000000);
556
557         tb_ticks_per_jiffy = freq / HZ;
558         tb_to_us = mulhwu_scale_factor(freq, 1000000);
559
560         return;
561 }
562
563 static void parse_bootinfo(unsigned long r3,
564                            unsigned long r4, unsigned long r5,
565                            unsigned long r6, unsigned long r7)
566 {
567         bd_t *bd = NULL;
568         char *cmdline_start = NULL;
569         int cmdline_len = 0;
570
571         if (r3) {
572                 if ((r3 & 0xf0000000) == 0)
573                         r3 += KERNELBASE;
574                 if ((r3 & 0xf0000000) == KERNELBASE) {
575                         bd = (void *)r3;
576
577                         memcpy(&ppcboot_bd, bd, sizeof(ppcboot_bd));
578                         ppcboot_bd_valid = 1;
579                 }
580         }
581 #ifdef CONFIG_BLK_DEV_INITRD
582         if (r4 && r5 && r5 > r4) {
583                 if ((r4 & 0xf0000000) == 0)
584                         r4 += KERNELBASE;
585                 if ((r5 & 0xf0000000) == 0)
586                         r5 += KERNELBASE;
587                 if ((r4 & 0xf0000000) == KERNELBASE) {
588                         initrd_start = r4;
589                         initrd_end = r5;
590                         initrd_below_start_ok = 1;
591                 }
592         }
593 #endif                          /* CONFIG_BLK_DEV_INITRD */
594
595         if (r6 && r7 && r7 > r6) {
596                 if ((r6 & 0xf0000000) == 0)
597                         r6 += KERNELBASE;
598                 if ((r7 & 0xf0000000) == 0)
599                         r7 += KERNELBASE;
600                 if ((r6 & 0xf0000000) == KERNELBASE) {
601                         cmdline_start = (void *)r6;
602                         cmdline_len = (r7 - r6);
603                         strncpy(cmd_line, cmdline_start, cmdline_len);
604                 }
605         }
606 }
607
608 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
609 static void
610 hdpu_ide_request_region(ide_ioreg_t from, unsigned int extent, const char *name)
611 {
612         request_region(from, extent, name);
613         return;
614 }
615
616 static void hdpu_ide_release_region(ide_ioreg_t from, unsigned int extent)
617 {
618         release_region(from, extent);
619         return;
620 }
621
622 static void __init
623 hdpu_ide_pci_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
624                              ide_ioreg_t ctrl_port, int *irq)
625 {
626         struct pci_dev *dev;
627
628         pci_for_each_dev(dev) {
629                 if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) ||
630                     ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)) {
631                         hw->irq = dev->irq;
632
633                         if (irq != NULL) {
634                                 *irq = dev->irq;
635                         }
636                 }
637         }
638
639         return;
640 }
641 #endif
642
643 void hdpu_heartbeat(void)
644 {
645         if (mv64x60_read(&bh, MV64x60_GPP_VALUE) & (1 << 5))
646                 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 5));
647         else
648                 mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, (1 << 5));
649
650         ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
651
652 }
653
654 static void __init hdpu_map_io(void)
655 {
656         io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO);
657 }
658
659 #ifdef CONFIG_SMP
660 char hdpu_smp0[] = "SMP Cpu #0";
661 char hdpu_smp1[] = "SMP Cpu #1";
662
663 static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id,
664                                              struct pt_regs *regs)
665 {
666         volatile unsigned int doorbell;
667
668         doorbell = mv64x60_read(&bh, MV64360_CPU0_DOORBELL);
669
670         /* Ack the doorbell interrupts */
671         mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, doorbell);
672
673         if (doorbell & 1) {
674                 smp_message_recv(0, regs);
675         }
676         if (doorbell & 2) {
677                 smp_message_recv(1, regs);
678         }
679         if (doorbell & 4) {
680                 smp_message_recv(2, regs);
681         }
682         if (doorbell & 8) {
683                 smp_message_recv(3, regs);
684         }
685         return IRQ_HANDLED;
686 }
687
688 static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id,
689                                              struct pt_regs *regs)
690 {
691         volatile unsigned int doorbell;
692
693         doorbell = mv64x60_read(&bh, MV64360_CPU1_DOORBELL);
694
695         /* Ack the doorbell interrupts */
696         mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, doorbell);
697
698         if (doorbell & 1) {
699                 smp_message_recv(0, regs);
700         }
701         if (doorbell & 2) {
702                 smp_message_recv(1, regs);
703         }
704         if (doorbell & 4) {
705                 smp_message_recv(2, regs);
706         }
707         if (doorbell & 8) {
708                 smp_message_recv(3, regs);
709         }
710         return IRQ_HANDLED;
711 }
712
713 static void smp_hdpu_CPU_two(void)
714 {
715         __asm__ __volatile__
716             ("\n"
717              "lis     3,0x0000\n"
718              "ori     3,3,0x00c0\n"
719              "mtspr   26, 3\n" "li      4,0\n" "mtspr   27,4\n" "rfi");
720
721 }
722
723 static int smp_hdpu_probe(void)
724 {
725         int *cpu_count_reg;
726         int num_cpus = 0;
727
728         cpu_count_reg = ioremap(HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE);
729         if (cpu_count_reg) {
730                 num_cpus = (*cpu_count_reg >> 20) & 0x3;
731                 iounmap(cpu_count_reg);
732         }
733
734         /* Validate the bits in the CPLD. If we could not map the reg, return 2.
735          * If the register reported 0 or 3, return 2.
736          * Older CPLD revisions set these bits to all ones (val = 3).
737          */
738         if ((num_cpus < 1) || (num_cpus > 2)) {
739                 printk
740                     ("Unable to determine the number of processors %d . deafulting to 2.\n",
741                      num_cpus);
742                 num_cpus = 2;
743         }
744         return num_cpus;
745 }
746
747 static void
748 smp_hdpu_message_pass(int target, int msg)
749 {
750         if (msg > 0x3) {
751                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
752                        smp_processor_id(), msg);
753                 return;
754         }
755         switch (target) {
756         case MSG_ALL:
757                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
758                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
759                 break;
760         case MSG_ALL_BUT_SELF:
761                 if (smp_processor_id())
762                         mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
763                 else
764                         mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
765                 break;
766         default:
767                 if (target == 0)
768                         mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
769                 else
770                         mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
771                 break;
772         }
773 }
774
775 static void smp_hdpu_kick_cpu(int nr)
776 {
777         volatile unsigned int *bootaddr;
778
779         if (ppc_md.progress)
780                 ppc_md.progress("smp_hdpu_kick_cpu", 0);
781
782         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_CPU1_KICK);
783
784        /* Disable BootCS. Must also reduce the windows size to zero. */
785         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
786         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 0, 0, 0);
787
788         bootaddr = ioremap(HDPU_INTERNAL_SRAM_BASE, HDPU_INTERNAL_SRAM_SIZE);
789         if (!bootaddr) {
790                 if (ppc_md.progress)
791                         ppc_md.progress("smp_hdpu_kick_cpu: ioremap failed", 0);
792                 return;
793         }
794
795         memcpy((void *)(bootaddr + 0x40), (void *)&smp_hdpu_CPU_two, 0x20);
796
797         /* map SRAM to 0xfff00000 */
798         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
799
800         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
801                                  0xfff00000, HDPU_INTERNAL_SRAM_SIZE, 0);
802         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
803
804         /* Enable CPU1 arbitration */
805         mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1 << 9));
806
807         /*
808          * Wait 100mSecond until other CPU has reached __secondary_start.
809          * When it reaches, it is permittable to rever the SRAM mapping etc...
810          */
811         mdelay(100);
812         *(unsigned long *)KERNELBASE = nr;
813         asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
814
815         iounmap(bootaddr);
816
817         /* Set up window for internal sram (256KByte insize) */
818         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
819         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
820                                  HDPU_INTERNAL_SRAM_BASE,
821                                  HDPU_INTERNAL_SRAM_SIZE, 0);
822         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
823         /*
824          * Set up windows for embedded FLASH (using boot CS window).
825          */
826
827         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
828         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
829                                  HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
830         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
831 }
832
833 static void smp_hdpu_setup_cpu(int cpu_nr)
834 {
835         if (cpu_nr == 0) {
836                 if (ppc_md.progress)
837                         ppc_md.progress("smp_hdpu_setup_cpu 0", 0);
838                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff);
839                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff);
840                 request_irq(60, hdpu_smp_cpu0_int_handler,
841                             SA_INTERRUPT, hdpu_smp0, 0);
842         }
843
844         if (cpu_nr == 1) {
845                 if (ppc_md.progress)
846                         ppc_md.progress("smp_hdpu_setup_cpu 1", 0);
847
848                 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR |
849                                   CPUSTATE_KERNEL_CPU1_OK);
850
851                 /* Enable L1 Parity Bits */
852                 hdpu_set_l1pe();
853
854                 /* Enable L2 cache */
855                 _set_L2CR(0);
856                 _set_L2CR(0x80080000);
857
858                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0);
859                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff);
860                 request_irq(28, hdpu_smp_cpu1_int_handler,
861                             SA_INTERRUPT, hdpu_smp1, 0);
862         }
863
864 }
865
866 void __devinit hdpu_tben_give()
867 {
868         volatile unsigned long *val = 0;
869
870         /* By writing 0 to the TBEN_BASE, the timebases is frozen */
871         val = ioremap(HDPU_TBEN_BASE, 4);
872         *val = 0;
873         mb();
874
875         spin_lock(&timebase_lock);
876         timebase_upper = get_tbu();
877         timebase_lower = get_tbl();
878         spin_unlock(&timebase_lock);
879
880         while (timebase_upper || timebase_lower)
881                 barrier();
882
883         /* By writing 1 to the TBEN_BASE, the timebases is thawed */
884         *val = 1;
885         mb();
886
887         iounmap(val);
888
889 }
890
891 void __devinit hdpu_tben_take()
892 {
893         while (!(timebase_upper || timebase_lower))
894                 barrier();
895
896         spin_lock(&timebase_lock);
897         set_tb(timebase_upper, timebase_lower);
898         timebase_upper = 0;
899         timebase_lower = 0;
900         spin_unlock(&timebase_lock);
901 }
902
903 static struct smp_ops_t hdpu_smp_ops = {
904         .message_pass = smp_hdpu_message_pass,
905         .probe = smp_hdpu_probe,
906         .kick_cpu = smp_hdpu_kick_cpu,
907         .setup_cpu = smp_hdpu_setup_cpu,
908         .give_timebase = hdpu_tben_give,
909         .take_timebase = hdpu_tben_take,
910 };
911 #endif                          /* CONFIG_SMP */
912
913 void __init
914 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
915               unsigned long r6, unsigned long r7)
916 {
917         parse_bootinfo(r3, r4, r5, r6, r7);
918
919         isa_mem_base = 0;
920
921         ppc_md.setup_arch = hdpu_setup_arch;
922         ppc_md.init = hdpu_init2;
923         ppc_md.show_cpuinfo = hdpu_show_cpuinfo;
924         ppc_md.init_IRQ = hdpu_init_irq;
925         ppc_md.get_irq = mv64360_get_irq;
926         ppc_md.restart = hdpu_restart;
927         ppc_md.power_off = hdpu_power_off;
928         ppc_md.halt = hdpu_halt;
929         ppc_md.find_end_of_memory = hdpu_find_end_of_memory;
930         ppc_md.calibrate_decr = hdpu_calibrate_decr;
931         ppc_md.setup_io_mappings = hdpu_map_io;
932
933         bh.p_base = CONFIG_MV64X60_NEW_BASE;
934         bh.v_base = (unsigned long *)bh.p_base;
935
936         hdpu_set_bat();
937
938 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
939         ppc_md.progress = hdpu_mpsc_progress;   /* embedded UART */
940         mv64x60_progress_init(bh.p_base);
941 #endif                          /* CONFIG_SERIAL_TEXT_DEBUG */
942
943 #ifdef CONFIG_SMP
944         smp_ops = &hdpu_smp_ops;
945 #endif                          /* CONFIG_SMP */
946
947 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
948         platform_notify = hdpu_platform_notify;
949 #endif
950         return;
951 }
952
953 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
954 /* SMP safe version of the serial text debug routine. Uses Semaphore 0 */
955 void hdpu_mpsc_progress(char *s, unsigned short hex)
956 {
957         while (mv64x60_read(&bh, MV64360_WHO_AM_I) !=
958                mv64x60_read(&bh, MV64360_SEMAPHORE_0)) {
959         }
960         mv64x60_mpsc_progress(s, hex);
961         mv64x60_write(&bh, MV64360_SEMAPHORE_0, 0xff);
962 }
963 #endif
964
965 static void hdpu_cpustate_set(unsigned char new_state)
966 {
967         unsigned int state = (new_state << 21);
968         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (0xff << 21));
969         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, state);
970 }
971
972 #ifdef CONFIG_MTD_PHYSMAP
973 static struct mtd_partition hdpu_partitions[] = {
974         {
975          .name = "Root FS",
976          .size = 0x03400000,
977          .offset = 0,
978          .mask_flags = 0,
979          },{
980          .name = "User FS",
981          .size = 0x00800000,
982          .offset = 0x03400000,
983          .mask_flags = 0,
984          },{
985          .name = "Kernel Image",
986          .size = 0x002C0000,
987          .offset = 0x03C00000,
988          .mask_flags = 0,
989          },{
990          .name = "bootEnv",
991          .size = 0x00040000,
992          .offset = 0x03EC0000,
993          .mask_flags = 0,
994          },{
995          .name = "bootROM",
996          .size = 0x00100000,
997          .offset = 0x03F00000,
998          .mask_flags = 0,
999          }
1000 };
1001
1002 static int __init hdpu_setup_mtd(void)
1003 {
1004
1005         physmap_set_partitions(hdpu_partitions, 5);
1006         return 0;
1007 }
1008
1009 arch_initcall(hdpu_setup_mtd);
1010 #endif
1011
1012 #ifdef CONFIG_HDPU_FEATURES
1013
1014 static struct resource hdpu_cpustate_resources[] = {
1015         [0] = {
1016                .name = "addr base",
1017                .start = MV64x60_GPP_VALUE_SET,
1018                .end = MV64x60_GPP_VALUE_CLR + 1,
1019                .flags = IORESOURCE_MEM,
1020                },
1021 };
1022
1023 static struct resource hdpu_nexus_resources[] = {
1024         [0] = {
1025                .name = "nexus register",
1026                .start = HDPU_NEXUS_ID_BASE,
1027                .end = HDPU_NEXUS_ID_BASE + HDPU_NEXUS_ID_SIZE,
1028                .flags = IORESOURCE_MEM,
1029                },
1030 };
1031
1032 static struct platform_device hdpu_cpustate_device = {
1033         .name = HDPU_CPUSTATE_NAME,
1034         .id = 0,
1035         .num_resources = ARRAY_SIZE(hdpu_cpustate_resources),
1036         .resource = hdpu_cpustate_resources,
1037 };
1038
1039 static struct platform_device hdpu_nexus_device = {
1040         .name = HDPU_NEXUS_NAME,
1041         .id = 0,
1042         .num_resources = ARRAY_SIZE(hdpu_nexus_resources),
1043         .resource = hdpu_nexus_resources,
1044 };
1045
1046 static int __init hdpu_add_pds(void)
1047 {
1048         platform_device_register(&hdpu_cpustate_device);
1049         platform_device_register(&hdpu_nexus_device);
1050         return 0;
1051 }
1052
1053 arch_initcall(hdpu_add_pds);
1054 #endif