arch/ppc/platforms/4xx/ibm440gx.c

   1 /*
   2  * arch/ppc/platforms/4xx/ibm440gx.c
   3  *
   4  * PPC440GX I/O descriptions
   5  *
   6  * Matt Porter <mporter@mvista.com>
   7  * Copyright 2002-2004 MontaVista Software Inc.
   8  *
   9  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  10  * Copyright (c) 2003, 2004 Zultys Technologies
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <platforms/4xx/ibm440gx.h>
  21 #include <asm/ocp.h>
  22 #include <asm/ppc4xx_pic.h>
  23
  24 static struct ocp_func_emac_data ibm440gx_emac0_def = {
  25         .rgmii_idx      = -1,           /* No RGMII */
  26         .rgmii_mux      = -1,           /* No RGMII */
  27         .zmii_idx       = 0,            /* ZMII device index */
  28         .zmii_mux       = 0,            /* ZMII input of this EMAC */
  29         .mal_idx        = 0,            /* MAL device index */
  30         .mal_rx_chan    = 0,            /* MAL rx channel number */
  31         .mal_tx_chan    = 0,            /* MAL tx channel number */
  32         .wol_irq        = 61,           /* WOL interrupt number */
  33         .mdio_idx       = -1,           /* No shared MDIO */
  34         .tah_idx        = -1,           /* No TAH */
  35 };
  36
  37 static struct ocp_func_emac_data ibm440gx_emac1_def = {
  38         .rgmii_idx      = -1,           /* No RGMII */
  39         .rgmii_mux      = -1,           /* No RGMII */
  40         .zmii_idx       = 0,            /* ZMII device index */
  41         .zmii_mux       = 1,            /* ZMII input of this EMAC */
  42         .mal_idx        = 0,            /* MAL device index */
  43         .mal_rx_chan    = 1,            /* MAL rx channel number */
  44         .mal_tx_chan    = 1,            /* MAL tx channel number */
  45         .wol_irq        = 63,           /* WOL interrupt number */
  46         .mdio_idx       = -1,           /* No shared MDIO */
  47         .tah_idx        = -1,           /* No TAH */
  48 };
  49
  50 static struct ocp_func_emac_data ibm440gx_emac2_def = {
  51         .rgmii_idx      = 0,            /* RGMII device index */
  52         .rgmii_mux      = 0,            /* RGMII input of this EMAC */
  53         .zmii_idx       = 0,            /* ZMII device index */
  54         .zmii_mux       = 2,            /* ZMII input of this EMAC */
  55         .mal_idx        = 0,            /* MAL device index */
  56         .mal_rx_chan    = 2,            /* MAL rx channel number */
  57         .mal_tx_chan    = 2,            /* MAL tx channel number */
  58         .wol_irq        = 65,           /* WOL interrupt number */
  59         .mdio_idx       = -1,           /* No shared MDIO */
  60         .tah_idx        = 0,            /* TAH device index */
  61         .jumbo          = 1,            /* Jumbo frames supported */
  62 };
  63
  64 static struct ocp_func_emac_data ibm440gx_emac3_def = {
  65         .rgmii_idx      = 0,            /* RGMII device index */
  66         .rgmii_mux      = 1,            /* RGMII input of this EMAC */
  67         .zmii_idx       = 0,            /* ZMII device index */
  68         .zmii_mux       = 3,            /* ZMII input of this EMAC */
  69         .mal_idx        = 0,            /* MAL device index */
  70         .mal_rx_chan    = 3,            /* MAL rx channel number */
  71         .mal_tx_chan    = 3,            /* MAL tx channel number */
  72         .wol_irq        = 67,           /* WOL interrupt number */
  73         .mdio_idx       = -1,           /* No shared MDIO */
  74         .tah_idx        = 1,            /* TAH device index */
  75         .jumbo          = 1,            /* Jumbo frames supported */
  76 };
  77 OCP_SYSFS_EMAC_DATA()
  78
  79 static struct ocp_func_mal_data ibm440gx_mal0_def = {
  80         .num_tx_chans   = 4,            /* Number of TX channels */
  81         .num_rx_chans   = 4,            /* Number of RX channels */
  82         .txeob_irq      = 10,           /* TX End Of Buffer IRQ  */
  83         .rxeob_irq      = 11,           /* RX End Of Buffer IRQ  */
  84         .txde_irq       = 33,           /* TX Descriptor Error IRQ */
  85         .rxde_irq       = 34,           /* RX Descriptor Error IRQ */
  86         .serr_irq       = 32,           /* MAL System Error IRQ    */
  87         .dcr_base       = DCRN_MAL_BASE /* MAL0_CFG DCR number */
  88 };
  89 OCP_SYSFS_MAL_DATA()
  90
  91 static struct ocp_func_iic_data ibm440gx_iic0_def = {
  92         .fast_mode      = 0,            /* Use standad mode (100Khz) */
  93 };
  94
  95 static struct ocp_func_iic_data ibm440gx_iic1_def = {
  96         .fast_mode      = 0,            /* Use standad mode (100Khz) */
  97 };
  98 OCP_SYSFS_IIC_DATA()
  99
 100 struct ocp_def core_ocp[] = {
 101         { .vendor       = OCP_VENDOR_IBM,
 102           .function     = OCP_FUNC_OPB,
 103           .index        = 0,
 104           .paddr        = 0x0000000140000000ULL,
 105           .irq          = OCP_IRQ_NA,
 106           .pm           = OCP_CPM_NA,
 107         },
 108         { .vendor       = OCP_VENDOR_IBM,
 109           .function     = OCP_FUNC_16550,
 110           .index        = 0,
 111           .paddr        = PPC440GX_UART0_ADDR,
 112           .irq          = UART0_INT,
 113           .pm           = IBM_CPM_UART0,
 114         },
 115         { .vendor       = OCP_VENDOR_IBM,
 116           .function     = OCP_FUNC_16550,
 117           .index        = 1,
 118           .paddr        = PPC440GX_UART1_ADDR,
 119           .irq          = UART1_INT,
 120           .pm           = IBM_CPM_UART1,
 121         },
 122         { .vendor       = OCP_VENDOR_IBM,
 123           .function     = OCP_FUNC_IIC,
 124           .index        = 0,
 125           .paddr        = 0x0000000140000400ULL,
 126           .irq          = 2,
 127           .pm           = IBM_CPM_IIC0,
 128           .additions    = &ibm440gx_iic0_def,
 129           .show         = &ocp_show_iic_data
 130         },
 131         { .vendor       = OCP_VENDOR_IBM,
 132           .function     = OCP_FUNC_IIC,
 133           .index        = 1,
 134           .paddr        = 0x0000000140000500ULL,
 135           .irq          = 3,
 136           .pm           = IBM_CPM_IIC1,
 137           .additions    = &ibm440gx_iic1_def,
 138           .show         = &ocp_show_iic_data
 139         },
 140         { .vendor       = OCP_VENDOR_IBM,
 141           .function     = OCP_FUNC_GPIO,
 142           .index        = 0,
 143           .paddr        = 0x0000000140000700ULL,
 144           .irq          = OCP_IRQ_NA,
 145           .pm           = IBM_CPM_GPIO0,
 146         },
 147         { .vendor       = OCP_VENDOR_IBM,
 148           .function     = OCP_FUNC_MAL,
 149           .paddr        = OCP_PADDR_NA,
 150           .irq          = OCP_IRQ_NA,
 151           .pm           = OCP_CPM_NA,
 152           .additions    = &ibm440gx_mal0_def,
 153           .show         = &ocp_show_mal_data,
 154         },
 155         { .vendor       = OCP_VENDOR_IBM,
 156           .function     = OCP_FUNC_EMAC,
 157           .index        = 0,
 158           .paddr        = 0x0000000140000800ULL,
 159           .irq          = 60,
 160           .pm           = OCP_CPM_NA,
 161           .additions    = &ibm440gx_emac0_def,
 162           .show         = &ocp_show_emac_data,
 163         },
 164         { .vendor       = OCP_VENDOR_IBM,
 165           .function     = OCP_FUNC_EMAC,
 166           .index        = 1,
 167           .paddr        = 0x0000000140000900ULL,
 168           .irq          = 62,
 169           .pm           = OCP_CPM_NA,
 170           .additions    = &ibm440gx_emac1_def,
 171           .show         = &ocp_show_emac_data,
 172         },
 173         { .vendor       = OCP_VENDOR_IBM,
 174           .function     = OCP_FUNC_EMAC,
 175           .index        = 2,
 176           .paddr        = 0x0000000140000C00ULL,
 177           .irq          = 64,
 178           .pm           = OCP_CPM_NA,
 179           .additions    = &ibm440gx_emac2_def,
 180           .show         = &ocp_show_emac_data,
 181         },
 182         { .vendor       = OCP_VENDOR_IBM,
 183           .function     = OCP_FUNC_EMAC,
 184           .index        = 3,
 185           .paddr        = 0x0000000140000E00ULL,
 186           .irq          = 66,
 187           .pm           = OCP_CPM_NA,
 188           .additions    = &ibm440gx_emac3_def,
 189           .show         = &ocp_show_emac_data,
 190         },
 191         { .vendor       = OCP_VENDOR_IBM,
 192           .function     = OCP_FUNC_RGMII,
 193           .paddr        = 0x0000000140000790ULL,
 194           .irq          = OCP_IRQ_NA,
 195           .pm           = OCP_CPM_NA,
 196         },
 197         { .vendor       = OCP_VENDOR_IBM,
 198           .function     = OCP_FUNC_ZMII,
 199           .paddr        = 0x0000000140000780ULL,
 200           .irq          = OCP_IRQ_NA,
 201           .pm           = OCP_CPM_NA,
 202         },
 203         { .vendor       = OCP_VENDOR_IBM,
 204           .function     = OCP_FUNC_TAH,
 205           .index        = 0,
 206           .paddr        = 0x0000000140000b50ULL,
 207           .irq          = 68,
 208           .pm           = OCP_CPM_NA,
 209         },
 210         { .vendor       = OCP_VENDOR_IBM,
 211           .function     = OCP_FUNC_TAH,
 212           .index        = 1,
 213           .paddr        = 0x0000000140000d50ULL,
 214           .irq          = 69,
 215           .pm           = OCP_CPM_NA,
 216         },
 217         { .vendor       = OCP_VENDOR_INVALID
 218         }
 219 };
 220
 221 /* Polarity and triggering settings for internal interrupt sources */
 222 struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
 223         { .polarity     = 0xfffffe03,
 224           .triggering   = 0x01c00000,
 225           .ext_irq_mask = 0x000001fc,   /* IRQ0 - IRQ6 */
 226         },
 227         { .polarity     = 0xffffc0ff,
 228           .triggering   = 0x00ff8000,
 229           .ext_irq_mask = 0x00003f00,   /* IRQ7 - IRQ12 */
 230         },
 231         { .polarity     = 0xffff83ff,
 232           .triggering   = 0x000f83c0,
 233           .ext_irq_mask = 0x00007c00,   /* IRQ13 - IRQ17 */
 234         },
 235 };