2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
15 #include <linux/irq.h>
16 #include <linux/bootmem.h>
17 #include <linux/msi.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/of_platform.h>
21 #include <sysdev/fsl_soc.h>
23 #include <asm/hw_irq.h>
24 #include <asm/ppc-pci.h>
27 struct fsl_msi_feature {
33 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
35 return in_be32(base + (reg >> 2));
39 * We do not need this actually. The MSIR register has been read once
40 * in the cascade interrupt. So, this MSI interrupt has been acked
42 static void fsl_msi_end_irq(unsigned int virq)
46 static struct irq_chip fsl_msi_chip = {
48 .unmask = unmask_msi_irq,
49 .ack = fsl_msi_end_irq,
53 static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
56 struct fsl_msi *msi_data = h->host_data;
57 struct irq_chip *chip = &fsl_msi_chip;
59 irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
61 set_irq_chip_data(virq, msi_data);
62 set_irq_chip_and_handler(virq, chip, handle_edge_irq);
67 static struct irq_host_ops fsl_msi_host_ops = {
68 .map = fsl_msi_host_map,
71 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
75 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
76 msi_data->irqhost->of_node);
80 rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
82 msi_bitmap_free(&msi_data->bitmap);
89 static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
91 if (type == PCI_CAP_ID_MSIX)
92 pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
97 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
99 struct msi_desc *entry;
100 struct fsl_msi *msi_data;
102 list_for_each_entry(entry, &pdev->msi_list, list) {
103 if (entry->irq == NO_IRQ)
105 msi_data = get_irq_chip_data(entry->irq);
106 set_irq_msi(entry->irq, NULL);
107 msi_bitmap_free_hwirqs(&msi_data->bitmap,
108 virq_to_hw(entry->irq), 1);
109 irq_dispose_mapping(entry->irq);
115 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
117 struct fsl_msi *fsl_msi_data)
119 struct fsl_msi *msi_data = fsl_msi_data;
120 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
123 pci_bus_read_config_dword(hose->bus,
124 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
126 msg->address_lo = msi_data->msi_addr_lo + base;
127 msg->address_hi = msi_data->msi_addr_hi;
130 pr_debug("%s: allocated srs: %d, ibs: %d\n",
131 __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
134 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
138 struct msi_desc *entry;
140 struct fsl_msi *msi_data;
142 list_for_each_entry(entry, &pdev->msi_list, list) {
143 msi_data = get_irq_chip_data(entry->irq);
145 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
148 pr_debug("%s: fail allocating msi interrupt\n",
153 virq = irq_create_mapping(msi_data->irqhost, hwirq);
155 if (virq == NO_IRQ) {
156 pr_debug("%s: fail mapping hwirq 0x%x\n",
158 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
162 set_irq_msi(virq, entry);
164 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
165 write_msi_msg(virq, &msg);
173 static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
175 unsigned int cascade_irq;
176 struct fsl_msi *msi_data = get_irq_chip_data(irq);
182 raw_spin_lock(&desc->lock);
183 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
184 if (desc->chip->mask_ack)
185 desc->chip->mask_ack(irq);
187 desc->chip->mask(irq);
188 desc->chip->ack(irq);
192 if (unlikely(desc->status & IRQ_INPROGRESS))
195 msir_index = (int)desc->handler_data;
197 if (msir_index >= NR_MSI_REG)
198 cascade_irq = NO_IRQ;
200 desc->status |= IRQ_INPROGRESS;
201 switch (msi_data->feature & FSL_PIC_IP_MASK) {
202 case FSL_PIC_IP_MPIC:
203 msir_value = fsl_msi_read(msi_data->msi_regs,
206 case FSL_PIC_IP_IPIC:
207 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
212 intr_index = ffs(msir_value) - 1;
214 cascade_irq = irq_linear_revmap(msi_data->irqhost,
215 msir_index * IRQS_PER_MSI_REG +
216 intr_index + have_shift);
217 if (cascade_irq != NO_IRQ)
218 generic_handle_irq(cascade_irq);
219 have_shift += intr_index + 1;
220 msir_value = msir_value >> (intr_index + 1);
222 desc->status &= ~IRQ_INPROGRESS;
224 switch (msi_data->feature & FSL_PIC_IP_MASK) {
225 case FSL_PIC_IP_MPIC:
226 desc->chip->eoi(irq);
228 case FSL_PIC_IP_IPIC:
229 if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
230 desc->chip->unmask(irq);
234 raw_spin_unlock(&desc->lock);
237 static int __devinit fsl_of_msi_probe(struct of_device *dev,
238 const struct of_device_id *match)
246 struct fsl_msi_feature *features = match->data;
248 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
250 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
252 dev_err(&dev->dev, "No memory for MSI structure\n");
257 msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR,
258 NR_MSI_IRQS, &fsl_msi_host_ops, 0);
260 if (msi->irqhost == NULL) {
261 dev_err(&dev->dev, "No memory for MSI irqhost\n");
266 /* Get the MSI reg base */
267 err = of_address_to_resource(dev->node, 0, &res);
269 dev_err(&dev->dev, "%s resource error!\n",
270 dev->node->full_name);
274 msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
275 if (!msi->msi_regs) {
276 dev_err(&dev->dev, "ioremap problem failed\n");
280 msi->feature = features->fsl_pic_ip;
282 msi->irqhost->host_data = msi;
284 msi->msi_addr_hi = 0x0;
285 msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
287 rc = fsl_msi_init_allocator(msi);
289 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
293 p = of_get_property(dev->node, "interrupts", &count);
295 dev_err(&dev->dev, "no interrupts property found on %s\n",
296 dev->node->full_name);
300 if (count % 8 != 0) {
301 dev_err(&dev->dev, "Malformed interrupts property on %s\n",
302 dev->node->full_name);
307 count /= sizeof(u32);
308 for (i = 0; i < count / 2; i++) {
311 virt_msir = irq_of_parse_and_map(dev->node, i);
312 if (virt_msir != NO_IRQ) {
313 set_irq_data(virt_msir, (void *)i);
314 set_irq_chained_handler(virt_msir, fsl_msi_cascade);
315 set_irq_chip_data(virt_msir, msi);
319 /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
320 if (!ppc_md.setup_msi_irqs) {
321 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
322 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
323 ppc_md.msi_check_device = fsl_msi_check_device;
324 } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
325 dev_err(&dev->dev, "Different MSI driver already installed!\n");
335 static const struct fsl_msi_feature mpic_msi_feature = {
336 .fsl_pic_ip = FSL_PIC_IP_MPIC,
337 .msiir_offset = 0x140,
340 static const struct fsl_msi_feature ipic_msi_feature = {
341 .fsl_pic_ip = FSL_PIC_IP_IPIC,
342 .msiir_offset = 0x38,
345 static const struct of_device_id fsl_of_msi_ids[] = {
347 .compatible = "fsl,mpic-msi",
348 .data = (void *)&mpic_msi_feature,
351 .compatible = "fsl,ipic-msi",
352 .data = (void *)&ipic_msi_feature,
357 static struct of_platform_driver fsl_of_msi_driver = {
359 .match_table = fsl_of_msi_ids,
360 .probe = fsl_of_msi_probe,
363 static __init int fsl_of_msi_init(void)
365 return of_register_platform_driver(&fsl_of_msi_driver);
368 subsys_initcall(fsl_of_msi_init);