arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26 #include <linux/iommu.h>
  27 #include <linux/rculist.h>
  28 #include <linux/sizes.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/machdep.h>
  35 #include <asm/msi_bitmap.h>
  36 #include <asm/ppc-pci.h>
  37 #include <asm/opal.h>
  38 #include <asm/iommu.h>
  39 #include <asm/tce.h>
  40 #include <asm/xics.h>
  41 #include <asm/debug.h>
  42 #include <asm/firmware.h>
  43 #include <asm/pnv-pci.h>
  44 #include <asm/mmzone.h>
  45
  46 #include <misc/cxl-base.h>
  47
  48 #include "powernv.h"
  49 #include "pci.h"
  50
  51 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  52 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  54
  55 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  56 #define POWERNV_IOMMU_MAX_LEVELS        5
  57
  58 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
  59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  60
  61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  62                             const char *fmt, ...)
  63 {
  64         struct va_format vaf;
  65         va_list args;
  66         char pfix[32];
  67
  68         va_start(args, fmt);
  69
  70         vaf.fmt = fmt;
  71         vaf.va = &args;
  72
  73         if (pe->flags & PNV_IODA_PE_DEV)
  74                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  75         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  76                 sprintf(pfix, "%04x:%02x     ",
  77                         pci_domain_nr(pe->pbus), pe->pbus->number);
  78 #ifdef CONFIG_PCI_IOV
  79         else if (pe->flags & PNV_IODA_PE_VF)
  80                 sprintf(pfix, "%04x:%02x:%2x.%d",
  81                         pci_domain_nr(pe->parent_dev->bus),
  82                         (pe->rid & 0xff00) >> 8,
  83                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  84 #endif /* CONFIG_PCI_IOV*/
  85
  86         printk("%spci %s: [PE# %.2x] %pV",
  87                level, pfix, pe->pe_number, &vaf);
  88
  89         va_end(args);
  90 }
  91
  92 static bool pnv_iommu_bypass_disabled __read_mostly;
  93
  94 static int __init iommu_setup(char *str)
  95 {
  96         if (!str)
  97                 return -EINVAL;
  98
  99         while (*str) {
 100                 if (!strncmp(str, "nobypass", 8)) {
 101                         pnv_iommu_bypass_disabled = true;
 102                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 103                         break;
 104                 }
 105                 str += strcspn(str, ",");
 106                 if (*str == ',')
 107                         str++;
 108         }
 109
 110         return 0;
 111 }
 112 early_param("iommu", iommu_setup);
 113
 114 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
 115 {
 116         /*
 117          * WARNING: We cannot rely on the resource flags. The Linux PCI
 118          * allocation code sometimes decides to put a 64-bit prefetchable
 119          * BAR in the 32-bit window, so we have to compare the addresses.
 120          *
 121          * For simplicity we only test resource start.
 122          */
 123         return (r->start >= phb->ioda.m64_base &&
 124                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
 125 }
 126
 127 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
 128 {
 129         unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 130
 131         return (resource_flags & flags) == flags;
 132 }
 133
 134 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 135 {
 136         s64 rc;
 137
 138         phb->ioda.pe_array[pe_no].phb = phb;
 139         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 140
 141         /*
 142          * Clear the PE frozen state as it might be put into frozen state
 143          * in the last PCI remove path. It's not harmful to do so when the
 144          * PE is already in unfrozen state.
 145          */
 146         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 147                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 148         if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
 149                 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
 150                         __func__, rc, phb->hose->global_number, pe_no);
 151
 152         return &phb->ioda.pe_array[pe_no];
 153 }
 154
 155 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 156 {
 157         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 158                 pr_warn("%s: Invalid PE %x on PHB#%x\n",
 159                         __func__, pe_no, phb->hose->global_number);
 160                 return;
 161         }
 162
 163         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 164                 pr_debug("%s: PE %x was reserved on PHB#%x\n",
 165                          __func__, pe_no, phb->hose->global_number);
 166
 167         pnv_ioda_init_pe(phb, pe_no);
 168 }
 169
 170 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 171 {
 172         long pe;
 173
 174         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 175                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 176                         return pnv_ioda_init_pe(phb, pe);
 177         }
 178
 179         return NULL;
 180 }
 181
 182 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 183 {
 184         struct pnv_phb *phb = pe->phb;
 185         unsigned int pe_num = pe->pe_number;
 186
 187         WARN_ON(pe->pdev);
 188
 189         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 190         clear_bit(pe_num, phb->ioda.pe_alloc);
 191 }
 192
 193 /* The default M64 BAR is shared by all PEs */
 194 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 195 {
 196         const char *desc;
 197         struct resource *r;
 198         s64 rc;
 199
 200         /* Configure the default M64 BAR */
 201         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 202                                          OPAL_M64_WINDOW_TYPE,
 203                                          phb->ioda.m64_bar_idx,
 204                                          phb->ioda.m64_base,
 205                                          0, /* unused */
 206                                          phb->ioda.m64_size);
 207         if (rc != OPAL_SUCCESS) {
 208                 desc = "configuring";
 209                 goto fail;
 210         }
 211
 212         /* Enable the default M64 BAR */
 213         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 214                                       OPAL_M64_WINDOW_TYPE,
 215                                       phb->ioda.m64_bar_idx,
 216                                       OPAL_ENABLE_M64_SPLIT);
 217         if (rc != OPAL_SUCCESS) {
 218                 desc = "enabling";
 219                 goto fail;
 220         }
 221
 222         /*
 223          * Exclude the segments for reserved and root bus PE, which
 224          * are first or last two PEs.
 225          */
 226         r = &phb->hose->mem_resources[1];
 227         if (phb->ioda.reserved_pe_idx == 0)
 228                 r->start += (2 * phb->ioda.m64_segsize);
 229         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 230                 r->end -= (2 * phb->ioda.m64_segsize);
 231         else
 232                 pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
 233                         phb->ioda.reserved_pe_idx);
 234
 235         return 0;
 236
 237 fail:
 238         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 239                 rc, desc, phb->ioda.m64_bar_idx);
 240         opal_pci_phb_mmio_enable(phb->opal_id,
 241                                  OPAL_M64_WINDOW_TYPE,
 242                                  phb->ioda.m64_bar_idx,
 243                                  OPAL_DISABLE_M64);
 244         return -EIO;
 245 }
 246
 247 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 248                                          unsigned long *pe_bitmap)
 249 {
 250         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 251         struct pnv_phb *phb = hose->private_data;
 252         struct resource *r;
 253         resource_size_t base, sgsz, start, end;
 254         int segno, i;
 255
 256         base = phb->ioda.m64_base;
 257         sgsz = phb->ioda.m64_segsize;
 258         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 259                 r = &pdev->resource[i];
 260                 if (!r->parent || !pnv_pci_is_m64(phb, r))
 261                         continue;
 262
 263                 start = _ALIGN_DOWN(r->start - base, sgsz);
 264                 end = _ALIGN_UP(r->end - base, sgsz);
 265                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 266                         if (pe_bitmap)
 267                                 set_bit(segno, pe_bitmap);
 268                         else
 269                                 pnv_ioda_reserve_pe(phb, segno);
 270                 }
 271         }
 272 }
 273
 274 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 275 {
 276         struct resource *r;
 277         int index;
 278
 279         /*
 280          * There are 16 M64 BARs, each of which has 8 segments. So
 281          * there are as many M64 segments as the maximum number of
 282          * PEs, which is 128.
 283          */
 284         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 285                 unsigned long base, segsz = phb->ioda.m64_segsize;
 286                 int64_t rc;
 287
 288                 base = phb->ioda.m64_base +
 289                        index * PNV_IODA1_M64_SEGS * segsz;
 290                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 291                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 292                                 PNV_IODA1_M64_SEGS * segsz);
 293                 if (rc != OPAL_SUCCESS) {
 294                         pr_warn("  Error %lld setting M64 PHB#%x-BAR#%d\n",
 295                                 rc, phb->hose->global_number, index);
 296                         goto fail;
 297                 }
 298
 299                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 300                                 OPAL_M64_WINDOW_TYPE, index,
 301                                 OPAL_ENABLE_M64_SPLIT);
 302                 if (rc != OPAL_SUCCESS) {
 303                         pr_warn("  Error %lld enabling M64 PHB#%x-BAR#%d\n",
 304                                 rc, phb->hose->global_number, index);
 305                         goto fail;
 306                 }
 307         }
 308
 309         /*
 310          * Exclude the segments for reserved and root bus PE, which
 311          * are first or last two PEs.
 312          */
 313         r = &phb->hose->mem_resources[1];
 314         if (phb->ioda.reserved_pe_idx == 0)
 315                 r->start += (2 * phb->ioda.m64_segsize);
 316         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 317                 r->end -= (2 * phb->ioda.m64_segsize);
 318         else
 319                 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
 320                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 321
 322         return 0;
 323
 324 fail:
 325         for ( ; index >= 0; index--)
 326                 opal_pci_phb_mmio_enable(phb->opal_id,
 327                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 328
 329         return -EIO;
 330 }
 331
 332 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 333                                     unsigned long *pe_bitmap,
 334                                     bool all)
 335 {
 336         struct pci_dev *pdev;
 337
 338         list_for_each_entry(pdev, &bus->devices, bus_list) {
 339                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 340
 341                 if (all && pdev->subordinate)
 342                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 343                                                 pe_bitmap, all);
 344         }
 345 }
 346
 347 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 348 {
 349         struct pci_controller *hose = pci_bus_to_host(bus);
 350         struct pnv_phb *phb = hose->private_data;
 351         struct pnv_ioda_pe *master_pe, *pe;
 352         unsigned long size, *pe_alloc;
 353         int i;
 354
 355         /* Root bus shouldn't use M64 */
 356         if (pci_is_root_bus(bus))
 357                 return NULL;
 358
 359         /* Allocate bitmap */
 360         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 361         pe_alloc = kzalloc(size, GFP_KERNEL);
 362         if (!pe_alloc) {
 363                 pr_warn("%s: Out of memory !\n",
 364                         __func__);
 365                 return NULL;
 366         }
 367
 368         /* Figure out reserved PE numbers by the PE */
 369         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 370
 371         /*
 372          * the current bus might not own M64 window and that's all
 373          * contributed by its child buses. For the case, we needn't
 374          * pick M64 dependent PE#.
 375          */
 376         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 377                 kfree(pe_alloc);
 378                 return NULL;
 379         }
 380
 381         /*
 382          * Figure out the master PE and put all slave PEs to master
 383          * PE's list to form compound PE.
 384          */
 385         master_pe = NULL;
 386         i = -1;
 387         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 388                 phb->ioda.total_pe_num) {
 389                 pe = &phb->ioda.pe_array[i];
 390
 391                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 392                 if (!master_pe) {
 393                         pe->flags |= PNV_IODA_PE_MASTER;
 394                         INIT_LIST_HEAD(&pe->slaves);
 395                         master_pe = pe;
 396                 } else {
 397                         pe->flags |= PNV_IODA_PE_SLAVE;
 398                         pe->master = master_pe;
 399                         list_add_tail(&pe->list, &master_pe->slaves);
 400                 }
 401
 402                 /*
 403                  * P7IOC supports M64DT, which helps mapping M64 segment
 404                  * to one particular PE#. However, PHB3 has fixed mapping
 405                  * between M64 segment and PE#. In order to have same logic
 406                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 407                  * segment and PE# on P7IOC.
 408                  */
 409                 if (phb->type == PNV_PHB_IODA1) {
 410                         int64_t rc;
 411
 412                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 413                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 414                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 415                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 416                         if (rc != OPAL_SUCCESS)
 417                                 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
 418                                         __func__, rc, phb->hose->global_number,
 419                                         pe->pe_number);
 420                 }
 421         }
 422
 423         kfree(pe_alloc);
 424         return master_pe;
 425 }
 426
 427 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 428 {
 429         struct pci_controller *hose = phb->hose;
 430         struct device_node *dn = hose->dn;
 431         struct resource *res;
 432         u32 m64_range[2], i;
 433         const __be32 *r;
 434         u64 pci_addr;
 435
 436         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 437                 pr_info("  Not support M64 window\n");
 438                 return;
 439         }
 440
 441         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 442                 pr_info("  Firmware too old to support M64 window\n");
 443                 return;
 444         }
 445
 446         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 447         if (!r) {
 448                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 449                         dn->full_name);
 450                 return;
 451         }
 452
 453         /*
 454          * Find the available M64 BAR range and pickup the last one for
 455          * covering the whole 64-bits space. We support only one range.
 456          */
 457         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
 458                                        m64_range, 2)) {
 459                 /* In absence of the property, assume 0..15 */
 460                 m64_range[0] = 0;
 461                 m64_range[1] = 16;
 462         }
 463         /* We only support 64 bits in our allocator */
 464         if (m64_range[1] > 63) {
 465                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
 466                         __func__, m64_range[1], phb->hose->global_number);
 467                 m64_range[1] = 63;
 468         }
 469         /* Empty range, no m64 */
 470         if (m64_range[1] <= m64_range[0]) {
 471                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
 472                         __func__, phb->hose->global_number);
 473                 return;
 474         }
 475
 476         /* Configure M64 informations */
 477         res = &hose->mem_resources[1];
 478         res->name = dn->full_name;
 479         res->start = of_translate_address(dn, r + 2);
 480         res->end = res->start + of_read_number(r + 4, 2) - 1;
 481         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 482         pci_addr = of_read_number(r, 2);
 483         hose->mem_offset[1] = res->start - pci_addr;
 484
 485         phb->ioda.m64_size = resource_size(res);
 486         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 487         phb->ioda.m64_base = pci_addr;
 488
 489         /* This lines up nicely with the display from processing OF ranges */
 490         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
 491                 res->start, res->end, pci_addr, m64_range[0],
 492                 m64_range[0] + m64_range[1] - 1);
 493
 494         /* Mark all M64 used up by default */
 495         phb->ioda.m64_bar_alloc = (unsigned long)-1;
 496
 497         /* Use last M64 BAR to cover M64 window */
 498         m64_range[1]--;
 499         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
 500
 501         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
 502
 503         /* Mark remaining ones free */
 504         for (i = m64_range[0]; i < m64_range[1]; i++)
 505                 clear_bit(i, &phb->ioda.m64_bar_alloc);
 506
 507         /*
 508          * Setup init functions for M64 based on IODA version, IODA3 uses
 509          * the IODA2 code.
 510          */
 511         if (phb->type == PNV_PHB_IODA1)
 512                 phb->init_m64 = pnv_ioda1_init_m64;
 513         else
 514                 phb->init_m64 = pnv_ioda2_init_m64;
 515         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
 516         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
 517 }
 518
 519 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 520 {
 521         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 522         struct pnv_ioda_pe *slave;
 523         s64 rc;
 524
 525         /* Fetch master PE */
 526         if (pe->flags & PNV_IODA_PE_SLAVE) {
 527                 pe = pe->master;
 528                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 529                         return;
 530
 531                 pe_no = pe->pe_number;
 532         }
 533
 534         /* Freeze master PE */
 535         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 536                                      pe_no,
 537                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 538         if (rc != OPAL_SUCCESS) {
 539                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 540                         __func__, rc, phb->hose->global_number, pe_no);
 541                 return;
 542         }
 543
 544         /* Freeze slave PEs */
 545         if (!(pe->flags & PNV_IODA_PE_MASTER))
 546                 return;
 547
 548         list_for_each_entry(slave, &pe->slaves, list) {
 549                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 550                                              slave->pe_number,
 551                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 552                 if (rc != OPAL_SUCCESS)
 553                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 554                                 __func__, rc, phb->hose->global_number,
 555                                 slave->pe_number);
 556         }
 557 }
 558
 559 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 560 {
 561         struct pnv_ioda_pe *pe, *slave;
 562         s64 rc;
 563
 564         /* Find master PE */
 565         pe = &phb->ioda.pe_array[pe_no];
 566         if (pe->flags & PNV_IODA_PE_SLAVE) {
 567                 pe = pe->master;
 568                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 569                 pe_no = pe->pe_number;
 570         }
 571
 572         /* Clear frozen state for master PE */
 573         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 574         if (rc != OPAL_SUCCESS) {
 575                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 576                         __func__, rc, opt, phb->hose->global_number, pe_no);
 577                 return -EIO;
 578         }
 579
 580         if (!(pe->flags & PNV_IODA_PE_MASTER))
 581                 return 0;
 582
 583         /* Clear frozen state for slave PEs */
 584         list_for_each_entry(slave, &pe->slaves, list) {
 585                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 586                                              slave->pe_number,
 587                                              opt);
 588                 if (rc != OPAL_SUCCESS) {
 589                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 590                                 __func__, rc, opt, phb->hose->global_number,
 591                                 slave->pe_number);
 592                         return -EIO;
 593                 }
 594         }
 595
 596         return 0;
 597 }
 598
 599 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 600 {
 601         struct pnv_ioda_pe *slave, *pe;
 602         u8 fstate, state;
 603         __be16 pcierr;
 604         s64 rc;
 605
 606         /* Sanity check on PE number */
 607         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 608                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 609
 610         /*
 611          * Fetch the master PE and the PE instance might be
 612          * not initialized yet.
 613          */
 614         pe = &phb->ioda.pe_array[pe_no];
 615         if (pe->flags & PNV_IODA_PE_SLAVE) {
 616                 pe = pe->master;
 617                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 618                 pe_no = pe->pe_number;
 619         }
 620
 621         /* Check the master PE */
 622         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 623                                         &state, &pcierr, NULL);
 624         if (rc != OPAL_SUCCESS) {
 625                 pr_warn("%s: Failure %lld getting "
 626                         "PHB#%x-PE#%x state\n",
 627                         __func__, rc,
 628                         phb->hose->global_number, pe_no);
 629                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 630         }
 631
 632         /* Check the slave PE */
 633         if (!(pe->flags & PNV_IODA_PE_MASTER))
 634                 return state;
 635
 636         list_for_each_entry(slave, &pe->slaves, list) {
 637                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 638                                                 slave->pe_number,
 639                                                 &fstate,
 640                                                 &pcierr,
 641                                                 NULL);
 642                 if (rc != OPAL_SUCCESS) {
 643                         pr_warn("%s: Failure %lld getting "
 644                                 "PHB#%x-PE#%x state\n",
 645                                 __func__, rc,
 646                                 phb->hose->global_number, slave->pe_number);
 647                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 648                 }
 649
 650                 /*
 651                  * Override the result based on the ascending
 652                  * priority.
 653                  */
 654                 if (fstate > state)
 655                         state = fstate;
 656         }
 657
 658         return state;
 659 }
 660
 661 /* Currently those 2 are only used when MSIs are enabled, this will change
 662  * but in the meantime, we need to protect them to avoid warnings
 663  */
 664 #ifdef CONFIG_PCI_MSI
 665 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 666 {
 667         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 668         struct pnv_phb *phb = hose->private_data;
 669         struct pci_dn *pdn = pci_get_pdn(dev);
 670
 671         if (!pdn)
 672                 return NULL;
 673         if (pdn->pe_number == IODA_INVALID_PE)
 674                 return NULL;
 675         return &phb->ioda.pe_array[pdn->pe_number];
 676 }
 677 #endif /* CONFIG_PCI_MSI */
 678
 679 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 680                                   struct pnv_ioda_pe *parent,
 681                                   struct pnv_ioda_pe *child,
 682                                   bool is_add)
 683 {
 684         const char *desc = is_add ? "adding" : "removing";
 685         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 686                               OPAL_REMOVE_PE_FROM_DOMAIN;
 687         struct pnv_ioda_pe *slave;
 688         long rc;
 689
 690         /* Parent PE affects child PE */
 691         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 692                                 child->pe_number, op);
 693         if (rc != OPAL_SUCCESS) {
 694                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 695                         rc, desc);
 696                 return -ENXIO;
 697         }
 698
 699         if (!(child->flags & PNV_IODA_PE_MASTER))
 700                 return 0;
 701
 702         /* Compound case: parent PE affects slave PEs */
 703         list_for_each_entry(slave, &child->slaves, list) {
 704                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 705                                         slave->pe_number, op);
 706                 if (rc != OPAL_SUCCESS) {
 707                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 708                                 rc, desc);
 709                         return -ENXIO;
 710                 }
 711         }
 712
 713         return 0;
 714 }
 715
 716 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 717                               struct pnv_ioda_pe *pe,
 718                               bool is_add)
 719 {
 720         struct pnv_ioda_pe *slave;
 721         struct pci_dev *pdev = NULL;
 722         int ret;
 723
 724         /*
 725          * Clear PE frozen state. If it's master PE, we need
 726          * clear slave PE frozen state as well.
 727          */
 728         if (is_add) {
 729                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 730                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 731                 if (pe->flags & PNV_IODA_PE_MASTER) {
 732                         list_for_each_entry(slave, &pe->slaves, list)
 733                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 734                                                           slave->pe_number,
 735                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 736                 }
 737         }
 738
 739         /*
 740          * Associate PE in PELT. We need add the PE into the
 741          * corresponding PELT-V as well. Otherwise, the error
 742          * originated from the PE might contribute to other
 743          * PEs.
 744          */
 745         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 746         if (ret)
 747                 return ret;
 748
 749         /* For compound PEs, any one affects all of them */
 750         if (pe->flags & PNV_IODA_PE_MASTER) {
 751                 list_for_each_entry(slave, &pe->slaves, list) {
 752                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 753                         if (ret)
 754                                 return ret;
 755                 }
 756         }
 757
 758         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 759                 pdev = pe->pbus->self;
 760         else if (pe->flags & PNV_IODA_PE_DEV)
 761                 pdev = pe->pdev->bus->self;
 762 #ifdef CONFIG_PCI_IOV
 763         else if (pe->flags & PNV_IODA_PE_VF)
 764                 pdev = pe->parent_dev;
 765 #endif /* CONFIG_PCI_IOV */
 766         while (pdev) {
 767                 struct pci_dn *pdn = pci_get_pdn(pdev);
 768                 struct pnv_ioda_pe *parent;
 769
 770                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 771                         parent = &phb->ioda.pe_array[pdn->pe_number];
 772                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 773                         if (ret)
 774                                 return ret;
 775                 }
 776
 777                 pdev = pdev->bus->self;
 778         }
 779
 780         return 0;
 781 }
 782
 783 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 784 {
 785         struct pci_dev *parent;
 786         uint8_t bcomp, dcomp, fcomp;
 787         int64_t rc;
 788         long rid_end, rid;
 789
 790         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 791         if (pe->pbus) {
 792                 int count;
 793
 794                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 795                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 796                 parent = pe->pbus->self;
 797                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 798                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 799                 else
 800                         count = 1;
 801
 802                 switch(count) {
 803                 case  1: bcomp = OpalPciBusAll;         break;
 804                 case  2: bcomp = OpalPciBus7Bits;       break;
 805                 case  4: bcomp = OpalPciBus6Bits;       break;
 806                 case  8: bcomp = OpalPciBus5Bits;       break;
 807                 case 16: bcomp = OpalPciBus4Bits;       break;
 808                 case 32: bcomp = OpalPciBus3Bits;       break;
 809                 default:
 810                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 811                                 count);
 812                         /* Do an exact match only */
 813                         bcomp = OpalPciBusAll;
 814                 }
 815                 rid_end = pe->rid + (count << 8);
 816         } else {
 817 #ifdef CONFIG_PCI_IOV
 818                 if (pe->flags & PNV_IODA_PE_VF)
 819                         parent = pe->parent_dev;
 820                 else
 821 #endif
 822                         parent = pe->pdev->bus->self;
 823                 bcomp = OpalPciBusAll;
 824                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 825                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 826                 rid_end = pe->rid + 1;
 827         }
 828
 829         /* Clear the reverse map */
 830         for (rid = pe->rid; rid < rid_end; rid++)
 831                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 832
 833         /* Release from all parents PELT-V */
 834         while (parent) {
 835                 struct pci_dn *pdn = pci_get_pdn(parent);
 836                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 837                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 838                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 839                         /* XXX What to do in case of error ? */
 840                 }
 841                 parent = parent->bus->self;
 842         }
 843
 844         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 845                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 846
 847         /* Disassociate PE in PELT */
 848         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 849                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 850         if (rc)
 851                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 852         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 853                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 854         if (rc)
 855                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 856
 857         pe->pbus = NULL;
 858         pe->pdev = NULL;
 859 #ifdef CONFIG_PCI_IOV
 860         pe->parent_dev = NULL;
 861 #endif
 862
 863         return 0;
 864 }
 865
 866 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 867 {
 868         struct pci_dev *parent;
 869         uint8_t bcomp, dcomp, fcomp;
 870         long rc, rid_end, rid;
 871
 872         /* Bus validation ? */
 873         if (pe->pbus) {
 874                 int count;
 875
 876                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 877                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 878                 parent = pe->pbus->self;
 879                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 880                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 881                 else
 882                         count = 1;
 883
 884                 switch(count) {
 885                 case  1: bcomp = OpalPciBusAll;         break;
 886                 case  2: bcomp = OpalPciBus7Bits;       break;
 887                 case  4: bcomp = OpalPciBus6Bits;       break;
 888                 case  8: bcomp = OpalPciBus5Bits;       break;
 889                 case 16: bcomp = OpalPciBus4Bits;       break;
 890                 case 32: bcomp = OpalPciBus3Bits;       break;
 891                 default:
 892                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 893                                 count);
 894                         /* Do an exact match only */
 895                         bcomp = OpalPciBusAll;
 896                 }
 897                 rid_end = pe->rid + (count << 8);
 898         } else {
 899 #ifdef CONFIG_PCI_IOV
 900                 if (pe->flags & PNV_IODA_PE_VF)
 901                         parent = pe->parent_dev;
 902                 else
 903 #endif /* CONFIG_PCI_IOV */
 904                         parent = pe->pdev->bus->self;
 905                 bcomp = OpalPciBusAll;
 906                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 907                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 908                 rid_end = pe->rid + 1;
 909         }
 910
 911         /*
 912          * Associate PE in PELT. We need add the PE into the
 913          * corresponding PELT-V as well. Otherwise, the error
 914          * originated from the PE might contribute to other
 915          * PEs.
 916          */
 917         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 918                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 919         if (rc) {
 920                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 921                 return -ENXIO;
 922         }
 923
 924         /*
 925          * Configure PELTV. NPUs don't have a PELTV table so skip
 926          * configuration on them.
 927          */
 928         if (phb->type != PNV_PHB_NPU)
 929                 pnv_ioda_set_peltv(phb, pe, true);
 930
 931         /* Setup reverse map */
 932         for (rid = pe->rid; rid < rid_end; rid++)
 933                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 934
 935         /* Setup one MVTs on IODA1 */
 936         if (phb->type != PNV_PHB_IODA1) {
 937                 pe->mve_number = 0;
 938                 goto out;
 939         }
 940
 941         pe->mve_number = pe->pe_number;
 942         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 943         if (rc != OPAL_SUCCESS) {
 944                 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
 945                        rc, pe->mve_number);
 946                 pe->mve_number = -1;
 947         } else {
 948                 rc = opal_pci_set_mve_enable(phb->opal_id,
 949                                              pe->mve_number, OPAL_ENABLE_MVE);
 950                 if (rc) {
 951                         pe_err(pe, "OPAL error %ld enabling MVE %x\n",
 952                                rc, pe->mve_number);
 953                         pe->mve_number = -1;
 954                 }
 955         }
 956
 957 out:
 958         return 0;
 959 }
 960
 961 #ifdef CONFIG_PCI_IOV
 962 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 963 {
 964         struct pci_dn *pdn = pci_get_pdn(dev);
 965         int i;
 966         struct resource *res, res2;
 967         resource_size_t size;
 968         u16 num_vfs;
 969
 970         if (!dev->is_physfn)
 971                 return -EINVAL;
 972
 973         /*
 974          * "offset" is in VFs.  The M64 windows are sized so that when they
 975          * are segmented, each segment is the same size as the IOV BAR.
 976          * Each segment is in a separate PE, and the high order bits of the
 977          * address are the PE number.  Therefore, each VF's BAR is in a
 978          * separate PE, and changing the IOV BAR start address changes the
 979          * range of PEs the VFs are in.
 980          */
 981         num_vfs = pdn->num_vfs;
 982         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 983                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 984                 if (!res->flags || !res->parent)
 985                         continue;
 986
 987                 /*
 988                  * The actual IOV BAR range is determined by the start address
 989                  * and the actual size for num_vfs VFs BAR.  This check is to
 990                  * make sure that after shifting, the range will not overlap
 991                  * with another device.
 992                  */
 993                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 994                 res2.flags = res->flags;
 995                 res2.start = res->start + (size * offset);
 996                 res2.end = res2.start + (size * num_vfs) - 1;
 997
 998                 if (res2.end > res->end) {
 999                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1000                                 i, &res2, res, num_vfs, offset);
1001                         return -EBUSY;
1002                 }
1003         }
1004
1005         /*
1006          * After doing so, there would be a "hole" in the /proc/iomem when
1007          * offset is a positive value. It looks like the device return some
1008          * mmio back to the system, which actually no one could use it.
1009          */
1010         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1011                 res = &dev->resource[i + PCI_IOV_RESOURCES];
1012                 if (!res->flags || !res->parent)
1013                         continue;
1014
1015                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1016                 res2 = *res;
1017                 res->start += size * offset;
1018
1019                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1020                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1021                          num_vfs, offset);
1022                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1023         }
1024         return 0;
1025 }
1026 #endif /* CONFIG_PCI_IOV */
1027
1028 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1029 {
1030         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1031         struct pnv_phb *phb = hose->private_data;
1032         struct pci_dn *pdn = pci_get_pdn(dev);
1033         struct pnv_ioda_pe *pe;
1034
1035         if (!pdn) {
1036                 pr_err("%s: Device tree node not associated properly\n",
1037                            pci_name(dev));
1038                 return NULL;
1039         }
1040         if (pdn->pe_number != IODA_INVALID_PE)
1041                 return NULL;
1042
1043         pe = pnv_ioda_alloc_pe(phb);
1044         if (!pe) {
1045                 pr_warning("%s: Not enough PE# available, disabling device\n",
1046                            pci_name(dev));
1047                 return NULL;
1048         }
1049
1050         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1051          * pointer in the PE data structure, both should be destroyed at the
1052          * same time. However, this needs to be looked at more closely again
1053          * once we actually start removing things (Hotplug, SR-IOV, ...)
1054          *
1055          * At some point we want to remove the PDN completely anyways
1056          */
1057         pci_dev_get(dev);
1058         pdn->pcidev = dev;
1059         pdn->pe_number = pe->pe_number;
1060         pe->flags = PNV_IODA_PE_DEV;
1061         pe->pdev = dev;
1062         pe->pbus = NULL;
1063         pe->mve_number = -1;
1064         pe->rid = dev->bus->number << 8 | pdn->devfn;
1065
1066         pe_info(pe, "Associated device to PE\n");
1067
1068         if (pnv_ioda_configure_pe(phb, pe)) {
1069                 /* XXX What do we do here ? */
1070                 pnv_ioda_free_pe(pe);
1071                 pdn->pe_number = IODA_INVALID_PE;
1072                 pe->pdev = NULL;
1073                 pci_dev_put(dev);
1074                 return NULL;
1075         }
1076
1077         /* Put PE to the list */
1078         list_add_tail(&pe->list, &phb->ioda.pe_list);
1079
1080         return pe;
1081 }
1082
1083 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1084 {
1085         struct pci_dev *dev;
1086
1087         list_for_each_entry(dev, &bus->devices, bus_list) {
1088                 struct pci_dn *pdn = pci_get_pdn(dev);
1089
1090                 if (pdn == NULL) {
1091                         pr_warn("%s: No device node associated with device !\n",
1092                                 pci_name(dev));
1093                         continue;
1094                 }
1095
1096                 /*
1097                  * In partial hotplug case, the PCI device might be still
1098                  * associated with the PE and needn't attach it to the PE
1099                  * again.
1100                  */
1101                 if (pdn->pe_number != IODA_INVALID_PE)
1102                         continue;
1103
1104                 pe->device_count++;
1105                 pdn->pcidev = dev;
1106                 pdn->pe_number = pe->pe_number;
1107                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1108                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1109         }
1110 }
1111
1112 /*
1113  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1114  * single PCI bus. Another one that contains the primary PCI bus and its
1115  * subordinate PCI devices and buses. The second type of PE is normally
1116  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1117  */
1118 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1119 {
1120         struct pci_controller *hose = pci_bus_to_host(bus);
1121         struct pnv_phb *phb = hose->private_data;
1122         struct pnv_ioda_pe *pe = NULL;
1123         unsigned int pe_num;
1124
1125         /*
1126          * In partial hotplug case, the PE instance might be still alive.
1127          * We should reuse it instead of allocating a new one.
1128          */
1129         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1130         if (pe_num != IODA_INVALID_PE) {
1131                 pe = &phb->ioda.pe_array[pe_num];
1132                 pnv_ioda_setup_same_PE(bus, pe);
1133                 return NULL;
1134         }
1135
1136         /* PE number for root bus should have been reserved */
1137         if (pci_is_root_bus(bus) &&
1138             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1139                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1140
1141         /* Check if PE is determined by M64 */
1142         if (!pe && phb->pick_m64_pe)
1143                 pe = phb->pick_m64_pe(bus, all);
1144
1145         /* The PE number isn't pinned by M64 */
1146         if (!pe)
1147                 pe = pnv_ioda_alloc_pe(phb);
1148
1149         if (!pe) {
1150                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1151                         __func__, pci_domain_nr(bus), bus->number);
1152                 return NULL;
1153         }
1154
1155         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1156         pe->pbus = bus;
1157         pe->pdev = NULL;
1158         pe->mve_number = -1;
1159         pe->rid = bus->busn_res.start << 8;
1160
1161         if (all)
1162                 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1163                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1164         else
1165                 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1166                         bus->busn_res.start, pe->pe_number);
1167
1168         if (pnv_ioda_configure_pe(phb, pe)) {
1169                 /* XXX What do we do here ? */
1170                 pnv_ioda_free_pe(pe);
1171                 pe->pbus = NULL;
1172                 return NULL;
1173         }
1174
1175         /* Associate it with all child devices */
1176         pnv_ioda_setup_same_PE(bus, pe);
1177
1178         /* Put PE to the list */
1179         list_add_tail(&pe->list, &phb->ioda.pe_list);
1180
1181         return pe;
1182 }
1183
1184 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1185 {
1186         int pe_num, found_pe = false, rc;
1187         long rid;
1188         struct pnv_ioda_pe *pe;
1189         struct pci_dev *gpu_pdev;
1190         struct pci_dn *npu_pdn;
1191         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1192         struct pnv_phb *phb = hose->private_data;
1193
1194         /*
1195          * Due to a hardware errata PE#0 on the NPU is reserved for
1196          * error handling. This means we only have three PEs remaining
1197          * which need to be assigned to four links, implying some
1198          * links must share PEs.
1199          *
1200          * To achieve this we assign PEs such that NPUs linking the
1201          * same GPU get assigned the same PE.
1202          */
1203         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1204         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1205                 pe = &phb->ioda.pe_array[pe_num];
1206                 if (!pe->pdev)
1207                         continue;
1208
1209                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1210                         /*
1211                          * This device has the same peer GPU so should
1212                          * be assigned the same PE as the existing
1213                          * peer NPU.
1214                          */
1215                         dev_info(&npu_pdev->dev,
1216                                 "Associating to existing PE %x\n", pe_num);
1217                         pci_dev_get(npu_pdev);
1218                         npu_pdn = pci_get_pdn(npu_pdev);
1219                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1220                         npu_pdn->pcidev = npu_pdev;
1221                         npu_pdn->pe_number = pe_num;
1222                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1223
1224                         /* Map the PE to this link */
1225                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1226                                         OpalPciBusAll,
1227                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1228                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1229                                         OPAL_MAP_PE);
1230                         WARN_ON(rc != OPAL_SUCCESS);
1231                         found_pe = true;
1232                         break;
1233                 }
1234         }
1235
1236         if (!found_pe)
1237                 /*
1238                  * Could not find an existing PE so allocate a new
1239                  * one.
1240                  */
1241                 return pnv_ioda_setup_dev_PE(npu_pdev);
1242         else
1243                 return pe;
1244 }
1245
1246 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1247 {
1248         struct pci_dev *pdev;
1249
1250         list_for_each_entry(pdev, &bus->devices, bus_list)
1251                 pnv_ioda_setup_npu_PE(pdev);
1252 }
1253
1254 static void pnv_pci_ioda_setup_PEs(void)
1255 {
1256         struct pci_controller *hose, *tmp;
1257         struct pnv_phb *phb;
1258
1259         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1260                 phb = hose->private_data;
1261                 if (phb->type == PNV_PHB_NPU) {
1262                         /* PE#0 is needed for error reporting */
1263                         pnv_ioda_reserve_pe(phb, 0);
1264                         pnv_ioda_setup_npu_PEs(hose->bus);
1265                 }
1266         }
1267 }
1268
1269 #ifdef CONFIG_PCI_IOV
1270 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1271 {
1272         struct pci_bus        *bus;
1273         struct pci_controller *hose;
1274         struct pnv_phb        *phb;
1275         struct pci_dn         *pdn;
1276         int                    i, j;
1277         int                    m64_bars;
1278
1279         bus = pdev->bus;
1280         hose = pci_bus_to_host(bus);
1281         phb = hose->private_data;
1282         pdn = pci_get_pdn(pdev);
1283
1284         if (pdn->m64_single_mode)
1285                 m64_bars = num_vfs;
1286         else
1287                 m64_bars = 1;
1288
1289         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1290                 for (j = 0; j < m64_bars; j++) {
1291                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1292                                 continue;
1293                         opal_pci_phb_mmio_enable(phb->opal_id,
1294                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1295                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1296                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1297                 }
1298
1299         kfree(pdn->m64_map);
1300         return 0;
1301 }
1302
1303 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1304 {
1305         struct pci_bus        *bus;
1306         struct pci_controller *hose;
1307         struct pnv_phb        *phb;
1308         struct pci_dn         *pdn;
1309         unsigned int           win;
1310         struct resource       *res;
1311         int                    i, j;
1312         int64_t                rc;
1313         int                    total_vfs;
1314         resource_size_t        size, start;
1315         int                    pe_num;
1316         int                    m64_bars;
1317
1318         bus = pdev->bus;
1319         hose = pci_bus_to_host(bus);
1320         phb = hose->private_data;
1321         pdn = pci_get_pdn(pdev);
1322         total_vfs = pci_sriov_get_totalvfs(pdev);
1323
1324         if (pdn->m64_single_mode)
1325                 m64_bars = num_vfs;
1326         else
1327                 m64_bars = 1;
1328
1329         pdn->m64_map = kmalloc_array(m64_bars,
1330                                      sizeof(*pdn->m64_map),
1331                                      GFP_KERNEL);
1332         if (!pdn->m64_map)
1333                 return -ENOMEM;
1334         /* Initialize the m64_map to IODA_INVALID_M64 */
1335         for (i = 0; i < m64_bars ; i++)
1336                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1337                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1338
1339
1340         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1341                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1342                 if (!res->flags || !res->parent)
1343                         continue;
1344
1345                 for (j = 0; j < m64_bars; j++) {
1346                         do {
1347                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1348                                                 phb->ioda.m64_bar_idx + 1, 0);
1349
1350                                 if (win >= phb->ioda.m64_bar_idx + 1)
1351                                         goto m64_failed;
1352                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1353
1354                         pdn->m64_map[j][i] = win;
1355
1356                         if (pdn->m64_single_mode) {
1357                                 size = pci_iov_resource_size(pdev,
1358                                                         PCI_IOV_RESOURCES + i);
1359                                 start = res->start + size * j;
1360                         } else {
1361                                 size = resource_size(res);
1362                                 start = res->start;
1363                         }
1364
1365                         /* Map the M64 here */
1366                         if (pdn->m64_single_mode) {
1367                                 pe_num = pdn->pe_num_map[j];
1368                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1369                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1370                                                 pdn->m64_map[j][i], 0);
1371                         }
1372
1373                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1374                                                  OPAL_M64_WINDOW_TYPE,
1375                                                  pdn->m64_map[j][i],
1376                                                  start,
1377                                                  0, /* unused */
1378                                                  size);
1379
1380
1381                         if (rc != OPAL_SUCCESS) {
1382                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1383                                         win, rc);
1384                                 goto m64_failed;
1385                         }
1386
1387                         if (pdn->m64_single_mode)
1388                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1389                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1390                         else
1391                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1392                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1393
1394                         if (rc != OPAL_SUCCESS) {
1395                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1396                                         win, rc);
1397                                 goto m64_failed;
1398                         }
1399                 }
1400         }
1401         return 0;
1402
1403 m64_failed:
1404         pnv_pci_vf_release_m64(pdev, num_vfs);
1405         return -EBUSY;
1406 }
1407
1408 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1409                 int num);
1410 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1411
1412 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1413 {
1414         struct iommu_table    *tbl;
1415         int64_t               rc;
1416
1417         tbl = pe->table_group.tables[0];
1418         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1419         if (rc)
1420                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1421
1422         pnv_pci_ioda2_set_bypass(pe, false);
1423         if (pe->table_group.group) {
1424                 iommu_group_put(pe->table_group.group);
1425                 BUG_ON(pe->table_group.group);
1426         }
1427         pnv_pci_ioda2_table_free_pages(tbl);
1428         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1429 }
1430
1431 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1432 {
1433         struct pci_bus        *bus;
1434         struct pci_controller *hose;
1435         struct pnv_phb        *phb;
1436         struct pnv_ioda_pe    *pe, *pe_n;
1437         struct pci_dn         *pdn;
1438
1439         bus = pdev->bus;
1440         hose = pci_bus_to_host(bus);
1441         phb = hose->private_data;
1442         pdn = pci_get_pdn(pdev);
1443
1444         if (!pdev->is_physfn)
1445                 return;
1446
1447         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1448                 if (pe->parent_dev != pdev)
1449                         continue;
1450
1451                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1452
1453                 /* Remove from list */
1454                 mutex_lock(&phb->ioda.pe_list_mutex);
1455                 list_del(&pe->list);
1456                 mutex_unlock(&phb->ioda.pe_list_mutex);
1457
1458                 pnv_ioda_deconfigure_pe(phb, pe);
1459
1460                 pnv_ioda_free_pe(pe);
1461         }
1462 }
1463
1464 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1465 {
1466         struct pci_bus        *bus;
1467         struct pci_controller *hose;
1468         struct pnv_phb        *phb;
1469         struct pnv_ioda_pe    *pe;
1470         struct pci_dn         *pdn;
1471         u16                    num_vfs, i;
1472
1473         bus = pdev->bus;
1474         hose = pci_bus_to_host(bus);
1475         phb = hose->private_data;
1476         pdn = pci_get_pdn(pdev);
1477         num_vfs = pdn->num_vfs;
1478
1479         /* Release VF PEs */
1480         pnv_ioda_release_vf_PE(pdev);
1481
1482         if (phb->type == PNV_PHB_IODA2) {
1483                 if (!pdn->m64_single_mode)
1484                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1485
1486                 /* Release M64 windows */
1487                 pnv_pci_vf_release_m64(pdev, num_vfs);
1488
1489                 /* Release PE numbers */
1490                 if (pdn->m64_single_mode) {
1491                         for (i = 0; i < num_vfs; i++) {
1492                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1493                                         continue;
1494
1495                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1496                                 pnv_ioda_free_pe(pe);
1497                         }
1498                 } else
1499                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1500                 /* Releasing pe_num_map */
1501                 kfree(pdn->pe_num_map);
1502         }
1503 }
1504
1505 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1506                                        struct pnv_ioda_pe *pe);
1507 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1508 {
1509         struct pci_bus        *bus;
1510         struct pci_controller *hose;
1511         struct pnv_phb        *phb;
1512         struct pnv_ioda_pe    *pe;
1513         int                    pe_num;
1514         u16                    vf_index;
1515         struct pci_dn         *pdn;
1516
1517         bus = pdev->bus;
1518         hose = pci_bus_to_host(bus);
1519         phb = hose->private_data;
1520         pdn = pci_get_pdn(pdev);
1521
1522         if (!pdev->is_physfn)
1523                 return;
1524
1525         /* Reserve PE for each VF */
1526         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1527                 if (pdn->m64_single_mode)
1528                         pe_num = pdn->pe_num_map[vf_index];
1529                 else
1530                         pe_num = *pdn->pe_num_map + vf_index;
1531
1532                 pe = &phb->ioda.pe_array[pe_num];
1533                 pe->pe_number = pe_num;
1534                 pe->phb = phb;
1535                 pe->flags = PNV_IODA_PE_VF;
1536                 pe->pbus = NULL;
1537                 pe->parent_dev = pdev;
1538                 pe->mve_number = -1;
1539                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1540                            pci_iov_virtfn_devfn(pdev, vf_index);
1541
1542                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1543                         hose->global_number, pdev->bus->number,
1544                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1545                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1546
1547                 if (pnv_ioda_configure_pe(phb, pe)) {
1548                         /* XXX What do we do here ? */
1549                         pnv_ioda_free_pe(pe);
1550                         pe->pdev = NULL;
1551                         continue;
1552                 }
1553
1554                 /* Put PE to the list */
1555                 mutex_lock(&phb->ioda.pe_list_mutex);
1556                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1557                 mutex_unlock(&phb->ioda.pe_list_mutex);
1558
1559                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1560         }
1561 }
1562
1563 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1564 {
1565         struct pci_bus        *bus;
1566         struct pci_controller *hose;
1567         struct pnv_phb        *phb;
1568         struct pnv_ioda_pe    *pe;
1569         struct pci_dn         *pdn;
1570         int                    ret;
1571         u16                    i;
1572
1573         bus = pdev->bus;
1574         hose = pci_bus_to_host(bus);
1575         phb = hose->private_data;
1576         pdn = pci_get_pdn(pdev);
1577
1578         if (phb->type == PNV_PHB_IODA2) {
1579                 if (!pdn->vfs_expanded) {
1580                         dev_info(&pdev->dev, "don't support this SRIOV device"
1581                                 " with non 64bit-prefetchable IOV BAR\n");
1582                         return -ENOSPC;
1583                 }
1584
1585                 /*
1586                  * When M64 BARs functions in Single PE mode, the number of VFs
1587                  * could be enabled must be less than the number of M64 BARs.
1588                  */
1589                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1590                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1591                         return -EBUSY;
1592                 }
1593
1594                 /* Allocating pe_num_map */
1595                 if (pdn->m64_single_mode)
1596                         pdn->pe_num_map = kmalloc_array(num_vfs,
1597                                                         sizeof(*pdn->pe_num_map),
1598                                                         GFP_KERNEL);
1599                 else
1600                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1601
1602                 if (!pdn->pe_num_map)
1603                         return -ENOMEM;
1604
1605                 if (pdn->m64_single_mode)
1606                         for (i = 0; i < num_vfs; i++)
1607                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1608
1609                 /* Calculate available PE for required VFs */
1610                 if (pdn->m64_single_mode) {
1611                         for (i = 0; i < num_vfs; i++) {
1612                                 pe = pnv_ioda_alloc_pe(phb);
1613                                 if (!pe) {
1614                                         ret = -EBUSY;
1615                                         goto m64_failed;
1616                                 }
1617
1618                                 pdn->pe_num_map[i] = pe->pe_number;
1619                         }
1620                 } else {
1621                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1622                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1623                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1624                                 0, num_vfs, 0);
1625                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1626                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1627                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1628                                 kfree(pdn->pe_num_map);
1629                                 return -EBUSY;
1630                         }
1631                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1632                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1633                 }
1634                 pdn->num_vfs = num_vfs;
1635
1636                 /* Assign M64 window accordingly */
1637                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1638                 if (ret) {
1639                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1640                         goto m64_failed;
1641                 }
1642
1643                 /*
1644                  * When using one M64 BAR to map one IOV BAR, we need to shift
1645                  * the IOV BAR according to the PE# allocated to the VFs.
1646                  * Otherwise, the PE# for the VF will conflict with others.
1647                  */
1648                 if (!pdn->m64_single_mode) {
1649                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1650                         if (ret)
1651                                 goto m64_failed;
1652                 }
1653         }
1654
1655         /* Setup VF PEs */
1656         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1657
1658         return 0;
1659
1660 m64_failed:
1661         if (pdn->m64_single_mode) {
1662                 for (i = 0; i < num_vfs; i++) {
1663                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1664                                 continue;
1665
1666                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1667                         pnv_ioda_free_pe(pe);
1668                 }
1669         } else
1670                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1671
1672         /* Releasing pe_num_map */
1673         kfree(pdn->pe_num_map);
1674
1675         return ret;
1676 }
1677
1678 int pcibios_sriov_disable(struct pci_dev *pdev)
1679 {
1680         pnv_pci_sriov_disable(pdev);
1681
1682         /* Release PCI data */
1683         remove_dev_pci_data(pdev);
1684         return 0;
1685 }
1686
1687 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1688 {
1689         /* Allocate PCI data */
1690         add_dev_pci_data(pdev);
1691
1692         return pnv_pci_sriov_enable(pdev, num_vfs);
1693 }
1694 #endif /* CONFIG_PCI_IOV */
1695
1696 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1697 {
1698         struct pci_dn *pdn = pci_get_pdn(pdev);
1699         struct pnv_ioda_pe *pe;
1700
1701         /*
1702          * The function can be called while the PE#
1703          * hasn't been assigned. Do nothing for the
1704          * case.
1705          */
1706         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1707                 return;
1708
1709         pe = &phb->ioda.pe_array[pdn->pe_number];
1710         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1711         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1712         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1713         /*
1714          * Note: iommu_add_device() will fail here as
1715          * for physical PE: the device is already added by now;
1716          * for virtual PE: sysfs entries are not ready yet and
1717          * tce_iommu_bus_notifier will add the device to a group later.
1718          */
1719 }
1720
1721 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1722 {
1723         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1724         struct pnv_phb *phb = hose->private_data;
1725         struct pci_dn *pdn = pci_get_pdn(pdev);
1726         struct pnv_ioda_pe *pe;
1727         uint64_t top;
1728         bool bypass = false;
1729
1730         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1731                 return -ENODEV;;
1732
1733         pe = &phb->ioda.pe_array[pdn->pe_number];
1734         if (pe->tce_bypass_enabled) {
1735                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1736                 bypass = (dma_mask >= top);
1737         }
1738
1739         if (bypass) {
1740                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1741                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1742         } else {
1743                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1744                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1745         }
1746         *pdev->dev.dma_mask = dma_mask;
1747
1748         /* Update peer npu devices */
1749         pnv_npu_try_dma_set_bypass(pdev, bypass);
1750
1751         return 0;
1752 }
1753
1754 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1755 {
1756         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1757         struct pnv_phb *phb = hose->private_data;
1758         struct pci_dn *pdn = pci_get_pdn(pdev);
1759         struct pnv_ioda_pe *pe;
1760         u64 end, mask;
1761
1762         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1763                 return 0;
1764
1765         pe = &phb->ioda.pe_array[pdn->pe_number];
1766         if (!pe->tce_bypass_enabled)
1767                 return __dma_get_required_mask(&pdev->dev);
1768
1769
1770         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1771         mask = 1ULL << (fls64(end) - 1);
1772         mask += mask - 1;
1773
1774         return mask;
1775 }
1776
1777 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1778                                    struct pci_bus *bus,
1779                                    bool add_to_group)
1780 {
1781         struct pci_dev *dev;
1782
1783         list_for_each_entry(dev, &bus->devices, bus_list) {
1784                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1785                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1786                 if (add_to_group)
1787                         iommu_add_device(&dev->dev);
1788
1789                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1790                         pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1791                                         add_to_group);
1792         }
1793 }
1794
1795 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1796                                                      bool real_mode)
1797 {
1798         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1799                 (phb->regs + 0x210);
1800 }
1801
1802 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1803                 unsigned long index, unsigned long npages, bool rm)
1804 {
1805         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1806                         &tbl->it_group_list, struct iommu_table_group_link,
1807                         next);
1808         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1809                         struct pnv_ioda_pe, table_group);
1810         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1811         unsigned long start, end, inc;
1812
1813         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1814         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1815                         npages - 1);
1816
1817         /* p7ioc-style invalidation, 2 TCEs per write */
1818         start |= (1ull << 63);
1819         end |= (1ull << 63);
1820         inc = 16;
1821         end |= inc - 1; /* round up end to be different than start */
1822
1823         mb(); /* Ensure above stores are visible */
1824         while (start <= end) {
1825                 if (rm)
1826                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1827                 else
1828                         __raw_writeq(cpu_to_be64(start), invalidate);
1829                 start += inc;
1830         }
1831
1832         /*
1833          * The iommu layer will do another mb() for us on build()
1834          * and we don't care on free()
1835          */
1836 }
1837
1838 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1839                 long npages, unsigned long uaddr,
1840                 enum dma_data_direction direction,
1841                 unsigned long attrs)
1842 {
1843         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1844                         attrs);
1845
1846         if (!ret)
1847                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1848
1849         return ret;
1850 }
1851
1852 #ifdef CONFIG_IOMMU_API
1853 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1854                 unsigned long *hpa, enum dma_data_direction *direction)
1855 {
1856         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1857
1858         if (!ret)
1859                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1860
1861         return ret;
1862 }
1863 #endif
1864
1865 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1866                 long npages)
1867 {
1868         pnv_tce_free(tbl, index, npages);
1869
1870         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1871 }
1872
1873 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1874         .set = pnv_ioda1_tce_build,
1875 #ifdef CONFIG_IOMMU_API
1876         .exchange = pnv_ioda1_tce_xchg,
1877 #endif
1878         .clear = pnv_ioda1_tce_free,
1879         .get = pnv_tce_get,
1880 };
1881
1882 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
1883 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
1884 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
1885
1886 void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1887 {
1888         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1889         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1890
1891         mb(); /* Ensure previous TCE table stores are visible */
1892         if (rm)
1893                 __raw_rm_writeq(cpu_to_be64(val), invalidate);
1894         else
1895                 __raw_writeq(cpu_to_be64(val), invalidate);
1896 }
1897
1898 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1899 {
1900         /* 01xb - invalidate TCEs that match the specified PE# */
1901         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1902         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1903
1904         mb(); /* Ensure above stores are visible */
1905         __raw_writeq(cpu_to_be64(val), invalidate);
1906 }
1907
1908 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1909                                         unsigned shift, unsigned long index,
1910                                         unsigned long npages)
1911 {
1912         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1913         unsigned long start, end, inc;
1914
1915         /* We'll invalidate DMA address in PE scope */
1916         start = PHB3_TCE_KILL_INVAL_ONE;
1917         start |= (pe->pe_number & 0xFF);
1918         end = start;
1919
1920         /* Figure out the start, end and step */
1921         start |= (index << shift);
1922         end |= ((index + npages - 1) << shift);
1923         inc = (0x1ull << shift);
1924         mb();
1925
1926         while (start <= end) {
1927                 if (rm)
1928                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1929                 else
1930                         __raw_writeq(cpu_to_be64(start), invalidate);
1931                 start += inc;
1932         }
1933 }
1934
1935 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1936 {
1937         struct pnv_phb *phb = pe->phb;
1938
1939         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1940                 pnv_pci_phb3_tce_invalidate_pe(pe);
1941         else
1942                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1943                                   pe->pe_number, 0, 0, 0);
1944 }
1945
1946 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1947                 unsigned long index, unsigned long npages, bool rm)
1948 {
1949         struct iommu_table_group_link *tgl;
1950
1951         list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1952                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1953                                 struct pnv_ioda_pe, table_group);
1954                 struct pnv_phb *phb = pe->phb;
1955                 unsigned int shift = tbl->it_page_shift;
1956
1957                 /*
1958                  * NVLink1 can use the TCE kill register directly as
1959                  * it's the same as PHB3. NVLink2 is different and
1960                  * should go via the OPAL call.
1961                  */
1962                 if (phb->model == PNV_PHB_MODEL_NPU) {
1963                         /*
1964                          * The NVLink hardware does not support TCE kill
1965                          * per TCE entry so we have to invalidate
1966                          * the entire cache for it.
1967                          */
1968                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1969                         continue;
1970                 }
1971                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1972                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1973                                                     index, npages);
1974                 else
1975                         opal_pci_tce_kill(phb->opal_id,
1976                                           OPAL_PCI_TCE_KILL_PAGES,
1977                                           pe->pe_number, 1u << shift,
1978                                           index << shift, npages);
1979         }
1980 }
1981
1982 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1983                 long npages, unsigned long uaddr,
1984                 enum dma_data_direction direction,
1985                 unsigned long attrs)
1986 {
1987         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1988                         attrs);
1989
1990         if (!ret)
1991                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1992
1993         return ret;
1994 }
1995
1996 #ifdef CONFIG_IOMMU_API
1997 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1998                 unsigned long *hpa, enum dma_data_direction *direction)
1999 {
2000         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2001
2002         if (!ret)
2003                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2004
2005         return ret;
2006 }
2007 #endif
2008
2009 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2010                 long npages)
2011 {
2012         pnv_tce_free(tbl, index, npages);
2013
2014         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2015 }
2016
2017 static void pnv_ioda2_table_free(struct iommu_table *tbl)
2018 {
2019         pnv_pci_ioda2_table_free_pages(tbl);
2020         iommu_free_table(tbl, "pnv");
2021 }
2022
2023 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2024         .set = pnv_ioda2_tce_build,
2025 #ifdef CONFIG_IOMMU_API
2026         .exchange = pnv_ioda2_tce_xchg,
2027 #endif
2028         .clear = pnv_ioda2_tce_free,
2029         .get = pnv_tce_get,
2030         .free = pnv_ioda2_table_free,
2031 };
2032
2033 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2034 {
2035         unsigned int *weight = (unsigned int *)data;
2036
2037         /* This is quite simplistic. The "base" weight of a device
2038          * is 10. 0 means no DMA is to be accounted for it.
2039          */
2040         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2041                 return 0;
2042
2043         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2044             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2045             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2046                 *weight += 3;
2047         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2048                 *weight += 15;
2049         else
2050                 *weight += 10;
2051
2052         return 0;
2053 }
2054
2055 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2056 {
2057         unsigned int weight = 0;
2058
2059         /* SRIOV VF has same DMA32 weight as its PF */
2060 #ifdef CONFIG_PCI_IOV
2061         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2062                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2063                 return weight;
2064         }
2065 #endif
2066
2067         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2068                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2069         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2070                 struct pci_dev *pdev;
2071
2072                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2073                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2074         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2075                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2076         }
2077
2078         return weight;
2079 }
2080
2081 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2082                                        struct pnv_ioda_pe *pe)
2083 {
2084
2085         struct page *tce_mem = NULL;
2086         struct iommu_table *tbl;
2087         unsigned int weight, total_weight = 0;
2088         unsigned int tce32_segsz, base, segs, avail, i;
2089         int64_t rc;
2090         void *addr;
2091
2092         /* XXX FIXME: Handle 64-bit only DMA devices */
2093         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2094         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2095         weight = pnv_pci_ioda_pe_dma_weight(pe);
2096         if (!weight)
2097                 return;
2098
2099         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2100                      &total_weight);
2101         segs = (weight * phb->ioda.dma32_count) / total_weight;
2102         if (!segs)
2103                 segs = 1;
2104
2105         /*
2106          * Allocate contiguous DMA32 segments. We begin with the expected
2107          * number of segments. With one more attempt, the number of DMA32
2108          * segments to be allocated is decreased by one until one segment
2109          * is allocated successfully.
2110          */
2111         do {
2112                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2113                         for (avail = 0, i = base; i < base + segs; i++) {
2114                                 if (phb->ioda.dma32_segmap[i] ==
2115                                     IODA_INVALID_PE)
2116                                         avail++;
2117                         }
2118
2119                         if (avail == segs)
2120                                 goto found;
2121                 }
2122         } while (--segs);
2123
2124         if (!segs) {
2125                 pe_warn(pe, "No available DMA32 segments\n");
2126                 return;
2127         }
2128
2129 found:
2130         tbl = pnv_pci_table_alloc(phb->hose->node);
2131         iommu_register_group(&pe->table_group, phb->hose->global_number,
2132                         pe->pe_number);
2133         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2134
2135         /* Grab a 32-bit TCE table */
2136         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2137                 weight, total_weight, base, segs);
2138         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2139                 base * PNV_IODA1_DMA32_SEGSIZE,
2140                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2141
2142         /* XXX Currently, we allocate one big contiguous table for the
2143          * TCEs. We only really need one chunk per 256M of TCE space
2144          * (ie per segment) but that's an optimization for later, it
2145          * requires some added smarts with our get/put_tce implementation
2146          *
2147          * Each TCE page is 4KB in size and each TCE entry occupies 8
2148          * bytes
2149          */
2150         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2151         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2152                                    get_order(tce32_segsz * segs));
2153         if (!tce_mem) {
2154                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2155                 goto fail;
2156         }
2157         addr = page_address(tce_mem);
2158         memset(addr, 0, tce32_segsz * segs);
2159
2160         /* Configure HW */
2161         for (i = 0; i < segs; i++) {
2162                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2163                                               pe->pe_number,
2164                                               base + i, 1,
2165                                               __pa(addr) + tce32_segsz * i,
2166                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2167                 if (rc) {
2168                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2169                                " err %ld\n", rc);
2170                         goto fail;
2171                 }
2172         }
2173
2174         /* Setup DMA32 segment mapping */
2175         for (i = base; i < base + segs; i++)
2176                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2177
2178         /* Setup linux iommu table */
2179         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2180                                   base * PNV_IODA1_DMA32_SEGSIZE,
2181                                   IOMMU_PAGE_SHIFT_4K);
2182
2183         tbl->it_ops = &pnv_ioda1_iommu_ops;
2184         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2185         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2186         iommu_init_table(tbl, phb->hose->node);
2187
2188         if (pe->flags & PNV_IODA_PE_DEV) {
2189                 /*
2190                  * Setting table base here only for carrying iommu_group
2191                  * further down to let iommu_add_device() do the job.
2192                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2193                  */
2194                 set_iommu_table_base(&pe->pdev->dev, tbl);
2195                 iommu_add_device(&pe->pdev->dev);
2196         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2197                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2198
2199         return;
2200  fail:
2201         /* XXX Failure: Try to fallback to 64-bit only ? */
2202         if (tce_mem)
2203                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2204         if (tbl) {
2205                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2206                 iommu_free_table(tbl, "pnv");
2207         }
2208 }
2209
2210 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2211                 int num, struct iommu_table *tbl)
2212 {
2213         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2214                         table_group);
2215         struct pnv_phb *phb = pe->phb;
2216         int64_t rc;
2217         const unsigned long size = tbl->it_indirect_levels ?
2218                         tbl->it_level_size : tbl->it_size;
2219         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2220         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2221
2222         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2223                         start_addr, start_addr + win_size - 1,
2224                         IOMMU_PAGE_SIZE(tbl));
2225
2226         /*
2227          * Map TCE table through TVT. The TVE index is the PE number
2228          * shifted by 1 bit for 32-bits DMA space.
2229          */
2230         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2231                         pe->pe_number,
2232                         (pe->pe_number << 1) + num,
2233                         tbl->it_indirect_levels + 1,
2234                         __pa(tbl->it_base),
2235                         size << 3,
2236                         IOMMU_PAGE_SIZE(tbl));
2237         if (rc) {
2238                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2239                 return rc;
2240         }
2241
2242         pnv_pci_link_table_and_group(phb->hose->node, num,
2243                         tbl, &pe->table_group);
2244         pnv_pci_ioda2_tce_invalidate_pe(pe);
2245
2246         return 0;
2247 }
2248
2249 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2250 {
2251         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2252         int64_t rc;
2253
2254         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2255         if (enable) {
2256                 phys_addr_t top = memblock_end_of_DRAM();
2257
2258                 top = roundup_pow_of_two(top);
2259                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2260                                                      pe->pe_number,
2261                                                      window_id,
2262                                                      pe->tce_bypass_base,
2263                                                      top);
2264         } else {
2265                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2266                                                      pe->pe_number,
2267                                                      window_id,
2268                                                      pe->tce_bypass_base,
2269                                                      0);
2270         }
2271         if (rc)
2272                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2273         else
2274                 pe->tce_bypass_enabled = enable;
2275 }
2276
2277 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2278                 __u32 page_shift, __u64 window_size, __u32 levels,
2279                 struct iommu_table *tbl);
2280
2281 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2282                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2283                 struct iommu_table **ptbl)
2284 {
2285         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2286                         table_group);
2287         int nid = pe->phb->hose->node;
2288         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2289         long ret;
2290         struct iommu_table *tbl;
2291
2292         tbl = pnv_pci_table_alloc(nid);
2293         if (!tbl)
2294                 return -ENOMEM;
2295
2296         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2297                         bus_offset, page_shift, window_size,
2298                         levels, tbl);
2299         if (ret) {
2300                 iommu_free_table(tbl, "pnv");
2301                 return ret;
2302         }
2303
2304         tbl->it_ops = &pnv_ioda2_iommu_ops;
2305
2306         *ptbl = tbl;
2307
2308         return 0;
2309 }
2310
2311 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2312 {
2313         struct iommu_table *tbl = NULL;
2314         long rc;
2315
2316         /*
2317          * crashkernel= specifies the kdump kernel's maximum memory at
2318          * some offset and there is no guaranteed the result is a power
2319          * of 2, which will cause errors later.
2320          */
2321         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2322
2323         /*
2324          * In memory constrained environments, e.g. kdump kernel, the
2325          * DMA window can be larger than available memory, which will
2326          * cause errors later.
2327          */
2328         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2329
2330         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2331                         IOMMU_PAGE_SHIFT_4K,
2332                         window_size,
2333                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2334         if (rc) {
2335                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2336                                 rc);
2337                 return rc;
2338         }
2339
2340         iommu_init_table(tbl, pe->phb->hose->node);
2341
2342         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2343         if (rc) {
2344                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2345                                 rc);
2346                 pnv_ioda2_table_free(tbl);
2347                 return rc;
2348         }
2349
2350         if (!pnv_iommu_bypass_disabled)
2351                 pnv_pci_ioda2_set_bypass(pe, true);
2352
2353         /*
2354          * Setting table base here only for carrying iommu_group
2355          * further down to let iommu_add_device() do the job.
2356          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2357          */
2358         if (pe->flags & PNV_IODA_PE_DEV)
2359                 set_iommu_table_base(&pe->pdev->dev, tbl);
2360
2361         return 0;
2362 }
2363
2364 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2365 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2366                 int num)
2367 {
2368         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2369                         table_group);
2370         struct pnv_phb *phb = pe->phb;
2371         long ret;
2372
2373         pe_info(pe, "Removing DMA window #%d\n", num);
2374
2375         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2376                         (pe->pe_number << 1) + num,
2377                         0/* levels */, 0/* table address */,
2378                         0/* table size */, 0/* page size */);
2379         if (ret)
2380                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2381         else
2382                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2383
2384         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2385
2386         return ret;
2387 }
2388 #endif
2389
2390 #ifdef CONFIG_IOMMU_API
2391 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2392                 __u64 window_size, __u32 levels)
2393 {
2394         unsigned long bytes = 0;
2395         const unsigned window_shift = ilog2(window_size);
2396         unsigned entries_shift = window_shift - page_shift;
2397         unsigned table_shift = entries_shift + 3;
2398         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2399         unsigned long direct_table_size;
2400
2401         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2402                         (window_size > memory_hotplug_max()) ||
2403                         !is_power_of_2(window_size))
2404                 return 0;
2405
2406         /* Calculate a direct table size from window_size and levels */
2407         entries_shift = (entries_shift + levels - 1) / levels;
2408         table_shift = entries_shift + 3;
2409         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2410         direct_table_size =  1UL << table_shift;
2411
2412         for ( ; levels; --levels) {
2413                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2414
2415                 tce_table_size /= direct_table_size;
2416                 tce_table_size <<= 3;
2417                 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2418         }
2419
2420         return bytes;
2421 }
2422
2423 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2424 {
2425         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2426                                                 table_group);
2427         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2428         struct iommu_table *tbl = pe->table_group.tables[0];
2429
2430         pnv_pci_ioda2_set_bypass(pe, false);
2431         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2432         if (pe->pbus)
2433                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2434         pnv_ioda2_table_free(tbl);
2435 }
2436
2437 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2438 {
2439         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2440                                                 table_group);
2441
2442         pnv_pci_ioda2_setup_default_config(pe);
2443         if (pe->pbus)
2444                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2445 }
2446
2447 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2448         .get_table_size = pnv_pci_ioda2_get_table_size,
2449         .create_table = pnv_pci_ioda2_create_table,
2450         .set_window = pnv_pci_ioda2_set_window,
2451         .unset_window = pnv_pci_ioda2_unset_window,
2452         .take_ownership = pnv_ioda2_take_ownership,
2453         .release_ownership = pnv_ioda2_release_ownership,
2454 };
2455
2456 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2457 {
2458         struct pci_controller *hose;
2459         struct pnv_phb *phb;
2460         struct pnv_ioda_pe **ptmppe = opaque;
2461         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2462         struct pci_dn *pdn = pci_get_pdn(pdev);
2463
2464         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2465                 return 0;
2466
2467         hose = pci_bus_to_host(pdev->bus);
2468         phb = hose->private_data;
2469         if (phb->type != PNV_PHB_NPU)
2470                 return 0;
2471
2472         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2473
2474         return 1;
2475 }
2476
2477 /*
2478  * This returns PE of associated NPU.
2479  * This assumes that NPU is in the same IOMMU group with GPU and there is
2480  * no other PEs.
2481  */
2482 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2483                 struct iommu_table_group *table_group)
2484 {
2485         struct pnv_ioda_pe *npe = NULL;
2486         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2487                         gpe_table_group_to_npe_cb);
2488
2489         BUG_ON(!ret || !npe);
2490
2491         return npe;
2492 }
2493
2494 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2495                 int num, struct iommu_table *tbl)
2496 {
2497         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2498
2499         if (ret)
2500                 return ret;
2501
2502         ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2503         if (ret)
2504                 pnv_pci_ioda2_unset_window(table_group, num);
2505
2506         return ret;
2507 }
2508
2509 static long pnv_pci_ioda2_npu_unset_window(
2510                 struct iommu_table_group *table_group,
2511                 int num)
2512 {
2513         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2514
2515         if (ret)
2516                 return ret;
2517
2518         return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2519 }
2520
2521 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2522 {
2523         /*
2524          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2525          * the iommu_table if 32bit DMA is enabled.
2526          */
2527         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2528         pnv_ioda2_take_ownership(table_group);
2529 }
2530
2531 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2532         .get_table_size = pnv_pci_ioda2_get_table_size,
2533         .create_table = pnv_pci_ioda2_create_table,
2534         .set_window = pnv_pci_ioda2_npu_set_window,
2535         .unset_window = pnv_pci_ioda2_npu_unset_window,
2536         .take_ownership = pnv_ioda2_npu_take_ownership,
2537         .release_ownership = pnv_ioda2_release_ownership,
2538 };
2539
2540 static void pnv_pci_ioda_setup_iommu_api(void)
2541 {
2542         struct pci_controller *hose, *tmp;
2543         struct pnv_phb *phb;
2544         struct pnv_ioda_pe *pe, *gpe;
2545
2546         /*
2547          * Now we have all PHBs discovered, time to add NPU devices to
2548          * the corresponding IOMMU groups.
2549          */
2550         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2551                 phb = hose->private_data;
2552
2553                 if (phb->type != PNV_PHB_NPU)
2554                         continue;
2555
2556                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2557                         gpe = pnv_pci_npu_setup_iommu(pe);
2558                         if (gpe)
2559                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2560                 }
2561         }
2562 }
2563 #else /* !CONFIG_IOMMU_API */
2564 static void pnv_pci_ioda_setup_iommu_api(void) { };
2565 #endif
2566
2567 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2568                 unsigned levels, unsigned long limit,
2569                 unsigned long *current_offset, unsigned long *total_allocated)
2570 {
2571         struct page *tce_mem = NULL;
2572         __be64 *addr, *tmp;
2573         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2574         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2575         unsigned entries = 1UL << (shift - 3);
2576         long i;
2577
2578         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2579         if (!tce_mem) {
2580                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2581                 return NULL;
2582         }
2583         addr = page_address(tce_mem);
2584         memset(addr, 0, allocated);
2585         *total_allocated += allocated;
2586
2587         --levels;
2588         if (!levels) {
2589                 *current_offset += allocated;
2590                 return addr;
2591         }
2592
2593         for (i = 0; i < entries; ++i) {
2594                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2595                                 levels, limit, current_offset, total_allocated);
2596                 if (!tmp)
2597                         break;
2598
2599                 addr[i] = cpu_to_be64(__pa(tmp) |
2600                                 TCE_PCI_READ | TCE_PCI_WRITE);
2601
2602                 if (*current_offset >= limit)
2603                         break;
2604         }
2605
2606         return addr;
2607 }
2608
2609 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2610                 unsigned long size, unsigned level);
2611
2612 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2613                 __u32 page_shift, __u64 window_size, __u32 levels,
2614                 struct iommu_table *tbl)
2615 {
2616         void *addr;
2617         unsigned long offset = 0, level_shift, total_allocated = 0;
2618         const unsigned window_shift = ilog2(window_size);
2619         unsigned entries_shift = window_shift - page_shift;
2620         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2621         const unsigned long tce_table_size = 1UL << table_shift;
2622
2623         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2624                 return -EINVAL;
2625
2626         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2627                 return -EINVAL;
2628
2629         /* Adjust direct table size from window_size and levels */
2630         entries_shift = (entries_shift + levels - 1) / levels;
2631         level_shift = entries_shift + 3;
2632         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2633
2634         if ((level_shift - 3) * levels + page_shift >= 60)
2635                 return -EINVAL;
2636
2637         /* Allocate TCE table */
2638         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2639                         levels, tce_table_size, &offset, &total_allocated);
2640
2641         /* addr==NULL means that the first level allocation failed */
2642         if (!addr)
2643                 return -ENOMEM;
2644
2645         /*
2646          * First level was allocated but some lower level failed as
2647          * we did not allocate as much as we wanted,
2648          * release partially allocated table.
2649          */
2650         if (offset < tce_table_size) {
2651                 pnv_pci_ioda2_table_do_free_pages(addr,
2652                                 1ULL << (level_shift - 3), levels - 1);
2653                 return -ENOMEM;
2654         }
2655
2656         /* Setup linux iommu table */
2657         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2658                         page_shift);
2659         tbl->it_level_size = 1ULL << (level_shift - 3);
2660         tbl->it_indirect_levels = levels - 1;
2661         tbl->it_allocated_size = total_allocated;
2662
2663         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2664                         window_size, tce_table_size, bus_offset);
2665
2666         return 0;
2667 }
2668
2669 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2670                 unsigned long size, unsigned level)
2671 {
2672         const unsigned long addr_ul = (unsigned long) addr &
2673                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2674
2675         if (level) {
2676                 long i;
2677                 u64 *tmp = (u64 *) addr_ul;
2678
2679                 for (i = 0; i < size; ++i) {
2680                         unsigned long hpa = be64_to_cpu(tmp[i]);
2681
2682                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2683                                 continue;
2684
2685                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2686                                         level - 1);
2687                 }
2688         }
2689
2690         free_pages(addr_ul, get_order(size << 3));
2691 }
2692
2693 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2694 {
2695         const unsigned long size = tbl->it_indirect_levels ?
2696                         tbl->it_level_size : tbl->it_size;
2697
2698         if (!tbl->it_size)
2699                 return;
2700
2701         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2702                         tbl->it_indirect_levels);
2703 }
2704
2705 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2706                                        struct pnv_ioda_pe *pe)
2707 {
2708         int64_t rc;
2709
2710         if (!pnv_pci_ioda_pe_dma_weight(pe))
2711                 return;
2712
2713         /* TVE #1 is selected by PCI address bit 59 */
2714         pe->tce_bypass_base = 1ull << 59;
2715
2716         iommu_register_group(&pe->table_group, phb->hose->global_number,
2717                         pe->pe_number);
2718
2719         /* The PE will reserve all possible 32-bits space */
2720         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2721                 phb->ioda.m32_pci_base);
2722
2723         /* Setup linux iommu table */
2724         pe->table_group.tce32_start = 0;
2725         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2726         pe->table_group.max_dynamic_windows_supported =
2727                         IOMMU_TABLE_GROUP_MAX_TABLES;
2728         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2729         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2730 #ifdef CONFIG_IOMMU_API
2731         pe->table_group.ops = &pnv_pci_ioda2_ops;
2732 #endif
2733
2734         rc = pnv_pci_ioda2_setup_default_config(pe);
2735         if (rc)
2736                 return;
2737
2738         if (pe->flags & PNV_IODA_PE_DEV)
2739                 iommu_add_device(&pe->pdev->dev);
2740         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2741                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2742 }
2743
2744 #ifdef CONFIG_PCI_MSI
2745 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2746 {
2747         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2748                                            ioda.irq_chip);
2749
2750         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2751 }
2752
2753 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2754 {
2755         int64_t rc;
2756         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2757         struct irq_chip *chip = irq_data_get_irq_chip(d);
2758
2759         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2760         WARN_ON_ONCE(rc);
2761
2762         icp_native_eoi(d);
2763 }
2764
2765
2766 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2767 {
2768         struct irq_data *idata;
2769         struct irq_chip *ichip;
2770
2771         /* The MSI EOI OPAL call is only needed on PHB3 */
2772         if (phb->model != PNV_PHB_MODEL_PHB3)
2773                 return;
2774
2775         if (!phb->ioda.irq_chip_init) {
2776                 /*
2777                  * First time we setup an MSI IRQ, we need to setup the
2778                  * corresponding IRQ chip to route correctly.
2779                  */
2780                 idata = irq_get_irq_data(virq);
2781                 ichip = irq_data_get_irq_chip(idata);
2782                 phb->ioda.irq_chip_init = 1;
2783                 phb->ioda.irq_chip = *ichip;
2784                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2785         }
2786         irq_set_chip(virq, &phb->ioda.irq_chip);
2787 }
2788
2789 /*
2790  * Returns true iff chip is something that we could call
2791  * pnv_opal_pci_msi_eoi for.
2792  */
2793 bool is_pnv_opal_msi(struct irq_chip *chip)
2794 {
2795         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2796 }
2797 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2798
2799 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2800                                   unsigned int hwirq, unsigned int virq,
2801                                   unsigned int is_64, struct msi_msg *msg)
2802 {
2803         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2804         unsigned int xive_num = hwirq - phb->msi_base;
2805         __be32 data;
2806         int rc;
2807
2808         /* No PE assigned ? bail out ... no MSI for you ! */
2809         if (pe == NULL)
2810                 return -ENXIO;
2811
2812         /* Check if we have an MVE */
2813         if (pe->mve_number < 0)
2814                 return -ENXIO;
2815
2816         /* Force 32-bit MSI on some broken devices */
2817         if (dev->no_64bit_msi)
2818                 is_64 = 0;
2819
2820         /* Assign XIVE to PE */
2821         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2822         if (rc) {
2823                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2824                         pci_name(dev), rc, xive_num);
2825                 return -EIO;
2826         }
2827
2828         if (is_64) {
2829                 __be64 addr64;
2830
2831                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2832                                      &addr64, &data);
2833                 if (rc) {
2834                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2835                                 pci_name(dev), rc);
2836                         return -EIO;
2837                 }
2838                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2839                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2840         } else {
2841                 __be32 addr32;
2842
2843                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2844                                      &addr32, &data);
2845                 if (rc) {
2846                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2847                                 pci_name(dev), rc);
2848                         return -EIO;
2849                 }
2850                 msg->address_hi = 0;
2851                 msg->address_lo = be32_to_cpu(addr32);
2852         }
2853         msg->data = be32_to_cpu(data);
2854
2855         pnv_set_msi_irq_chip(phb, virq);
2856
2857         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2858                  " address=%x_%08x data=%x PE# %x\n",
2859                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2860                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2861
2862         return 0;
2863 }
2864
2865 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2866 {
2867         unsigned int count;
2868         const __be32 *prop = of_get_property(phb->hose->dn,
2869                                              "ibm,opal-msi-ranges", NULL);
2870         if (!prop) {
2871                 /* BML Fallback */
2872                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2873         }
2874         if (!prop)
2875                 return;
2876
2877         phb->msi_base = be32_to_cpup(prop);
2878         count = be32_to_cpup(prop + 1);
2879         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2880                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2881                        phb->hose->global_number);
2882                 return;
2883         }
2884
2885         phb->msi_setup = pnv_pci_ioda_msi_setup;
2886         phb->msi32_support = 1;
2887         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2888                 count, phb->msi_base);
2889 }
2890 #else
2891 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2892 #endif /* CONFIG_PCI_MSI */
2893
2894 #ifdef CONFIG_PCI_IOV
2895 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2896 {
2897         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2898         struct pnv_phb *phb = hose->private_data;
2899         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2900         struct resource *res;
2901         int i;
2902         resource_size_t size, total_vf_bar_sz;
2903         struct pci_dn *pdn;
2904         int mul, total_vfs;
2905
2906         if (!pdev->is_physfn || pdev->is_added)
2907                 return;
2908
2909         pdn = pci_get_pdn(pdev);
2910         pdn->vfs_expanded = 0;
2911         pdn->m64_single_mode = false;
2912
2913         total_vfs = pci_sriov_get_totalvfs(pdev);
2914         mul = phb->ioda.total_pe_num;
2915         total_vf_bar_sz = 0;
2916
2917         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2918                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2919                 if (!res->flags || res->parent)
2920                         continue;
2921                 if (!pnv_pci_is_m64_flags(res->flags)) {
2922                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
2923                                         " non M64 VF BAR%d: %pR. \n",
2924                                  i, res);
2925                         goto truncate_iov;
2926                 }
2927
2928                 total_vf_bar_sz += pci_iov_resource_size(pdev,
2929                                 i + PCI_IOV_RESOURCES);
2930
2931                 /*
2932                  * If bigger than quarter of M64 segment size, just round up
2933                  * power of two.
2934                  *
2935                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2936                  * with other devices, IOV BAR size is expanded to be
2937                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2938                  * segment size , the expanded size would equal to half of the
2939                  * whole M64 space size, which will exhaust the M64 Space and
2940                  * limit the system flexibility.  This is a design decision to
2941                  * set the boundary to quarter of the M64 segment size.
2942                  */
2943                 if (total_vf_bar_sz > gate) {
2944                         mul = roundup_pow_of_two(total_vfs);
2945                         dev_info(&pdev->dev,
2946                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2947                                 total_vf_bar_sz, gate, mul);
2948                         pdn->m64_single_mode = true;
2949                         break;
2950                 }
2951         }
2952
2953         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2954                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2955                 if (!res->flags || res->parent)
2956                         continue;
2957
2958                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2959                 /*
2960                  * On PHB3, the minimum size alignment of M64 BAR in single
2961                  * mode is 32MB.
2962                  */
2963                 if (pdn->m64_single_mode && (size < SZ_32M))
2964                         goto truncate_iov;
2965                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2966                 res->end = res->start + size * mul - 1;
2967                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2968                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2969                          i, res, mul);
2970         }
2971         pdn->vfs_expanded = mul;
2972
2973         return;
2974
2975 truncate_iov:
2976         /* To save MMIO space, IOV BAR is truncated. */
2977         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2978                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2979                 res->flags = 0;
2980                 res->end = res->start - 1;
2981         }
2982 }
2983 #endif /* CONFIG_PCI_IOV */
2984
2985 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2986                                   struct resource *res)
2987 {
2988         struct pnv_phb *phb = pe->phb;
2989         struct pci_bus_region region;
2990         int index;
2991         int64_t rc;
2992
2993         if (!res || !res->flags || res->start > res->end)
2994                 return;
2995
2996         if (res->flags & IORESOURCE_IO) {
2997                 region.start = res->start - phb->ioda.io_pci_base;
2998                 region.end   = res->end - phb->ioda.io_pci_base;
2999                 index = region.start / phb->ioda.io_segsize;
3000
3001                 while (index < phb->ioda.total_pe_num &&
3002                        region.start <= region.end) {
3003                         phb->ioda.io_segmap[index] = pe->pe_number;
3004                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3005                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3006                         if (rc != OPAL_SUCCESS) {
3007                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3008                                        __func__, rc, index, pe->pe_number);
3009                                 break;
3010                         }
3011
3012                         region.start += phb->ioda.io_segsize;
3013                         index++;
3014                 }
3015         } else if ((res->flags & IORESOURCE_MEM) &&
3016                    !pnv_pci_is_m64(phb, res)) {
3017                 region.start = res->start -
3018                                phb->hose->mem_offset[0] -
3019                                phb->ioda.m32_pci_base;
3020                 region.end   = res->end -
3021                                phb->hose->mem_offset[0] -
3022                                phb->ioda.m32_pci_base;
3023                 index = region.start / phb->ioda.m32_segsize;
3024
3025                 while (index < phb->ioda.total_pe_num &&
3026                        region.start <= region.end) {
3027                         phb->ioda.m32_segmap[index] = pe->pe_number;
3028                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3029                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3030                         if (rc != OPAL_SUCCESS) {
3031                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3032                                        __func__, rc, index, pe->pe_number);
3033                                 break;
3034                         }
3035
3036                         region.start += phb->ioda.m32_segsize;
3037                         index++;
3038                 }
3039         }
3040 }
3041
3042 /*
3043  * This function is supposed to be called on basis of PE from top
3044  * to bottom style. So the the I/O or MMIO segment assigned to
3045  * parent PE could be overridden by its child PEs if necessary.
3046  */
3047 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3048 {
3049         struct pci_dev *pdev;
3050         int i;
3051
3052         /*
3053          * NOTE: We only care PCI bus based PE for now. For PCI
3054          * device based PE, for example SRIOV sensitive VF should
3055          * be figured out later.
3056          */
3057         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3058
3059         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3060                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3061                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3062
3063                 /*
3064                  * If the PE contains all subordinate PCI buses, the
3065                  * windows of the child bridges should be mapped to
3066                  * the PE as well.
3067                  */
3068                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3069                         continue;
3070                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3071                         pnv_ioda_setup_pe_res(pe,
3072                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3073         }
3074 }
3075
3076 #ifdef CONFIG_DEBUG_FS
3077 static int pnv_pci_diag_data_set(void *data, u64 val)
3078 {
3079         struct pci_controller *hose;
3080         struct pnv_phb *phb;
3081         s64 ret;
3082
3083         if (val != 1ULL)
3084                 return -EINVAL;
3085
3086         hose = (struct pci_controller *)data;
3087         if (!hose || !hose->private_data)
3088                 return -ENODEV;
3089
3090         phb = hose->private_data;
3091
3092         /* Retrieve the diag data from firmware */
3093         ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
3094                                           PNV_PCI_DIAG_BUF_SIZE);
3095         if (ret != OPAL_SUCCESS)
3096                 return -EIO;
3097
3098         /* Print the diag data to the kernel log */
3099         pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
3100         return 0;
3101 }
3102
3103 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3104                         pnv_pci_diag_data_set, "%llu\n");
3105
3106 #endif /* CONFIG_DEBUG_FS */
3107
3108 static void pnv_pci_ioda_create_dbgfs(void)
3109 {
3110 #ifdef CONFIG_DEBUG_FS
3111         struct pci_controller *hose, *tmp;
3112         struct pnv_phb *phb;
3113         char name[16];
3114
3115         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3116                 phb = hose->private_data;
3117
3118                 /* Notify initialization of PHB done */
3119                 phb->initialized = 1;
3120
3121                 sprintf(name, "PCI%04x", hose->global_number);
3122                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3123                 if (!phb->dbgfs) {
3124                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3125                                 __func__, hose->global_number);
3126                         continue;
3127                 }
3128
3129                 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3130                                     &pnv_pci_diag_data_fops);
3131         }
3132 #endif /* CONFIG_DEBUG_FS */
3133 }
3134
3135 static void pnv_pci_ioda_fixup(void)
3136 {
3137         pnv_pci_ioda_setup_PEs();
3138         pnv_pci_ioda_setup_iommu_api();
3139         pnv_pci_ioda_create_dbgfs();
3140
3141 #ifdef CONFIG_EEH
3142         eeh_init();
3143         eeh_addr_cache_build();
3144 #endif
3145 }
3146
3147 /*
3148  * Returns the alignment for I/O or memory windows for P2P
3149  * bridges. That actually depends on how PEs are segmented.
3150  * For now, we return I/O or M32 segment size for PE sensitive
3151  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3152  * 1MiB for memory) will be returned.
3153  *
3154  * The current PCI bus might be put into one PE, which was
3155  * create against the parent PCI bridge. For that case, we
3156  * needn't enlarge the alignment so that we can save some
3157  * resources.
3158  */
3159 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3160                                                 unsigned long type)
3161 {
3162         struct pci_dev *bridge;
3163         struct pci_controller *hose = pci_bus_to_host(bus);
3164         struct pnv_phb *phb = hose->private_data;
3165         int num_pci_bridges = 0;
3166
3167         bridge = bus->self;
3168         while (bridge) {
3169                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3170                         num_pci_bridges++;
3171                         if (num_pci_bridges >= 2)
3172                                 return 1;
3173                 }
3174
3175                 bridge = bridge->bus->self;
3176         }
3177
3178         /*
3179          * We fall back to M32 if M64 isn't supported. We enforce the M64
3180          * alignment for any 64-bit resource, PCIe doesn't care and
3181          * bridges only do 64-bit prefetchable anyway.
3182          */
3183         if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3184                 return phb->ioda.m64_segsize;
3185         if (type & IORESOURCE_MEM)
3186                 return phb->ioda.m32_segsize;
3187
3188         return phb->ioda.io_segsize;
3189 }
3190
3191 /*
3192  * We are updating root port or the upstream port of the
3193  * bridge behind the root port with PHB's windows in order
3194  * to accommodate the changes on required resources during
3195  * PCI (slot) hotplug, which is connected to either root
3196  * port or the downstream ports of PCIe switch behind the
3197  * root port.
3198  */
3199 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3200                                            unsigned long type)
3201 {
3202         struct pci_controller *hose = pci_bus_to_host(bus);
3203         struct pnv_phb *phb = hose->private_data;
3204         struct pci_dev *bridge = bus->self;
3205         struct resource *r, *w;
3206         bool msi_region = false;
3207         int i;
3208
3209         /* Check if we need apply fixup to the bridge's windows */
3210         if (!pci_is_root_bus(bridge->bus) &&
3211             !pci_is_root_bus(bridge->bus->self->bus))
3212                 return;
3213
3214         /* Fixup the resources */
3215         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3216                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3217                 if (!r->flags || !r->parent)
3218                         continue;
3219
3220                 w = NULL;
3221                 if (r->flags & type & IORESOURCE_IO)
3222                         w = &hose->io_resource;
3223                 else if (pnv_pci_is_m64(phb, r) &&
3224                          (type & IORESOURCE_PREFETCH) &&
3225                          phb->ioda.m64_segsize)
3226                         w = &hose->mem_resources[1];
3227                 else if (r->flags & type & IORESOURCE_MEM) {
3228                         w = &hose->mem_resources[0];
3229                         msi_region = true;
3230                 }
3231
3232                 r->start = w->start;
3233                 r->end = w->end;
3234
3235                 /* The 64KB 32-bits MSI region shouldn't be included in
3236                  * the 32-bits bridge window. Otherwise, we can see strange
3237                  * issues. One of them is EEH error observed on Garrison.
3238                  *
3239                  * Exclude top 1MB region which is the minimal alignment of
3240                  * 32-bits bridge window.
3241                  */
3242                 if (msi_region) {
3243                         r->end += 0x10000;
3244                         r->end -= 0x100000;
3245                 }
3246         }
3247 }
3248
3249 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3250 {
3251         struct pci_controller *hose = pci_bus_to_host(bus);
3252         struct pnv_phb *phb = hose->private_data;
3253         struct pci_dev *bridge = bus->self;
3254         struct pnv_ioda_pe *pe;
3255         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3256
3257         /* Extend bridge's windows if necessary */
3258         pnv_pci_fixup_bridge_resources(bus, type);
3259
3260         /* The PE for root bus should be realized before any one else */
3261         if (!phb->ioda.root_pe_populated) {
3262                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3263                 if (pe) {
3264                         phb->ioda.root_pe_idx = pe->pe_number;
3265                         phb->ioda.root_pe_populated = true;
3266                 }
3267         }
3268
3269         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3270         if (list_empty(&bus->devices))
3271                 return;
3272
3273         /* Reserve PEs according to used M64 resources */
3274         if (phb->reserve_m64_pe)
3275                 phb->reserve_m64_pe(bus, NULL, all);
3276
3277         /*
3278          * Assign PE. We might run here because of partial hotplug.
3279          * For the case, we just pick up the existing PE and should
3280          * not allocate resources again.
3281          */
3282         pe = pnv_ioda_setup_bus_PE(bus, all);
3283         if (!pe)
3284                 return;
3285
3286         pnv_ioda_setup_pe_seg(pe);
3287         switch (phb->type) {
3288         case PNV_PHB_IODA1:
3289                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3290                 break;
3291         case PNV_PHB_IODA2:
3292                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3293                 break;
3294         default:
3295                 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3296                         __func__, phb->hose->global_number, phb->type);
3297         }
3298 }
3299
3300 #ifdef CONFIG_PCI_IOV
3301 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3302                                                       int resno)
3303 {
3304         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3305         struct pnv_phb *phb = hose->private_data;
3306         struct pci_dn *pdn = pci_get_pdn(pdev);
3307         resource_size_t align;
3308
3309         /*
3310          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3311          * SR-IOV. While from hardware perspective, the range mapped by M64
3312          * BAR should be size aligned.
3313          *
3314          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3315          * powernv-specific hardware restriction is gone. But if just use the
3316          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3317          * in one segment of M64 #15, which introduces the PE conflict between
3318          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3319          * m64_segsize.
3320          *
3321          * This function returns the total IOV BAR size if M64 BAR is in
3322          * Shared PE mode or just VF BAR size if not.
3323          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3324          * M64 segment size if IOV BAR size is less.
3325          */
3326         align = pci_iov_resource_size(pdev, resno);
3327         if (!pdn->vfs_expanded)
3328                 return align;
3329         if (pdn->m64_single_mode)
3330                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3331
3332         return pdn->vfs_expanded * align;
3333 }
3334 #endif /* CONFIG_PCI_IOV */
3335
3336 /* Prevent enabling devices for which we couldn't properly
3337  * assign a PE
3338  */
3339 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3340 {
3341         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3342         struct pnv_phb *phb = hose->private_data;
3343         struct pci_dn *pdn;
3344
3345         /* The function is probably called while the PEs have
3346          * not be created yet. For example, resource reassignment
3347          * during PCI probe period. We just skip the check if
3348          * PEs isn't ready.
3349          */
3350         if (!phb->initialized)
3351                 return true;
3352
3353         pdn = pci_get_pdn(dev);
3354         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3355                 return false;
3356
3357         return true;
3358 }
3359
3360 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3361                                        int num)
3362 {
3363         struct pnv_ioda_pe *pe = container_of(table_group,
3364                                               struct pnv_ioda_pe, table_group);
3365         struct pnv_phb *phb = pe->phb;
3366         unsigned int idx;
3367         long rc;
3368
3369         pe_info(pe, "Removing DMA window #%d\n", num);
3370         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3371                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3372                         continue;
3373
3374                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3375                                                 idx, 0, 0ul, 0ul, 0ul);
3376                 if (rc != OPAL_SUCCESS) {
3377                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3378                                 rc, idx);
3379                         return rc;
3380                 }
3381
3382                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3383         }
3384
3385         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3386         return OPAL_SUCCESS;
3387 }
3388
3389 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3390 {
3391         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3392         struct iommu_table *tbl = pe->table_group.tables[0];
3393         int64_t rc;
3394
3395         if (!weight)
3396                 return;
3397
3398         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3399         if (rc != OPAL_SUCCESS)
3400                 return;
3401
3402         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3403         if (pe->table_group.group) {
3404                 iommu_group_put(pe->table_group.group);
3405                 WARN_ON(pe->table_group.group);
3406         }
3407
3408         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3409         iommu_free_table(tbl, "pnv");
3410 }
3411
3412 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3413 {
3414         struct iommu_table *tbl = pe->table_group.tables[0];
3415         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3416 #ifdef CONFIG_IOMMU_API
3417         int64_t rc;
3418 #endif
3419
3420         if (!weight)
3421                 return;
3422
3423 #ifdef CONFIG_IOMMU_API
3424         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3425         if (rc)
3426                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3427 #endif
3428
3429         pnv_pci_ioda2_set_bypass(pe, false);
3430         if (pe->table_group.group) {
3431                 iommu_group_put(pe->table_group.group);
3432                 WARN_ON(pe->table_group.group);
3433         }
3434
3435         pnv_pci_ioda2_table_free_pages(tbl);
3436         iommu_free_table(tbl, "pnv");
3437 }
3438
3439 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3440                                  unsigned short win,
3441                                  unsigned int *map)
3442 {
3443         struct pnv_phb *phb = pe->phb;
3444         int idx;
3445         int64_t rc;
3446
3447         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3448                 if (map[idx] != pe->pe_number)
3449                         continue;
3450
3451                 if (win == OPAL_M64_WINDOW_TYPE)
3452                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3453                                         phb->ioda.reserved_pe_idx, win,
3454                                         idx / PNV_IODA1_M64_SEGS,
3455                                         idx % PNV_IODA1_M64_SEGS);
3456                 else
3457                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3458                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3459
3460                 if (rc != OPAL_SUCCESS)
3461                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3462                                 rc, win, idx);
3463
3464                 map[idx] = IODA_INVALID_PE;
3465         }
3466 }
3467
3468 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3469 {
3470         struct pnv_phb *phb = pe->phb;
3471
3472         if (phb->type == PNV_PHB_IODA1) {
3473                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3474                                      phb->ioda.io_segmap);
3475                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3476                                      phb->ioda.m32_segmap);
3477                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3478                                      phb->ioda.m64_segmap);
3479         } else if (phb->type == PNV_PHB_IODA2) {
3480                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3481                                      phb->ioda.m32_segmap);
3482         }
3483 }
3484
3485 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3486 {
3487         struct pnv_phb *phb = pe->phb;
3488         struct pnv_ioda_pe *slave, *tmp;
3489
3490         list_del(&pe->list);
3491         switch (phb->type) {
3492         case PNV_PHB_IODA1:
3493                 pnv_pci_ioda1_release_pe_dma(pe);
3494                 break;
3495         case PNV_PHB_IODA2:
3496                 pnv_pci_ioda2_release_pe_dma(pe);
3497                 break;
3498         default:
3499                 WARN_ON(1);
3500         }
3501
3502         pnv_ioda_release_pe_seg(pe);
3503         pnv_ioda_deconfigure_pe(pe->phb, pe);
3504
3505         /* Release slave PEs in the compound PE */
3506         if (pe->flags & PNV_IODA_PE_MASTER) {
3507                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3508                         list_del(&slave->list);
3509                         pnv_ioda_free_pe(slave);
3510                 }
3511         }
3512
3513         /*
3514          * The PE for root bus can be removed because of hotplug in EEH
3515          * recovery for fenced PHB error. We need to mark the PE dead so
3516          * that it can be populated again in PCI hot add path. The PE
3517          * shouldn't be destroyed as it's the global reserved resource.
3518          */
3519         if (phb->ioda.root_pe_populated &&
3520             phb->ioda.root_pe_idx == pe->pe_number)
3521                 phb->ioda.root_pe_populated = false;
3522         else
3523                 pnv_ioda_free_pe(pe);
3524 }
3525
3526 static void pnv_pci_release_device(struct pci_dev *pdev)
3527 {
3528         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3529         struct pnv_phb *phb = hose->private_data;
3530         struct pci_dn *pdn = pci_get_pdn(pdev);
3531         struct pnv_ioda_pe *pe;
3532
3533         if (pdev->is_virtfn)
3534                 return;
3535
3536         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3537                 return;
3538
3539         /*
3540          * PCI hotplug can happen as part of EEH error recovery. The @pdn
3541          * isn't removed and added afterwards in this scenario. We should
3542          * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3543          * device count is decreased on removing devices while failing to
3544          * be increased on adding devices. It leads to unbalanced PE's device
3545          * count and eventually make normal PCI hotplug path broken.
3546          */
3547         pe = &phb->ioda.pe_array[pdn->pe_number];
3548         pdn->pe_number = IODA_INVALID_PE;
3549
3550         WARN_ON(--pe->device_count < 0);
3551         if (pe->device_count == 0)
3552                 pnv_ioda_release_pe(pe);
3553 }
3554
3555 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3556 {
3557         struct pnv_phb *phb = hose->private_data;
3558
3559         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3560                        OPAL_ASSERT_RESET);
3561 }
3562
3563 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3564         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3565         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3566 #ifdef CONFIG_PCI_MSI
3567         .setup_msi_irqs         = pnv_setup_msi_irqs,
3568         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3569 #endif
3570         .enable_device_hook     = pnv_pci_enable_device_hook,
3571         .release_device         = pnv_pci_release_device,
3572         .window_alignment       = pnv_pci_window_alignment,
3573         .setup_bridge           = pnv_pci_setup_bridge,
3574         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3575         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3576         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3577         .shutdown               = pnv_pci_ioda_shutdown,
3578 };
3579
3580 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3581 {
3582         dev_err_once(&npdev->dev,
3583                         "%s operation unsupported for NVLink devices\n",
3584                         __func__);
3585         return -EPERM;
3586 }
3587
3588 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3589         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3590 #ifdef CONFIG_PCI_MSI
3591         .setup_msi_irqs         = pnv_setup_msi_irqs,
3592         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3593 #endif
3594         .enable_device_hook     = pnv_pci_enable_device_hook,
3595         .window_alignment       = pnv_pci_window_alignment,
3596         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3597         .dma_set_mask           = pnv_npu_dma_set_mask,
3598         .shutdown               = pnv_pci_ioda_shutdown,
3599 };
3600
3601 #ifdef CONFIG_CXL_BASE
3602 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3603         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3604         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3605 #ifdef CONFIG_PCI_MSI
3606         .setup_msi_irqs         = pnv_cxl_cx4_setup_msi_irqs,
3607         .teardown_msi_irqs      = pnv_cxl_cx4_teardown_msi_irqs,
3608 #endif
3609         .enable_device_hook     = pnv_cxl_enable_device_hook,
3610         .disable_device         = pnv_cxl_disable_device,
3611         .release_device         = pnv_pci_release_device,
3612         .window_alignment       = pnv_pci_window_alignment,
3613         .setup_bridge           = pnv_pci_setup_bridge,
3614         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3615         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3616         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3617         .shutdown               = pnv_pci_ioda_shutdown,
3618 };
3619 #endif
3620
3621 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3622                                          u64 hub_id, int ioda_type)
3623 {
3624         struct pci_controller *hose;
3625         struct pnv_phb *phb;
3626         unsigned long size, m64map_off, m32map_off, pemap_off;
3627         unsigned long iomap_off = 0, dma32map_off = 0;
3628         struct resource r;
3629         const __be64 *prop64;
3630         const __be32 *prop32;
3631         int len;
3632         unsigned int segno;
3633         u64 phb_id;
3634         void *aux;
3635         long rc;
3636
3637         if (!of_device_is_available(np))
3638                 return;
3639
3640         pr_info("Initializing %s PHB (%s)\n",
3641                 pnv_phb_names[ioda_type], of_node_full_name(np));
3642
3643         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3644         if (!prop64) {
3645                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3646                 return;
3647         }
3648         phb_id = be64_to_cpup(prop64);
3649         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3650
3651         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3652
3653         /* Allocate PCI controller */
3654         phb->hose = hose = pcibios_alloc_controller(np);
3655         if (!phb->hose) {
3656                 pr_err("  Can't allocate PCI controller for %s\n",
3657                        np->full_name);
3658                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3659                 return;
3660         }
3661
3662         spin_lock_init(&phb->lock);
3663         prop32 = of_get_property(np, "bus-range", &len);
3664         if (prop32 && len == 8) {
3665                 hose->first_busno = be32_to_cpu(prop32[0]);
3666                 hose->last_busno = be32_to_cpu(prop32[1]);
3667         } else {
3668                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3669                 hose->first_busno = 0;
3670                 hose->last_busno = 0xff;
3671         }
3672         hose->private_data = phb;
3673         phb->hub_id = hub_id;
3674         phb->opal_id = phb_id;
3675         phb->type = ioda_type;
3676         mutex_init(&phb->ioda.pe_alloc_mutex);
3677
3678         /* Detect specific models for error handling */
3679         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3680                 phb->model = PNV_PHB_MODEL_P7IOC;
3681         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3682                 phb->model = PNV_PHB_MODEL_PHB3;
3683         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3684                 phb->model = PNV_PHB_MODEL_NPU;
3685         else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3686                 phb->model = PNV_PHB_MODEL_NPU2;
3687         else
3688                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3689
3690         /* Parse 32-bit and IO ranges (if any) */
3691         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3692
3693         /* Get registers */
3694         if (!of_address_to_resource(np, 0, &r)) {
3695                 phb->regs_phys = r.start;
3696                 phb->regs = ioremap(r.start, resource_size(&r));
3697                 if (phb->regs == NULL)
3698                         pr_err("  Failed to map registers !\n");
3699         }
3700
3701         /* Initialize more IODA stuff */
3702         phb->ioda.total_pe_num = 1;
3703         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3704         if (prop32)
3705                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3706         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3707         if (prop32)
3708                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3709
3710         /* Invalidate RID to PE# mapping */
3711         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3712                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3713
3714         /* Parse 64-bit MMIO range */
3715         pnv_ioda_parse_m64_window(phb);
3716
3717         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3718         /* FW Has already off top 64k of M32 space (MSI space) */
3719         phb->ioda.m32_size += 0x10000;
3720
3721         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3722         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3723         phb->ioda.io_size = hose->pci_io_size;
3724         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3725         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3726
3727         /* Calculate how many 32-bit TCE segments we have */
3728         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3729                                 PNV_IODA1_DMA32_SEGSIZE;
3730
3731         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3732         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3733                         sizeof(unsigned long));
3734         m64map_off = size;
3735         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3736         m32map_off = size;
3737         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3738         if (phb->type == PNV_PHB_IODA1) {
3739                 iomap_off = size;
3740                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3741                 dma32map_off = size;
3742                 size += phb->ioda.dma32_count *
3743                         sizeof(phb->ioda.dma32_segmap[0]);
3744         }
3745         pemap_off = size;
3746         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3747         aux = memblock_virt_alloc(size, 0);
3748         phb->ioda.pe_alloc = aux;
3749         phb->ioda.m64_segmap = aux + m64map_off;
3750         phb->ioda.m32_segmap = aux + m32map_off;
3751         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3752                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3753                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3754         }
3755         if (phb->type == PNV_PHB_IODA1) {
3756                 phb->ioda.io_segmap = aux + iomap_off;
3757                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3758                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3759
3760                 phb->ioda.dma32_segmap = aux + dma32map_off;
3761                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3762                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3763         }
3764         phb->ioda.pe_array = aux + pemap_off;
3765
3766         /*
3767          * Choose PE number for root bus, which shouldn't have
3768          * M64 resources consumed by its child devices. To pick
3769          * the PE number adjacent to the reserved one if possible.
3770          */
3771         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3772         if (phb->ioda.reserved_pe_idx == 0) {
3773                 phb->ioda.root_pe_idx = 1;
3774                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3775         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3776                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3777                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3778         } else {
3779                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3780         }
3781
3782         INIT_LIST_HEAD(&phb->ioda.pe_list);
3783         mutex_init(&phb->ioda.pe_list_mutex);
3784
3785         /* Calculate how many 32-bit TCE segments we have */
3786         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3787                                 PNV_IODA1_DMA32_SEGSIZE;
3788
3789 #if 0 /* We should really do that ... */
3790         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3791                                          window_type,
3792                                          window_num,
3793                                          starting_real_address,
3794                                          starting_pci_address,
3795                                          segment_size);
3796 #endif
3797
3798         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3799                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3800                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3801         if (phb->ioda.m64_size)
3802                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3803                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3804         if (phb->ioda.io_size)
3805                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3806                         phb->ioda.io_size, phb->ioda.io_segsize);
3807
3808
3809         phb->hose->ops = &pnv_pci_ops;
3810         phb->get_pe_state = pnv_ioda_get_pe_state;
3811         phb->freeze_pe = pnv_ioda_freeze_pe;
3812         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3813
3814         /* Setup MSI support */
3815         pnv_pci_init_ioda_msis(phb);
3816
3817         /*
3818          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3819          * to let the PCI core do resource assignment. It's supposed
3820          * that the PCI core will do correct I/O and MMIO alignment
3821          * for the P2P bridge bars so that each PCI bus (excluding
3822          * the child P2P bridges) can form individual PE.
3823          */
3824         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3825
3826         if (phb->type == PNV_PHB_NPU) {
3827                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3828         } else {
3829                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3830                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3831         }
3832
3833 #ifdef CONFIG_PCI_IOV
3834         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3835         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3836 #endif
3837
3838         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3839
3840         /* Reset IODA tables to a clean state */
3841         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3842         if (rc)
3843                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3844
3845         /*
3846          * If we're running in kdump kernel, the previous kernel never
3847          * shutdown PCI devices correctly. We already got IODA table
3848          * cleaned out. So we have to issue PHB reset to stop all PCI
3849          * transactions from previous kernel.
3850          */
3851         if (is_kdump_kernel()) {
3852                 pr_info("  Issue PHB reset ...\n");
3853                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3854                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3855         }
3856
3857         /* Remove M64 resource if we can't configure it successfully */
3858         if (!phb->init_m64 || phb->init_m64(phb))
3859                 hose->mem_resources[1].flags = 0;
3860 }
3861
3862 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3863 {
3864         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3865 }
3866
3867 void __init pnv_pci_init_npu_phb(struct device_node *np)
3868 {
3869         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3870 }
3871
3872 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3873 {
3874         struct device_node *phbn;
3875         const __be64 *prop64;
3876         u64 hub_id;
3877
3878         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3879
3880         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3881         if (!prop64) {
3882                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3883                 return;
3884         }
3885         hub_id = be64_to_cpup(prop64);
3886         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3887
3888         /* Count child PHBs */
3889         for_each_child_of_node(np, phbn) {
3890                 /* Look for IODA1 PHBs */
3891                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3892                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3893         }
3894 }