arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/memblock.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/msi.h>
  24 #include <linux/iommu.h>
  25 #include <linux/rculist.h>
  26 #include <linux/sizes.h>
  27
  28 #include <asm/sections.h>
  29 #include <asm/io.h>
  30 #include <asm/prom.h>
  31 #include <asm/pci-bridge.h>
  32 #include <asm/machdep.h>
  33 #include <asm/msi_bitmap.h>
  34 #include <asm/ppc-pci.h>
  35 #include <asm/opal.h>
  36 #include <asm/iommu.h>
  37 #include <asm/tce.h>
  38 #include <asm/xics.h>
  39 #include <asm/debugfs.h>
  40 #include <asm/firmware.h>
  41 #include <asm/pnv-pci.h>
  42 #include <asm/mmzone.h>
  43
  44 #include <misc/cxl-base.h>
  45
  46 #include "powernv.h"
  47 #include "pci.h"
  48 #include "../../../../drivers/pci/pci.h"
  49
  50 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  51 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  53
  54 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
  55                                               "NPU_OCAPI" };
  56
  57 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  58                             const char *fmt, ...)
  59 {
  60         struct va_format vaf;
  61         va_list args;
  62         char pfix[32];
  63
  64         va_start(args, fmt);
  65
  66         vaf.fmt = fmt;
  67         vaf.va = &args;
  68
  69         if (pe->flags & PNV_IODA_PE_DEV)
  70                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  71         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  72                 sprintf(pfix, "%04x:%02x     ",
  73                         pci_domain_nr(pe->pbus), pe->pbus->number);
  74 #ifdef CONFIG_PCI_IOV
  75         else if (pe->flags & PNV_IODA_PE_VF)
  76                 sprintf(pfix, "%04x:%02x:%2x.%d",
  77                         pci_domain_nr(pe->parent_dev->bus),
  78                         (pe->rid & 0xff00) >> 8,
  79                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  80 #endif /* CONFIG_PCI_IOV*/
  81
  82         printk("%spci %s: [PE# %.2x] %pV",
  83                level, pfix, pe->pe_number, &vaf);
  84
  85         va_end(args);
  86 }
  87
  88 static bool pnv_iommu_bypass_disabled __read_mostly;
  89 static bool pci_reset_phbs __read_mostly;
  90
  91 static int __init iommu_setup(char *str)
  92 {
  93         if (!str)
  94                 return -EINVAL;
  95
  96         while (*str) {
  97                 if (!strncmp(str, "nobypass", 8)) {
  98                         pnv_iommu_bypass_disabled = true;
  99                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 100                         break;
 101                 }
 102                 str += strcspn(str, ",");
 103                 if (*str == ',')
 104                         str++;
 105         }
 106
 107         return 0;
 108 }
 109 early_param("iommu", iommu_setup);
 110
 111 static int __init pci_reset_phbs_setup(char *str)
 112 {
 113         pci_reset_phbs = true;
 114         return 0;
 115 }
 116
 117 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
 118
 119 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
 120 {
 121         /*
 122          * WARNING: We cannot rely on the resource flags. The Linux PCI
 123          * allocation code sometimes decides to put a 64-bit prefetchable
 124          * BAR in the 32-bit window, so we have to compare the addresses.
 125          *
 126          * For simplicity we only test resource start.
 127          */
 128         return (r->start >= phb->ioda.m64_base &&
 129                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
 130 }
 131
 132 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
 133 {
 134         unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 135
 136         return (resource_flags & flags) == flags;
 137 }
 138
 139 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 140 {
 141         s64 rc;
 142
 143         phb->ioda.pe_array[pe_no].phb = phb;
 144         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 145
 146         /*
 147          * Clear the PE frozen state as it might be put into frozen state
 148          * in the last PCI remove path. It's not harmful to do so when the
 149          * PE is already in unfrozen state.
 150          */
 151         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 152                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 153         if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
 154                 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
 155                         __func__, rc, phb->hose->global_number, pe_no);
 156
 157         return &phb->ioda.pe_array[pe_no];
 158 }
 159
 160 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 161 {
 162         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 163                 pr_warn("%s: Invalid PE %x on PHB#%x\n",
 164                         __func__, pe_no, phb->hose->global_number);
 165                 return;
 166         }
 167
 168         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 169                 pr_debug("%s: PE %x was reserved on PHB#%x\n",
 170                          __func__, pe_no, phb->hose->global_number);
 171
 172         pnv_ioda_init_pe(phb, pe_no);
 173 }
 174
 175 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 176 {
 177         long pe;
 178
 179         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 180                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 181                         return pnv_ioda_init_pe(phb, pe);
 182         }
 183
 184         return NULL;
 185 }
 186
 187 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 188 {
 189         struct pnv_phb *phb = pe->phb;
 190         unsigned int pe_num = pe->pe_number;
 191
 192         WARN_ON(pe->pdev);
 193         WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */
 194         kfree(pe->npucomp);
 195         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 196         clear_bit(pe_num, phb->ioda.pe_alloc);
 197 }
 198
 199 /* The default M64 BAR is shared by all PEs */
 200 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 201 {
 202         const char *desc;
 203         struct resource *r;
 204         s64 rc;
 205
 206         /* Configure the default M64 BAR */
 207         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 208                                          OPAL_M64_WINDOW_TYPE,
 209                                          phb->ioda.m64_bar_idx,
 210                                          phb->ioda.m64_base,
 211                                          0, /* unused */
 212                                          phb->ioda.m64_size);
 213         if (rc != OPAL_SUCCESS) {
 214                 desc = "configuring";
 215                 goto fail;
 216         }
 217
 218         /* Enable the default M64 BAR */
 219         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 220                                       OPAL_M64_WINDOW_TYPE,
 221                                       phb->ioda.m64_bar_idx,
 222                                       OPAL_ENABLE_M64_SPLIT);
 223         if (rc != OPAL_SUCCESS) {
 224                 desc = "enabling";
 225                 goto fail;
 226         }
 227
 228         /*
 229          * Exclude the segments for reserved and root bus PE, which
 230          * are first or last two PEs.
 231          */
 232         r = &phb->hose->mem_resources[1];
 233         if (phb->ioda.reserved_pe_idx == 0)
 234                 r->start += (2 * phb->ioda.m64_segsize);
 235         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 236                 r->end -= (2 * phb->ioda.m64_segsize);
 237         else
 238                 pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
 239                         phb->ioda.reserved_pe_idx);
 240
 241         return 0;
 242
 243 fail:
 244         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 245                 rc, desc, phb->ioda.m64_bar_idx);
 246         opal_pci_phb_mmio_enable(phb->opal_id,
 247                                  OPAL_M64_WINDOW_TYPE,
 248                                  phb->ioda.m64_bar_idx,
 249                                  OPAL_DISABLE_M64);
 250         return -EIO;
 251 }
 252
 253 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 254                                          unsigned long *pe_bitmap)
 255 {
 256         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 257         struct pnv_phb *phb = hose->private_data;
 258         struct resource *r;
 259         resource_size_t base, sgsz, start, end;
 260         int segno, i;
 261
 262         base = phb->ioda.m64_base;
 263         sgsz = phb->ioda.m64_segsize;
 264         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 265                 r = &pdev->resource[i];
 266                 if (!r->parent || !pnv_pci_is_m64(phb, r))
 267                         continue;
 268
 269                 start = _ALIGN_DOWN(r->start - base, sgsz);
 270                 end = _ALIGN_UP(r->end - base, sgsz);
 271                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 272                         if (pe_bitmap)
 273                                 set_bit(segno, pe_bitmap);
 274                         else
 275                                 pnv_ioda_reserve_pe(phb, segno);
 276                 }
 277         }
 278 }
 279
 280 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 281 {
 282         struct resource *r;
 283         int index;
 284
 285         /*
 286          * There are 16 M64 BARs, each of which has 8 segments. So
 287          * there are as many M64 segments as the maximum number of
 288          * PEs, which is 128.
 289          */
 290         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 291                 unsigned long base, segsz = phb->ioda.m64_segsize;
 292                 int64_t rc;
 293
 294                 base = phb->ioda.m64_base +
 295                        index * PNV_IODA1_M64_SEGS * segsz;
 296                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 297                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 298                                 PNV_IODA1_M64_SEGS * segsz);
 299                 if (rc != OPAL_SUCCESS) {
 300                         pr_warn("  Error %lld setting M64 PHB#%x-BAR#%d\n",
 301                                 rc, phb->hose->global_number, index);
 302                         goto fail;
 303                 }
 304
 305                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 306                                 OPAL_M64_WINDOW_TYPE, index,
 307                                 OPAL_ENABLE_M64_SPLIT);
 308                 if (rc != OPAL_SUCCESS) {
 309                         pr_warn("  Error %lld enabling M64 PHB#%x-BAR#%d\n",
 310                                 rc, phb->hose->global_number, index);
 311                         goto fail;
 312                 }
 313         }
 314
 315         /*
 316          * Exclude the segments for reserved and root bus PE, which
 317          * are first or last two PEs.
 318          */
 319         r = &phb->hose->mem_resources[1];
 320         if (phb->ioda.reserved_pe_idx == 0)
 321                 r->start += (2 * phb->ioda.m64_segsize);
 322         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 323                 r->end -= (2 * phb->ioda.m64_segsize);
 324         else
 325                 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
 326                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 327
 328         return 0;
 329
 330 fail:
 331         for ( ; index >= 0; index--)
 332                 opal_pci_phb_mmio_enable(phb->opal_id,
 333                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 334
 335         return -EIO;
 336 }
 337
 338 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 339                                     unsigned long *pe_bitmap,
 340                                     bool all)
 341 {
 342         struct pci_dev *pdev;
 343
 344         list_for_each_entry(pdev, &bus->devices, bus_list) {
 345                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 346
 347                 if (all && pdev->subordinate)
 348                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 349                                                 pe_bitmap, all);
 350         }
 351 }
 352
 353 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 354 {
 355         struct pci_controller *hose = pci_bus_to_host(bus);
 356         struct pnv_phb *phb = hose->private_data;
 357         struct pnv_ioda_pe *master_pe, *pe;
 358         unsigned long size, *pe_alloc;
 359         int i;
 360
 361         /* Root bus shouldn't use M64 */
 362         if (pci_is_root_bus(bus))
 363                 return NULL;
 364
 365         /* Allocate bitmap */
 366         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 367         pe_alloc = kzalloc(size, GFP_KERNEL);
 368         if (!pe_alloc) {
 369                 pr_warn("%s: Out of memory !\n",
 370                         __func__);
 371                 return NULL;
 372         }
 373
 374         /* Figure out reserved PE numbers by the PE */
 375         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 376
 377         /*
 378          * the current bus might not own M64 window and that's all
 379          * contributed by its child buses. For the case, we needn't
 380          * pick M64 dependent PE#.
 381          */
 382         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 383                 kfree(pe_alloc);
 384                 return NULL;
 385         }
 386
 387         /*
 388          * Figure out the master PE and put all slave PEs to master
 389          * PE's list to form compound PE.
 390          */
 391         master_pe = NULL;
 392         i = -1;
 393         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 394                 phb->ioda.total_pe_num) {
 395                 pe = &phb->ioda.pe_array[i];
 396
 397                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 398                 if (!master_pe) {
 399                         pe->flags |= PNV_IODA_PE_MASTER;
 400                         INIT_LIST_HEAD(&pe->slaves);
 401                         master_pe = pe;
 402                 } else {
 403                         pe->flags |= PNV_IODA_PE_SLAVE;
 404                         pe->master = master_pe;
 405                         list_add_tail(&pe->list, &master_pe->slaves);
 406                 }
 407
 408                 /*
 409                  * P7IOC supports M64DT, which helps mapping M64 segment
 410                  * to one particular PE#. However, PHB3 has fixed mapping
 411                  * between M64 segment and PE#. In order to have same logic
 412                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 413                  * segment and PE# on P7IOC.
 414                  */
 415                 if (phb->type == PNV_PHB_IODA1) {
 416                         int64_t rc;
 417
 418                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 419                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 420                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 421                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 422                         if (rc != OPAL_SUCCESS)
 423                                 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
 424                                         __func__, rc, phb->hose->global_number,
 425                                         pe->pe_number);
 426                 }
 427         }
 428
 429         kfree(pe_alloc);
 430         return master_pe;
 431 }
 432
 433 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 434 {
 435         struct pci_controller *hose = phb->hose;
 436         struct device_node *dn = hose->dn;
 437         struct resource *res;
 438         u32 m64_range[2], i;
 439         const __be32 *r;
 440         u64 pci_addr;
 441
 442         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 443                 pr_info("  Not support M64 window\n");
 444                 return;
 445         }
 446
 447         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 448                 pr_info("  Firmware too old to support M64 window\n");
 449                 return;
 450         }
 451
 452         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 453         if (!r) {
 454                 pr_info("  No <ibm,opal-m64-window> on %pOF\n",
 455                         dn);
 456                 return;
 457         }
 458
 459         /*
 460          * Find the available M64 BAR range and pickup the last one for
 461          * covering the whole 64-bits space. We support only one range.
 462          */
 463         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
 464                                        m64_range, 2)) {
 465                 /* In absence of the property, assume 0..15 */
 466                 m64_range[0] = 0;
 467                 m64_range[1] = 16;
 468         }
 469         /* We only support 64 bits in our allocator */
 470         if (m64_range[1] > 63) {
 471                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
 472                         __func__, m64_range[1], phb->hose->global_number);
 473                 m64_range[1] = 63;
 474         }
 475         /* Empty range, no m64 */
 476         if (m64_range[1] <= m64_range[0]) {
 477                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
 478                         __func__, phb->hose->global_number);
 479                 return;
 480         }
 481
 482         /* Configure M64 informations */
 483         res = &hose->mem_resources[1];
 484         res->name = dn->full_name;
 485         res->start = of_translate_address(dn, r + 2);
 486         res->end = res->start + of_read_number(r + 4, 2) - 1;
 487         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 488         pci_addr = of_read_number(r, 2);
 489         hose->mem_offset[1] = res->start - pci_addr;
 490
 491         phb->ioda.m64_size = resource_size(res);
 492         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 493         phb->ioda.m64_base = pci_addr;
 494
 495         /* This lines up nicely with the display from processing OF ranges */
 496         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
 497                 res->start, res->end, pci_addr, m64_range[0],
 498                 m64_range[0] + m64_range[1] - 1);
 499
 500         /* Mark all M64 used up by default */
 501         phb->ioda.m64_bar_alloc = (unsigned long)-1;
 502
 503         /* Use last M64 BAR to cover M64 window */
 504         m64_range[1]--;
 505         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
 506
 507         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
 508
 509         /* Mark remaining ones free */
 510         for (i = m64_range[0]; i < m64_range[1]; i++)
 511                 clear_bit(i, &phb->ioda.m64_bar_alloc);
 512
 513         /*
 514          * Setup init functions for M64 based on IODA version, IODA3 uses
 515          * the IODA2 code.
 516          */
 517         if (phb->type == PNV_PHB_IODA1)
 518                 phb->init_m64 = pnv_ioda1_init_m64;
 519         else
 520                 phb->init_m64 = pnv_ioda2_init_m64;
 521 }
 522
 523 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 524 {
 525         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 526         struct pnv_ioda_pe *slave;
 527         s64 rc;
 528
 529         /* Fetch master PE */
 530         if (pe->flags & PNV_IODA_PE_SLAVE) {
 531                 pe = pe->master;
 532                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 533                         return;
 534
 535                 pe_no = pe->pe_number;
 536         }
 537
 538         /* Freeze master PE */
 539         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 540                                      pe_no,
 541                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 542         if (rc != OPAL_SUCCESS) {
 543                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 544                         __func__, rc, phb->hose->global_number, pe_no);
 545                 return;
 546         }
 547
 548         /* Freeze slave PEs */
 549         if (!(pe->flags & PNV_IODA_PE_MASTER))
 550                 return;
 551
 552         list_for_each_entry(slave, &pe->slaves, list) {
 553                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 554                                              slave->pe_number,
 555                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 556                 if (rc != OPAL_SUCCESS)
 557                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 558                                 __func__, rc, phb->hose->global_number,
 559                                 slave->pe_number);
 560         }
 561 }
 562
 563 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 564 {
 565         struct pnv_ioda_pe *pe, *slave;
 566         s64 rc;
 567
 568         /* Find master PE */
 569         pe = &phb->ioda.pe_array[pe_no];
 570         if (pe->flags & PNV_IODA_PE_SLAVE) {
 571                 pe = pe->master;
 572                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 573                 pe_no = pe->pe_number;
 574         }
 575
 576         /* Clear frozen state for master PE */
 577         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 578         if (rc != OPAL_SUCCESS) {
 579                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 580                         __func__, rc, opt, phb->hose->global_number, pe_no);
 581                 return -EIO;
 582         }
 583
 584         if (!(pe->flags & PNV_IODA_PE_MASTER))
 585                 return 0;
 586
 587         /* Clear frozen state for slave PEs */
 588         list_for_each_entry(slave, &pe->slaves, list) {
 589                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 590                                              slave->pe_number,
 591                                              opt);
 592                 if (rc != OPAL_SUCCESS) {
 593                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 594                                 __func__, rc, opt, phb->hose->global_number,
 595                                 slave->pe_number);
 596                         return -EIO;
 597                 }
 598         }
 599
 600         return 0;
 601 }
 602
 603 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 604 {
 605         struct pnv_ioda_pe *slave, *pe;
 606         u8 fstate = 0, state;
 607         __be16 pcierr = 0;
 608         s64 rc;
 609
 610         /* Sanity check on PE number */
 611         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 612                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 613
 614         /*
 615          * Fetch the master PE and the PE instance might be
 616          * not initialized yet.
 617          */
 618         pe = &phb->ioda.pe_array[pe_no];
 619         if (pe->flags & PNV_IODA_PE_SLAVE) {
 620                 pe = pe->master;
 621                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 622                 pe_no = pe->pe_number;
 623         }
 624
 625         /* Check the master PE */
 626         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 627                                         &state, &pcierr, NULL);
 628         if (rc != OPAL_SUCCESS) {
 629                 pr_warn("%s: Failure %lld getting "
 630                         "PHB#%x-PE#%x state\n",
 631                         __func__, rc,
 632                         phb->hose->global_number, pe_no);
 633                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 634         }
 635
 636         /* Check the slave PE */
 637         if (!(pe->flags & PNV_IODA_PE_MASTER))
 638                 return state;
 639
 640         list_for_each_entry(slave, &pe->slaves, list) {
 641                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 642                                                 slave->pe_number,
 643                                                 &fstate,
 644                                                 &pcierr,
 645                                                 NULL);
 646                 if (rc != OPAL_SUCCESS) {
 647                         pr_warn("%s: Failure %lld getting "
 648                                 "PHB#%x-PE#%x state\n",
 649                                 __func__, rc,
 650                                 phb->hose->global_number, slave->pe_number);
 651                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 652                 }
 653
 654                 /*
 655                  * Override the result based on the ascending
 656                  * priority.
 657                  */
 658                 if (fstate > state)
 659                         state = fstate;
 660         }
 661
 662         return state;
 663 }
 664
 665 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 666 {
 667         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 668         struct pnv_phb *phb = hose->private_data;
 669         struct pci_dn *pdn = pci_get_pdn(dev);
 670
 671         if (!pdn)
 672                 return NULL;
 673         if (pdn->pe_number == IODA_INVALID_PE)
 674                 return NULL;
 675         return &phb->ioda.pe_array[pdn->pe_number];
 676 }
 677
 678 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 679                                   struct pnv_ioda_pe *parent,
 680                                   struct pnv_ioda_pe *child,
 681                                   bool is_add)
 682 {
 683         const char *desc = is_add ? "adding" : "removing";
 684         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 685                               OPAL_REMOVE_PE_FROM_DOMAIN;
 686         struct pnv_ioda_pe *slave;
 687         long rc;
 688
 689         /* Parent PE affects child PE */
 690         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 691                                 child->pe_number, op);
 692         if (rc != OPAL_SUCCESS) {
 693                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 694                         rc, desc);
 695                 return -ENXIO;
 696         }
 697
 698         if (!(child->flags & PNV_IODA_PE_MASTER))
 699                 return 0;
 700
 701         /* Compound case: parent PE affects slave PEs */
 702         list_for_each_entry(slave, &child->slaves, list) {
 703                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 704                                         slave->pe_number, op);
 705                 if (rc != OPAL_SUCCESS) {
 706                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 707                                 rc, desc);
 708                         return -ENXIO;
 709                 }
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 716                               struct pnv_ioda_pe *pe,
 717                               bool is_add)
 718 {
 719         struct pnv_ioda_pe *slave;
 720         struct pci_dev *pdev = NULL;
 721         int ret;
 722
 723         /*
 724          * Clear PE frozen state. If it's master PE, we need
 725          * clear slave PE frozen state as well.
 726          */
 727         if (is_add) {
 728                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 729                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 730                 if (pe->flags & PNV_IODA_PE_MASTER) {
 731                         list_for_each_entry(slave, &pe->slaves, list)
 732                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 733                                                           slave->pe_number,
 734                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 735                 }
 736         }
 737
 738         /*
 739          * Associate PE in PELT. We need add the PE into the
 740          * corresponding PELT-V as well. Otherwise, the error
 741          * originated from the PE might contribute to other
 742          * PEs.
 743          */
 744         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 745         if (ret)
 746                 return ret;
 747
 748         /* For compound PEs, any one affects all of them */
 749         if (pe->flags & PNV_IODA_PE_MASTER) {
 750                 list_for_each_entry(slave, &pe->slaves, list) {
 751                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 752                         if (ret)
 753                                 return ret;
 754                 }
 755         }
 756
 757         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 758                 pdev = pe->pbus->self;
 759         else if (pe->flags & PNV_IODA_PE_DEV)
 760                 pdev = pe->pdev->bus->self;
 761 #ifdef CONFIG_PCI_IOV
 762         else if (pe->flags & PNV_IODA_PE_VF)
 763                 pdev = pe->parent_dev;
 764 #endif /* CONFIG_PCI_IOV */
 765         while (pdev) {
 766                 struct pci_dn *pdn = pci_get_pdn(pdev);
 767                 struct pnv_ioda_pe *parent;
 768
 769                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 770                         parent = &phb->ioda.pe_array[pdn->pe_number];
 771                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 772                         if (ret)
 773                                 return ret;
 774                 }
 775
 776                 pdev = pdev->bus->self;
 777         }
 778
 779         return 0;
 780 }
 781
 782 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 783 {
 784         struct pci_dev *parent;
 785         uint8_t bcomp, dcomp, fcomp;
 786         int64_t rc;
 787         long rid_end, rid;
 788
 789         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 790         if (pe->pbus) {
 791                 int count;
 792
 793                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 794                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 795                 parent = pe->pbus->self;
 796                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 797                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 798                 else
 799                         count = 1;
 800
 801                 switch(count) {
 802                 case  1: bcomp = OpalPciBusAll;         break;
 803                 case  2: bcomp = OpalPciBus7Bits;       break;
 804                 case  4: bcomp = OpalPciBus6Bits;       break;
 805                 case  8: bcomp = OpalPciBus5Bits;       break;
 806                 case 16: bcomp = OpalPciBus4Bits;       break;
 807                 case 32: bcomp = OpalPciBus3Bits;       break;
 808                 default:
 809                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 810                                 count);
 811                         /* Do an exact match only */
 812                         bcomp = OpalPciBusAll;
 813                 }
 814                 rid_end = pe->rid + (count << 8);
 815         } else {
 816 #ifdef CONFIG_PCI_IOV
 817                 if (pe->flags & PNV_IODA_PE_VF)
 818                         parent = pe->parent_dev;
 819                 else
 820 #endif
 821                         parent = pe->pdev->bus->self;
 822                 bcomp = OpalPciBusAll;
 823                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 824                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 825                 rid_end = pe->rid + 1;
 826         }
 827
 828         /* Clear the reverse map */
 829         for (rid = pe->rid; rid < rid_end; rid++)
 830                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 831
 832         /* Release from all parents PELT-V */
 833         while (parent) {
 834                 struct pci_dn *pdn = pci_get_pdn(parent);
 835                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 836                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 837                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 838                         /* XXX What to do in case of error ? */
 839                 }
 840                 parent = parent->bus->self;
 841         }
 842
 843         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 844                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 845
 846         /* Disassociate PE in PELT */
 847         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 848                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 849         if (rc)
 850                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 851         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 852                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 853         if (rc)
 854                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 855
 856         pe->pbus = NULL;
 857         pe->pdev = NULL;
 858 #ifdef CONFIG_PCI_IOV
 859         pe->parent_dev = NULL;
 860 #endif
 861
 862         return 0;
 863 }
 864
 865 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 866 {
 867         struct pci_dev *parent;
 868         uint8_t bcomp, dcomp, fcomp;
 869         long rc, rid_end, rid;
 870
 871         /* Bus validation ? */
 872         if (pe->pbus) {
 873                 int count;
 874
 875                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 876                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 877                 parent = pe->pbus->self;
 878                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 879                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 880                 else
 881                         count = 1;
 882
 883                 switch(count) {
 884                 case  1: bcomp = OpalPciBusAll;         break;
 885                 case  2: bcomp = OpalPciBus7Bits;       break;
 886                 case  4: bcomp = OpalPciBus6Bits;       break;
 887                 case  8: bcomp = OpalPciBus5Bits;       break;
 888                 case 16: bcomp = OpalPciBus4Bits;       break;
 889                 case 32: bcomp = OpalPciBus3Bits;       break;
 890                 default:
 891                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 892                                 count);
 893                         /* Do an exact match only */
 894                         bcomp = OpalPciBusAll;
 895                 }
 896                 rid_end = pe->rid + (count << 8);
 897         } else {
 898 #ifdef CONFIG_PCI_IOV
 899                 if (pe->flags & PNV_IODA_PE_VF)
 900                         parent = pe->parent_dev;
 901                 else
 902 #endif /* CONFIG_PCI_IOV */
 903                         parent = pe->pdev->bus->self;
 904                 bcomp = OpalPciBusAll;
 905                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 906                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 907                 rid_end = pe->rid + 1;
 908         }
 909
 910         /*
 911          * Associate PE in PELT. We need add the PE into the
 912          * corresponding PELT-V as well. Otherwise, the error
 913          * originated from the PE might contribute to other
 914          * PEs.
 915          */
 916         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 917                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 918         if (rc) {
 919                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 920                 return -ENXIO;
 921         }
 922
 923         /*
 924          * Configure PELTV. NPUs don't have a PELTV table so skip
 925          * configuration on them.
 926          */
 927         if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
 928                 pnv_ioda_set_peltv(phb, pe, true);
 929
 930         /* Setup reverse map */
 931         for (rid = pe->rid; rid < rid_end; rid++)
 932                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 933
 934         /* Setup one MVTs on IODA1 */
 935         if (phb->type != PNV_PHB_IODA1) {
 936                 pe->mve_number = 0;
 937                 goto out;
 938         }
 939
 940         pe->mve_number = pe->pe_number;
 941         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 942         if (rc != OPAL_SUCCESS) {
 943                 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
 944                        rc, pe->mve_number);
 945                 pe->mve_number = -1;
 946         } else {
 947                 rc = opal_pci_set_mve_enable(phb->opal_id,
 948                                              pe->mve_number, OPAL_ENABLE_MVE);
 949                 if (rc) {
 950                         pe_err(pe, "OPAL error %ld enabling MVE %x\n",
 951                                rc, pe->mve_number);
 952                         pe->mve_number = -1;
 953                 }
 954         }
 955
 956 out:
 957         return 0;
 958 }
 959
 960 #ifdef CONFIG_PCI_IOV
 961 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 962 {
 963         struct pci_dn *pdn = pci_get_pdn(dev);
 964         int i;
 965         struct resource *res, res2;
 966         resource_size_t size;
 967         u16 num_vfs;
 968
 969         if (!dev->is_physfn)
 970                 return -EINVAL;
 971
 972         /*
 973          * "offset" is in VFs.  The M64 windows are sized so that when they
 974          * are segmented, each segment is the same size as the IOV BAR.
 975          * Each segment is in a separate PE, and the high order bits of the
 976          * address are the PE number.  Therefore, each VF's BAR is in a
 977          * separate PE, and changing the IOV BAR start address changes the
 978          * range of PEs the VFs are in.
 979          */
 980         num_vfs = pdn->num_vfs;
 981         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 982                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 983                 if (!res->flags || !res->parent)
 984                         continue;
 985
 986                 /*
 987                  * The actual IOV BAR range is determined by the start address
 988                  * and the actual size for num_vfs VFs BAR.  This check is to
 989                  * make sure that after shifting, the range will not overlap
 990                  * with another device.
 991                  */
 992                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 993                 res2.flags = res->flags;
 994                 res2.start = res->start + (size * offset);
 995                 res2.end = res2.start + (size * num_vfs) - 1;
 996
 997                 if (res2.end > res->end) {
 998                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 999                                 i, &res2, res, num_vfs, offset);
1000                         return -EBUSY;
1001                 }
1002         }
1003
1004         /*
1005          * Since M64 BAR shares segments among all possible 256 PEs,
1006          * we have to shift the beginning of PF IOV BAR to make it start from
1007          * the segment which belongs to the PE number assigned to the first VF.
1008          * This creates a "hole" in the /proc/iomem which could be used for
1009          * allocating other resources so we reserve this area below and
1010          * release when IOV is released.
1011          */
1012         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1013                 res = &dev->resource[i + PCI_IOV_RESOURCES];
1014                 if (!res->flags || !res->parent)
1015                         continue;
1016
1017                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1018                 res2 = *res;
1019                 res->start += size * offset;
1020
1021                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1022                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1023                          num_vfs, offset);
1024
1025                 if (offset < 0) {
1026                         devm_release_resource(&dev->dev, &pdn->holes[i]);
1027                         memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1028                 }
1029
1030                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1031
1032                 if (offset > 0) {
1033                         pdn->holes[i].start = res2.start;
1034                         pdn->holes[i].end = res2.start + size * offset - 1;
1035                         pdn->holes[i].flags = IORESOURCE_BUS;
1036                         pdn->holes[i].name = "pnv_iov_reserved";
1037                         devm_request_resource(&dev->dev, res->parent,
1038                                         &pdn->holes[i]);
1039                 }
1040         }
1041         return 0;
1042 }
1043 #endif /* CONFIG_PCI_IOV */
1044
1045 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1046 {
1047         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1048         struct pnv_phb *phb = hose->private_data;
1049         struct pci_dn *pdn = pci_get_pdn(dev);
1050         struct pnv_ioda_pe *pe;
1051
1052         if (!pdn) {
1053                 pr_err("%s: Device tree node not associated properly\n",
1054                            pci_name(dev));
1055                 return NULL;
1056         }
1057         if (pdn->pe_number != IODA_INVALID_PE)
1058                 return NULL;
1059
1060         pe = pnv_ioda_alloc_pe(phb);
1061         if (!pe) {
1062                 pr_warn("%s: Not enough PE# available, disabling device\n",
1063                         pci_name(dev));
1064                 return NULL;
1065         }
1066
1067         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1068          * pointer in the PE data structure, both should be destroyed at the
1069          * same time. However, this needs to be looked at more closely again
1070          * once we actually start removing things (Hotplug, SR-IOV, ...)
1071          *
1072          * At some point we want to remove the PDN completely anyways
1073          */
1074         pci_dev_get(dev);
1075         pdn->pe_number = pe->pe_number;
1076         pe->flags = PNV_IODA_PE_DEV;
1077         pe->pdev = dev;
1078         pe->pbus = NULL;
1079         pe->mve_number = -1;
1080         pe->rid = dev->bus->number << 8 | pdn->devfn;
1081
1082         pe_info(pe, "Associated device to PE\n");
1083
1084         if (pnv_ioda_configure_pe(phb, pe)) {
1085                 /* XXX What do we do here ? */
1086                 pnv_ioda_free_pe(pe);
1087                 pdn->pe_number = IODA_INVALID_PE;
1088                 pe->pdev = NULL;
1089                 pci_dev_put(dev);
1090                 return NULL;
1091         }
1092
1093         /* Put PE to the list */
1094         list_add_tail(&pe->list, &phb->ioda.pe_list);
1095
1096         return pe;
1097 }
1098
1099 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1100 {
1101         struct pci_dev *dev;
1102
1103         list_for_each_entry(dev, &bus->devices, bus_list) {
1104                 struct pci_dn *pdn = pci_get_pdn(dev);
1105
1106                 if (pdn == NULL) {
1107                         pr_warn("%s: No device node associated with device !\n",
1108                                 pci_name(dev));
1109                         continue;
1110                 }
1111
1112                 /*
1113                  * In partial hotplug case, the PCI device might be still
1114                  * associated with the PE and needn't attach it to the PE
1115                  * again.
1116                  */
1117                 if (pdn->pe_number != IODA_INVALID_PE)
1118                         continue;
1119
1120                 pe->device_count++;
1121                 pdn->pe_number = pe->pe_number;
1122                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1123                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1124         }
1125 }
1126
1127 /*
1128  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1129  * single PCI bus. Another one that contains the primary PCI bus and its
1130  * subordinate PCI devices and buses. The second type of PE is normally
1131  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1132  */
1133 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1134 {
1135         struct pci_controller *hose = pci_bus_to_host(bus);
1136         struct pnv_phb *phb = hose->private_data;
1137         struct pnv_ioda_pe *pe = NULL;
1138         unsigned int pe_num;
1139
1140         /*
1141          * In partial hotplug case, the PE instance might be still alive.
1142          * We should reuse it instead of allocating a new one.
1143          */
1144         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1145         if (pe_num != IODA_INVALID_PE) {
1146                 pe = &phb->ioda.pe_array[pe_num];
1147                 pnv_ioda_setup_same_PE(bus, pe);
1148                 return NULL;
1149         }
1150
1151         /* PE number for root bus should have been reserved */
1152         if (pci_is_root_bus(bus) &&
1153             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1154                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1155
1156         /* Check if PE is determined by M64 */
1157         if (!pe)
1158                 pe = pnv_ioda_pick_m64_pe(bus, all);
1159
1160         /* The PE number isn't pinned by M64 */
1161         if (!pe)
1162                 pe = pnv_ioda_alloc_pe(phb);
1163
1164         if (!pe) {
1165                 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1166                         __func__, pci_domain_nr(bus), bus->number);
1167                 return NULL;
1168         }
1169
1170         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1171         pe->pbus = bus;
1172         pe->pdev = NULL;
1173         pe->mve_number = -1;
1174         pe->rid = bus->busn_res.start << 8;
1175
1176         if (all)
1177                 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1178                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1179         else
1180                 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1181                         bus->busn_res.start, pe->pe_number);
1182
1183         if (pnv_ioda_configure_pe(phb, pe)) {
1184                 /* XXX What do we do here ? */
1185                 pnv_ioda_free_pe(pe);
1186                 pe->pbus = NULL;
1187                 return NULL;
1188         }
1189
1190         /* Associate it with all child devices */
1191         pnv_ioda_setup_same_PE(bus, pe);
1192
1193         /* Put PE to the list */
1194         list_add_tail(&pe->list, &phb->ioda.pe_list);
1195
1196         return pe;
1197 }
1198
1199 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1200 {
1201         int pe_num, found_pe = false, rc;
1202         long rid;
1203         struct pnv_ioda_pe *pe;
1204         struct pci_dev *gpu_pdev;
1205         struct pci_dn *npu_pdn;
1206         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1207         struct pnv_phb *phb = hose->private_data;
1208
1209         /*
1210          * Due to a hardware errata PE#0 on the NPU is reserved for
1211          * error handling. This means we only have three PEs remaining
1212          * which need to be assigned to four links, implying some
1213          * links must share PEs.
1214          *
1215          * To achieve this we assign PEs such that NPUs linking the
1216          * same GPU get assigned the same PE.
1217          */
1218         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1219         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1220                 pe = &phb->ioda.pe_array[pe_num];
1221                 if (!pe->pdev)
1222                         continue;
1223
1224                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1225                         /*
1226                          * This device has the same peer GPU so should
1227                          * be assigned the same PE as the existing
1228                          * peer NPU.
1229                          */
1230                         dev_info(&npu_pdev->dev,
1231                                 "Associating to existing PE %x\n", pe_num);
1232                         pci_dev_get(npu_pdev);
1233                         npu_pdn = pci_get_pdn(npu_pdev);
1234                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1235                         npu_pdn->pe_number = pe_num;
1236                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1237
1238                         /* Map the PE to this link */
1239                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1240                                         OpalPciBusAll,
1241                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1242                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1243                                         OPAL_MAP_PE);
1244                         WARN_ON(rc != OPAL_SUCCESS);
1245                         found_pe = true;
1246                         break;
1247                 }
1248         }
1249
1250         if (!found_pe)
1251                 /*
1252                  * Could not find an existing PE so allocate a new
1253                  * one.
1254                  */
1255                 return pnv_ioda_setup_dev_PE(npu_pdev);
1256         else
1257                 return pe;
1258 }
1259
1260 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1261 {
1262         struct pci_dev *pdev;
1263
1264         list_for_each_entry(pdev, &bus->devices, bus_list)
1265                 pnv_ioda_setup_npu_PE(pdev);
1266 }
1267
1268 static void pnv_pci_ioda_setup_PEs(void)
1269 {
1270         struct pci_controller *hose;
1271         struct pnv_phb *phb;
1272         struct pci_bus *bus;
1273         struct pci_dev *pdev;
1274         struct pnv_ioda_pe *pe;
1275
1276         list_for_each_entry(hose, &hose_list, list_node) {
1277                 phb = hose->private_data;
1278                 if (phb->type == PNV_PHB_NPU_NVLINK) {
1279                         /* PE#0 is needed for error reporting */
1280                         pnv_ioda_reserve_pe(phb, 0);
1281                         pnv_ioda_setup_npu_PEs(hose->bus);
1282                         if (phb->model == PNV_PHB_MODEL_NPU2)
1283                                 WARN_ON_ONCE(pnv_npu2_init(hose));
1284                 }
1285                 if (phb->type == PNV_PHB_NPU_OCAPI) {
1286                         bus = hose->bus;
1287                         list_for_each_entry(pdev, &bus->devices, bus_list)
1288                                 pnv_ioda_setup_dev_PE(pdev);
1289                 }
1290         }
1291         list_for_each_entry(hose, &hose_list, list_node) {
1292                 phb = hose->private_data;
1293                 if (phb->type != PNV_PHB_IODA2)
1294                         continue;
1295
1296                 list_for_each_entry(pe, &phb->ioda.pe_list, list)
1297                         pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1298         }
1299 }
1300
1301 #ifdef CONFIG_PCI_IOV
1302 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1303 {
1304         struct pci_bus        *bus;
1305         struct pci_controller *hose;
1306         struct pnv_phb        *phb;
1307         struct pci_dn         *pdn;
1308         int                    i, j;
1309         int                    m64_bars;
1310
1311         bus = pdev->bus;
1312         hose = pci_bus_to_host(bus);
1313         phb = hose->private_data;
1314         pdn = pci_get_pdn(pdev);
1315
1316         if (pdn->m64_single_mode)
1317                 m64_bars = num_vfs;
1318         else
1319                 m64_bars = 1;
1320
1321         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1322                 for (j = 0; j < m64_bars; j++) {
1323                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1324                                 continue;
1325                         opal_pci_phb_mmio_enable(phb->opal_id,
1326                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1327                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1328                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1329                 }
1330
1331         kfree(pdn->m64_map);
1332         return 0;
1333 }
1334
1335 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1336 {
1337         struct pci_bus        *bus;
1338         struct pci_controller *hose;
1339         struct pnv_phb        *phb;
1340         struct pci_dn         *pdn;
1341         unsigned int           win;
1342         struct resource       *res;
1343         int                    i, j;
1344         int64_t                rc;
1345         int                    total_vfs;
1346         resource_size_t        size, start;
1347         int                    pe_num;
1348         int                    m64_bars;
1349
1350         bus = pdev->bus;
1351         hose = pci_bus_to_host(bus);
1352         phb = hose->private_data;
1353         pdn = pci_get_pdn(pdev);
1354         total_vfs = pci_sriov_get_totalvfs(pdev);
1355
1356         if (pdn->m64_single_mode)
1357                 m64_bars = num_vfs;
1358         else
1359                 m64_bars = 1;
1360
1361         pdn->m64_map = kmalloc_array(m64_bars,
1362                                      sizeof(*pdn->m64_map),
1363                                      GFP_KERNEL);
1364         if (!pdn->m64_map)
1365                 return -ENOMEM;
1366         /* Initialize the m64_map to IODA_INVALID_M64 */
1367         for (i = 0; i < m64_bars ; i++)
1368                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1369                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1370
1371
1372         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1373                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1374                 if (!res->flags || !res->parent)
1375                         continue;
1376
1377                 for (j = 0; j < m64_bars; j++) {
1378                         do {
1379                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1380                                                 phb->ioda.m64_bar_idx + 1, 0);
1381
1382                                 if (win >= phb->ioda.m64_bar_idx + 1)
1383                                         goto m64_failed;
1384                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1385
1386                         pdn->m64_map[j][i] = win;
1387
1388                         if (pdn->m64_single_mode) {
1389                                 size = pci_iov_resource_size(pdev,
1390                                                         PCI_IOV_RESOURCES + i);
1391                                 start = res->start + size * j;
1392                         } else {
1393                                 size = resource_size(res);
1394                                 start = res->start;
1395                         }
1396
1397                         /* Map the M64 here */
1398                         if (pdn->m64_single_mode) {
1399                                 pe_num = pdn->pe_num_map[j];
1400                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1401                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1402                                                 pdn->m64_map[j][i], 0);
1403                         }
1404
1405                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1406                                                  OPAL_M64_WINDOW_TYPE,
1407                                                  pdn->m64_map[j][i],
1408                                                  start,
1409                                                  0, /* unused */
1410                                                  size);
1411
1412
1413                         if (rc != OPAL_SUCCESS) {
1414                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1415                                         win, rc);
1416                                 goto m64_failed;
1417                         }
1418
1419                         if (pdn->m64_single_mode)
1420                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1421                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1422                         else
1423                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1424                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1425
1426                         if (rc != OPAL_SUCCESS) {
1427                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1428                                         win, rc);
1429                                 goto m64_failed;
1430                         }
1431                 }
1432         }
1433         return 0;
1434
1435 m64_failed:
1436         pnv_pci_vf_release_m64(pdev, num_vfs);
1437         return -EBUSY;
1438 }
1439
1440 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1441                 int num);
1442
1443 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1444 {
1445         struct iommu_table    *tbl;
1446         int64_t               rc;
1447
1448         tbl = pe->table_group.tables[0];
1449         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1450         if (rc)
1451                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1452
1453         pnv_pci_ioda2_set_bypass(pe, false);
1454         if (pe->table_group.group) {
1455                 iommu_group_put(pe->table_group.group);
1456                 BUG_ON(pe->table_group.group);
1457         }
1458         iommu_tce_table_put(tbl);
1459 }
1460
1461 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1462 {
1463         struct pci_bus        *bus;
1464         struct pci_controller *hose;
1465         struct pnv_phb        *phb;
1466         struct pnv_ioda_pe    *pe, *pe_n;
1467         struct pci_dn         *pdn;
1468
1469         bus = pdev->bus;
1470         hose = pci_bus_to_host(bus);
1471         phb = hose->private_data;
1472         pdn = pci_get_pdn(pdev);
1473
1474         if (!pdev->is_physfn)
1475                 return;
1476
1477         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1478                 if (pe->parent_dev != pdev)
1479                         continue;
1480
1481                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1482
1483                 /* Remove from list */
1484                 mutex_lock(&phb->ioda.pe_list_mutex);
1485                 list_del(&pe->list);
1486                 mutex_unlock(&phb->ioda.pe_list_mutex);
1487
1488                 pnv_ioda_deconfigure_pe(phb, pe);
1489
1490                 pnv_ioda_free_pe(pe);
1491         }
1492 }
1493
1494 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1495 {
1496         struct pci_bus        *bus;
1497         struct pci_controller *hose;
1498         struct pnv_phb        *phb;
1499         struct pnv_ioda_pe    *pe;
1500         struct pci_dn         *pdn;
1501         u16                    num_vfs, i;
1502
1503         bus = pdev->bus;
1504         hose = pci_bus_to_host(bus);
1505         phb = hose->private_data;
1506         pdn = pci_get_pdn(pdev);
1507         num_vfs = pdn->num_vfs;
1508
1509         /* Release VF PEs */
1510         pnv_ioda_release_vf_PE(pdev);
1511
1512         if (phb->type == PNV_PHB_IODA2) {
1513                 if (!pdn->m64_single_mode)
1514                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1515
1516                 /* Release M64 windows */
1517                 pnv_pci_vf_release_m64(pdev, num_vfs);
1518
1519                 /* Release PE numbers */
1520                 if (pdn->m64_single_mode) {
1521                         for (i = 0; i < num_vfs; i++) {
1522                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1523                                         continue;
1524
1525                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1526                                 pnv_ioda_free_pe(pe);
1527                         }
1528                 } else
1529                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1530                 /* Releasing pe_num_map */
1531                 kfree(pdn->pe_num_map);
1532         }
1533 }
1534
1535 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1536                                        struct pnv_ioda_pe *pe);
1537 #ifdef CONFIG_IOMMU_API
1538 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
1539                 struct iommu_table_group *table_group, struct pci_bus *bus);
1540
1541 #endif
1542 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1543 {
1544         struct pci_bus        *bus;
1545         struct pci_controller *hose;
1546         struct pnv_phb        *phb;
1547         struct pnv_ioda_pe    *pe;
1548         int                    pe_num;
1549         u16                    vf_index;
1550         struct pci_dn         *pdn;
1551
1552         bus = pdev->bus;
1553         hose = pci_bus_to_host(bus);
1554         phb = hose->private_data;
1555         pdn = pci_get_pdn(pdev);
1556
1557         if (!pdev->is_physfn)
1558                 return;
1559
1560         /* Reserve PE for each VF */
1561         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1562                 if (pdn->m64_single_mode)
1563                         pe_num = pdn->pe_num_map[vf_index];
1564                 else
1565                         pe_num = *pdn->pe_num_map + vf_index;
1566
1567                 pe = &phb->ioda.pe_array[pe_num];
1568                 pe->pe_number = pe_num;
1569                 pe->phb = phb;
1570                 pe->flags = PNV_IODA_PE_VF;
1571                 pe->pbus = NULL;
1572                 pe->parent_dev = pdev;
1573                 pe->mve_number = -1;
1574                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1575                            pci_iov_virtfn_devfn(pdev, vf_index);
1576
1577                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1578                         hose->global_number, pdev->bus->number,
1579                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1580                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1581
1582                 if (pnv_ioda_configure_pe(phb, pe)) {
1583                         /* XXX What do we do here ? */
1584                         pnv_ioda_free_pe(pe);
1585                         pe->pdev = NULL;
1586                         continue;
1587                 }
1588
1589                 /* Put PE to the list */
1590                 mutex_lock(&phb->ioda.pe_list_mutex);
1591                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1592                 mutex_unlock(&phb->ioda.pe_list_mutex);
1593
1594                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1595 #ifdef CONFIG_IOMMU_API
1596                 pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
1597 #endif
1598         }
1599 }
1600
1601 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1602 {
1603         struct pci_bus        *bus;
1604         struct pci_controller *hose;
1605         struct pnv_phb        *phb;
1606         struct pnv_ioda_pe    *pe;
1607         struct pci_dn         *pdn;
1608         int                    ret;
1609         u16                    i;
1610
1611         bus = pdev->bus;
1612         hose = pci_bus_to_host(bus);
1613         phb = hose->private_data;
1614         pdn = pci_get_pdn(pdev);
1615
1616         if (phb->type == PNV_PHB_IODA2) {
1617                 if (!pdn->vfs_expanded) {
1618                         dev_info(&pdev->dev, "don't support this SRIOV device"
1619                                 " with non 64bit-prefetchable IOV BAR\n");
1620                         return -ENOSPC;
1621                 }
1622
1623                 /*
1624                  * When M64 BARs functions in Single PE mode, the number of VFs
1625                  * could be enabled must be less than the number of M64 BARs.
1626                  */
1627                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1628                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1629                         return -EBUSY;
1630                 }
1631
1632                 /* Allocating pe_num_map */
1633                 if (pdn->m64_single_mode)
1634                         pdn->pe_num_map = kmalloc_array(num_vfs,
1635                                                         sizeof(*pdn->pe_num_map),
1636                                                         GFP_KERNEL);
1637                 else
1638                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1639
1640                 if (!pdn->pe_num_map)
1641                         return -ENOMEM;
1642
1643                 if (pdn->m64_single_mode)
1644                         for (i = 0; i < num_vfs; i++)
1645                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1646
1647                 /* Calculate available PE for required VFs */
1648                 if (pdn->m64_single_mode) {
1649                         for (i = 0; i < num_vfs; i++) {
1650                                 pe = pnv_ioda_alloc_pe(phb);
1651                                 if (!pe) {
1652                                         ret = -EBUSY;
1653                                         goto m64_failed;
1654                                 }
1655
1656                                 pdn->pe_num_map[i] = pe->pe_number;
1657                         }
1658                 } else {
1659                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1660                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1661                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1662                                 0, num_vfs, 0);
1663                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1664                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1665                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1666                                 kfree(pdn->pe_num_map);
1667                                 return -EBUSY;
1668                         }
1669                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1670                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1671                 }
1672                 pdn->num_vfs = num_vfs;
1673
1674                 /* Assign M64 window accordingly */
1675                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1676                 if (ret) {
1677                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1678                         goto m64_failed;
1679                 }
1680
1681                 /*
1682                  * When using one M64 BAR to map one IOV BAR, we need to shift
1683                  * the IOV BAR according to the PE# allocated to the VFs.
1684                  * Otherwise, the PE# for the VF will conflict with others.
1685                  */
1686                 if (!pdn->m64_single_mode) {
1687                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1688                         if (ret)
1689                                 goto m64_failed;
1690                 }
1691         }
1692
1693         /* Setup VF PEs */
1694         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1695
1696         return 0;
1697
1698 m64_failed:
1699         if (pdn->m64_single_mode) {
1700                 for (i = 0; i < num_vfs; i++) {
1701                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1702                                 continue;
1703
1704                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1705                         pnv_ioda_free_pe(pe);
1706                 }
1707         } else
1708                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1709
1710         /* Releasing pe_num_map */
1711         kfree(pdn->pe_num_map);
1712
1713         return ret;
1714 }
1715
1716 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1717 {
1718         pnv_pci_sriov_disable(pdev);
1719
1720         /* Release PCI data */
1721         remove_dev_pci_data(pdev);
1722         return 0;
1723 }
1724
1725 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1726 {
1727         /* Allocate PCI data */
1728         add_dev_pci_data(pdev);
1729
1730         return pnv_pci_sriov_enable(pdev, num_vfs);
1731 }
1732 #endif /* CONFIG_PCI_IOV */
1733
1734 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1735 {
1736         struct pci_dn *pdn = pci_get_pdn(pdev);
1737         struct pnv_ioda_pe *pe;
1738
1739         /*
1740          * The function can be called while the PE#
1741          * hasn't been assigned. Do nothing for the
1742          * case.
1743          */
1744         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1745                 return;
1746
1747         pe = &phb->ioda.pe_array[pdn->pe_number];
1748         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1749         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1750         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1751         /*
1752          * Note: iommu_add_device() will fail here as
1753          * for physical PE: the device is already added by now;
1754          * for virtual PE: sysfs entries are not ready yet and
1755          * tce_iommu_bus_notifier will add the device to a group later.
1756          */
1757 }
1758
1759 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe)
1760 {
1761         unsigned short vendor = 0;
1762         struct pci_dev *pdev;
1763
1764         if (pe->device_count == 1)
1765                 return true;
1766
1767         /* pe->pdev should be set if it's a single device, pe->pbus if not */
1768         if (!pe->pbus)
1769                 return true;
1770
1771         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
1772                 if (!vendor) {
1773                         vendor = pdev->vendor;
1774                         continue;
1775                 }
1776
1777                 if (pdev->vendor != vendor)
1778                         return false;
1779         }
1780
1781         return true;
1782 }
1783
1784 /*
1785  * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1786  *
1787  * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1788  * Devices can only access more than that if bit 59 of the PCI address is set
1789  * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1790  * Many PCI devices are not capable of addressing that many bits, and as a
1791  * result are limited to the 4GB of virtual memory made available to 32-bit
1792  * devices in TVE#0.
1793  *
1794  * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1795  * devices by configuring the virtual memory past the first 4GB inaccessible
1796  * by 64-bit DMAs.  This should only be used by devices that want more than
1797  * 4GB, and only on PEs that have no 32-bit devices.
1798  *
1799  * Currently this will only work on PHB3 (POWER8).
1800  */
1801 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1802 {
1803         u64 window_size, table_size, tce_count, addr;
1804         struct page *table_pages;
1805         u64 tce_order = 28; /* 256MB TCEs */
1806         __be64 *tces;
1807         s64 rc;
1808
1809         /*
1810          * Window size needs to be a power of two, but needs to account for
1811          * shifting memory by the 4GB offset required to skip 32bit space.
1812          */
1813         window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1814         tce_count = window_size >> tce_order;
1815         table_size = tce_count << 3;
1816
1817         if (table_size < PAGE_SIZE)
1818                 table_size = PAGE_SIZE;
1819
1820         table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1821                                        get_order(table_size));
1822         if (!table_pages)
1823                 goto err;
1824
1825         tces = page_address(table_pages);
1826         if (!tces)
1827                 goto err;
1828
1829         memset(tces, 0, table_size);
1830
1831         for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1832                 tces[(addr + (1ULL << 32)) >> tce_order] =
1833                         cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1834         }
1835
1836         rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1837                                         pe->pe_number,
1838                                         /* reconfigure window 0 */
1839                                         (pe->pe_number << 1) + 0,
1840                                         1,
1841                                         __pa(tces),
1842                                         table_size,
1843                                         1 << tce_order);
1844         if (rc == OPAL_SUCCESS) {
1845                 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1846                 return 0;
1847         }
1848 err:
1849         pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1850         return -EIO;
1851 }
1852
1853 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1854 {
1855         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1856         struct pnv_phb *phb = hose->private_data;
1857         struct pci_dn *pdn = pci_get_pdn(pdev);
1858         struct pnv_ioda_pe *pe;
1859         uint64_t top;
1860         bool bypass = false;
1861         s64 rc;
1862
1863         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1864                 return -ENODEV;
1865
1866         pe = &phb->ioda.pe_array[pdn->pe_number];
1867         if (pe->tce_bypass_enabled) {
1868                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1869                 bypass = (dma_mask >= top);
1870         }
1871
1872         if (bypass) {
1873                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1874                 set_dma_ops(&pdev->dev, &dma_nommu_ops);
1875         } else {
1876                 /*
1877                  * If the device can't set the TCE bypass bit but still wants
1878                  * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1879                  * bypass the 32-bit region and be usable for 64-bit DMAs.
1880                  * The device needs to be able to address all of this space.
1881                  */
1882                 if (dma_mask >> 32 &&
1883                     dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1884                     pnv_pci_ioda_pe_single_vendor(pe) &&
1885                     phb->model == PNV_PHB_MODEL_PHB3) {
1886                         /* Configure the bypass mode */
1887                         rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1888                         if (rc)
1889                                 return rc;
1890                         /* 4GB offset bypasses 32-bit space */
1891                         set_dma_offset(&pdev->dev, (1ULL << 32));
1892                         set_dma_ops(&pdev->dev, &dma_nommu_ops);
1893                 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
1894                         /*
1895                          * Fail the request if a DMA mask between 32 and 64 bits
1896                          * was requested but couldn't be fulfilled. Ideally we
1897                          * would do this for 64-bits but historically we have
1898                          * always fallen back to 32-bits.
1899                          */
1900                         return -ENOMEM;
1901                 } else {
1902                         dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1903                         set_dma_ops(&pdev->dev, &dma_iommu_ops);
1904                 }
1905         }
1906         *pdev->dev.dma_mask = dma_mask;
1907
1908         /* Update peer npu devices */
1909         pnv_npu_try_dma_set_bypass(pdev, bypass);
1910
1911         return 0;
1912 }
1913
1914 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1915 {
1916         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1917         struct pnv_phb *phb = hose->private_data;
1918         struct pci_dn *pdn = pci_get_pdn(pdev);
1919         struct pnv_ioda_pe *pe;
1920         u64 end, mask;
1921
1922         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1923                 return 0;
1924
1925         pe = &phb->ioda.pe_array[pdn->pe_number];
1926         if (!pe->tce_bypass_enabled)
1927                 return __dma_get_required_mask(&pdev->dev);
1928
1929
1930         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1931         mask = 1ULL << (fls64(end) - 1);
1932         mask += mask - 1;
1933
1934         return mask;
1935 }
1936
1937 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1938 {
1939         struct pci_dev *dev;
1940
1941         list_for_each_entry(dev, &bus->devices, bus_list) {
1942                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1943                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1944
1945                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1946                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1947         }
1948 }
1949
1950 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1951                                                      bool real_mode)
1952 {
1953         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1954                 (phb->regs + 0x210);
1955 }
1956
1957 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1958                 unsigned long index, unsigned long npages, bool rm)
1959 {
1960         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1961                         &tbl->it_group_list, struct iommu_table_group_link,
1962                         next);
1963         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1964                         struct pnv_ioda_pe, table_group);
1965         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1966         unsigned long start, end, inc;
1967
1968         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1969         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1970                         npages - 1);
1971
1972         /* p7ioc-style invalidation, 2 TCEs per write */
1973         start |= (1ull << 63);
1974         end |= (1ull << 63);
1975         inc = 16;
1976         end |= inc - 1; /* round up end to be different than start */
1977
1978         mb(); /* Ensure above stores are visible */
1979         while (start <= end) {
1980                 if (rm)
1981                         __raw_rm_writeq_be(start, invalidate);
1982                 else
1983                         __raw_writeq_be(start, invalidate);
1984
1985                 start += inc;
1986         }
1987
1988         /*
1989          * The iommu layer will do another mb() for us on build()
1990          * and we don't care on free()
1991          */
1992 }
1993
1994 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1995                 long npages, unsigned long uaddr,
1996                 enum dma_data_direction direction,
1997                 unsigned long attrs)
1998 {
1999         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2000                         attrs);
2001
2002         if (!ret)
2003                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2004
2005         return ret;
2006 }
2007
2008 #ifdef CONFIG_IOMMU_API
2009 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
2010                 unsigned long *hpa, enum dma_data_direction *direction)
2011 {
2012         long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2013
2014         if (!ret)
2015                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
2016
2017         return ret;
2018 }
2019
2020 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
2021                 unsigned long *hpa, enum dma_data_direction *direction)
2022 {
2023         long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2024
2025         if (!ret)
2026                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
2027
2028         return ret;
2029 }
2030 #endif
2031
2032 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
2033                 long npages)
2034 {
2035         pnv_tce_free(tbl, index, npages);
2036
2037         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2038 }
2039
2040 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
2041         .set = pnv_ioda1_tce_build,
2042 #ifdef CONFIG_IOMMU_API
2043         .exchange = pnv_ioda1_tce_xchg,
2044         .exchange_rm = pnv_ioda1_tce_xchg_rm,
2045         .useraddrptr = pnv_tce_useraddrptr,
2046 #endif
2047         .clear = pnv_ioda1_tce_free,
2048         .get = pnv_tce_get,
2049 };
2050
2051 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
2052 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
2053 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
2054
2055 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2056 {
2057         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2058         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2059
2060         mb(); /* Ensure previous TCE table stores are visible */
2061         if (rm)
2062                 __raw_rm_writeq_be(val, invalidate);
2063         else
2064                 __raw_writeq_be(val, invalidate);
2065 }
2066
2067 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2068 {
2069         /* 01xb - invalidate TCEs that match the specified PE# */
2070         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2071         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2072
2073         mb(); /* Ensure above stores are visible */
2074         __raw_writeq_be(val, invalidate);
2075 }
2076
2077 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2078                                         unsigned shift, unsigned long index,
2079                                         unsigned long npages)
2080 {
2081         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2082         unsigned long start, end, inc;
2083
2084         /* We'll invalidate DMA address in PE scope */
2085         start = PHB3_TCE_KILL_INVAL_ONE;
2086         start |= (pe->pe_number & 0xFF);
2087         end = start;
2088
2089         /* Figure out the start, end and step */
2090         start |= (index << shift);
2091         end |= ((index + npages - 1) << shift);
2092         inc = (0x1ull << shift);
2093         mb();
2094
2095         while (start <= end) {
2096                 if (rm)
2097                         __raw_rm_writeq_be(start, invalidate);
2098                 else
2099                         __raw_writeq_be(start, invalidate);
2100                 start += inc;
2101         }
2102 }
2103
2104 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2105 {
2106         struct pnv_phb *phb = pe->phb;
2107
2108         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2109                 pnv_pci_phb3_tce_invalidate_pe(pe);
2110         else
2111                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2112                                   pe->pe_number, 0, 0, 0);
2113 }
2114
2115 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2116                 unsigned long index, unsigned long npages, bool rm)
2117 {
2118         struct iommu_table_group_link *tgl;
2119
2120         list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2121                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2122                                 struct pnv_ioda_pe, table_group);
2123                 struct pnv_phb *phb = pe->phb;
2124                 unsigned int shift = tbl->it_page_shift;
2125
2126                 /*
2127                  * NVLink1 can use the TCE kill register directly as
2128                  * it's the same as PHB3. NVLink2 is different and
2129                  * should go via the OPAL call.
2130                  */
2131                 if (phb->model == PNV_PHB_MODEL_NPU) {
2132                         /*
2133                          * The NVLink hardware does not support TCE kill
2134                          * per TCE entry so we have to invalidate
2135                          * the entire cache for it.
2136                          */
2137                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2138                         continue;
2139                 }
2140                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2141                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2142                                                     index, npages);
2143                 else
2144                         opal_pci_tce_kill(phb->opal_id,
2145                                           OPAL_PCI_TCE_KILL_PAGES,
2146                                           pe->pe_number, 1u << shift,
2147                                           index << shift, npages);
2148         }
2149 }
2150
2151 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2152 {
2153         if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2154                 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2155         else
2156                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2157 }
2158
2159 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2160                 long npages, unsigned long uaddr,
2161                 enum dma_data_direction direction,
2162                 unsigned long attrs)
2163 {
2164         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2165                         attrs);
2166
2167         if (!ret)
2168                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2169
2170         return ret;
2171 }
2172
2173 #ifdef CONFIG_IOMMU_API
2174 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2175                 unsigned long *hpa, enum dma_data_direction *direction)
2176 {
2177         long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2178
2179         if (!ret)
2180                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2181
2182         return ret;
2183 }
2184
2185 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2186                 unsigned long *hpa, enum dma_data_direction *direction)
2187 {
2188         long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2189
2190         if (!ret)
2191                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2192
2193         return ret;
2194 }
2195 #endif
2196
2197 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2198                 long npages)
2199 {
2200         pnv_tce_free(tbl, index, npages);
2201
2202         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2203 }
2204
2205 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2206         .set = pnv_ioda2_tce_build,
2207 #ifdef CONFIG_IOMMU_API
2208         .exchange = pnv_ioda2_tce_xchg,
2209         .exchange_rm = pnv_ioda2_tce_xchg_rm,
2210         .useraddrptr = pnv_tce_useraddrptr,
2211 #endif
2212         .clear = pnv_ioda2_tce_free,
2213         .get = pnv_tce_get,
2214         .free = pnv_pci_ioda2_table_free_pages,
2215 };
2216
2217 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2218 {
2219         unsigned int *weight = (unsigned int *)data;
2220
2221         /* This is quite simplistic. The "base" weight of a device
2222          * is 10. 0 means no DMA is to be accounted for it.
2223          */
2224         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2225                 return 0;
2226
2227         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2228             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2229             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2230                 *weight += 3;
2231         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2232                 *weight += 15;
2233         else
2234                 *weight += 10;
2235
2236         return 0;
2237 }
2238
2239 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2240 {
2241         unsigned int weight = 0;
2242
2243         /* SRIOV VF has same DMA32 weight as its PF */
2244 #ifdef CONFIG_PCI_IOV
2245         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2246                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2247                 return weight;
2248         }
2249 #endif
2250
2251         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2252                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2253         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2254                 struct pci_dev *pdev;
2255
2256                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2257                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2258         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2259                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2260         }
2261
2262         return weight;
2263 }
2264
2265 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2266                                        struct pnv_ioda_pe *pe)
2267 {
2268
2269         struct page *tce_mem = NULL;
2270         struct iommu_table *tbl;
2271         unsigned int weight, total_weight = 0;
2272         unsigned int tce32_segsz, base, segs, avail, i;
2273         int64_t rc;
2274         void *addr;
2275
2276         /* XXX FIXME: Handle 64-bit only DMA devices */
2277         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2278         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2279         weight = pnv_pci_ioda_pe_dma_weight(pe);
2280         if (!weight)
2281                 return;
2282
2283         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2284                      &total_weight);
2285         segs = (weight * phb->ioda.dma32_count) / total_weight;
2286         if (!segs)
2287                 segs = 1;
2288
2289         /*
2290          * Allocate contiguous DMA32 segments. We begin with the expected
2291          * number of segments. With one more attempt, the number of DMA32
2292          * segments to be allocated is decreased by one until one segment
2293          * is allocated successfully.
2294          */
2295         do {
2296                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2297                         for (avail = 0, i = base; i < base + segs; i++) {
2298                                 if (phb->ioda.dma32_segmap[i] ==
2299                                     IODA_INVALID_PE)
2300                                         avail++;
2301                         }
2302
2303                         if (avail == segs)
2304                                 goto found;
2305                 }
2306         } while (--segs);
2307
2308         if (!segs) {
2309                 pe_warn(pe, "No available DMA32 segments\n");
2310                 return;
2311         }
2312
2313 found:
2314         tbl = pnv_pci_table_alloc(phb->hose->node);
2315         if (WARN_ON(!tbl))
2316                 return;
2317
2318         iommu_register_group(&pe->table_group, phb->hose->global_number,
2319                         pe->pe_number);
2320         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2321
2322         /* Grab a 32-bit TCE table */
2323         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2324                 weight, total_weight, base, segs);
2325         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2326                 base * PNV_IODA1_DMA32_SEGSIZE,
2327                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2328
2329         /* XXX Currently, we allocate one big contiguous table for the
2330          * TCEs. We only really need one chunk per 256M of TCE space
2331          * (ie per segment) but that's an optimization for later, it
2332          * requires some added smarts with our get/put_tce implementation
2333          *
2334          * Each TCE page is 4KB in size and each TCE entry occupies 8
2335          * bytes
2336          */
2337         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2338         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2339                                    get_order(tce32_segsz * segs));
2340         if (!tce_mem) {
2341                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2342                 goto fail;
2343         }
2344         addr = page_address(tce_mem);
2345         memset(addr, 0, tce32_segsz * segs);
2346
2347         /* Configure HW */
2348         for (i = 0; i < segs; i++) {
2349                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2350                                               pe->pe_number,
2351                                               base + i, 1,
2352                                               __pa(addr) + tce32_segsz * i,
2353                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2354                 if (rc) {
2355                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2356                                " err %ld\n", rc);
2357                         goto fail;
2358                 }
2359         }
2360
2361         /* Setup DMA32 segment mapping */
2362         for (i = base; i < base + segs; i++)
2363                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2364
2365         /* Setup linux iommu table */
2366         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2367                                   base * PNV_IODA1_DMA32_SEGSIZE,
2368                                   IOMMU_PAGE_SHIFT_4K);
2369
2370         tbl->it_ops = &pnv_ioda1_iommu_ops;
2371         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2372         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2373         iommu_init_table(tbl, phb->hose->node);
2374
2375         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2376                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2377
2378         return;
2379  fail:
2380         /* XXX Failure: Try to fallback to 64-bit only ? */
2381         if (tce_mem)
2382                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2383         if (tbl) {
2384                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2385                 iommu_tce_table_put(tbl);
2386         }
2387 }
2388
2389 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2390                 int num, struct iommu_table *tbl)
2391 {
2392         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2393                         table_group);
2394         struct pnv_phb *phb = pe->phb;
2395         int64_t rc;
2396         const unsigned long size = tbl->it_indirect_levels ?
2397                         tbl->it_level_size : tbl->it_size;
2398         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2399         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2400
2401         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2402                         start_addr, start_addr + win_size - 1,
2403                         IOMMU_PAGE_SIZE(tbl));
2404
2405         /*
2406          * Map TCE table through TVT. The TVE index is the PE number
2407          * shifted by 1 bit for 32-bits DMA space.
2408          */
2409         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2410                         pe->pe_number,
2411                         (pe->pe_number << 1) + num,
2412                         tbl->it_indirect_levels + 1,
2413                         __pa(tbl->it_base),
2414                         size << 3,
2415                         IOMMU_PAGE_SIZE(tbl));
2416         if (rc) {
2417                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2418                 return rc;
2419         }
2420
2421         pnv_pci_link_table_and_group(phb->hose->node, num,
2422                         tbl, &pe->table_group);
2423         pnv_pci_ioda2_tce_invalidate_pe(pe);
2424
2425         return 0;
2426 }
2427
2428 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2429 {
2430         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2431         int64_t rc;
2432
2433         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2434         if (enable) {
2435                 phys_addr_t top = memblock_end_of_DRAM();
2436
2437                 top = roundup_pow_of_two(top);
2438                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2439                                                      pe->pe_number,
2440                                                      window_id,
2441                                                      pe->tce_bypass_base,
2442                                                      top);
2443         } else {
2444                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2445                                                      pe->pe_number,
2446                                                      window_id,
2447                                                      pe->tce_bypass_base,
2448                                                      0);
2449         }
2450         if (rc)
2451                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2452         else
2453                 pe->tce_bypass_enabled = enable;
2454 }
2455
2456 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2457                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2458                 bool alloc_userspace_copy, struct iommu_table **ptbl)
2459 {
2460         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2461                         table_group);
2462         int nid = pe->phb->hose->node;
2463         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2464         long ret;
2465         struct iommu_table *tbl;
2466
2467         tbl = pnv_pci_table_alloc(nid);
2468         if (!tbl)
2469                 return -ENOMEM;
2470
2471         tbl->it_ops = &pnv_ioda2_iommu_ops;
2472
2473         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2474                         bus_offset, page_shift, window_size,
2475                         levels, alloc_userspace_copy, tbl);
2476         if (ret) {
2477                 iommu_tce_table_put(tbl);
2478                 return ret;
2479         }
2480
2481         *ptbl = tbl;
2482
2483         return 0;
2484 }
2485
2486 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2487 {
2488         struct iommu_table *tbl = NULL;
2489         long rc;
2490
2491         /*
2492          * crashkernel= specifies the kdump kernel's maximum memory at
2493          * some offset and there is no guaranteed the result is a power
2494          * of 2, which will cause errors later.
2495          */
2496         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2497
2498         /*
2499          * In memory constrained environments, e.g. kdump kernel, the
2500          * DMA window can be larger than available memory, which will
2501          * cause errors later.
2502          */
2503         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2504
2505         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2506                         IOMMU_PAGE_SHIFT_4K,
2507                         window_size,
2508                         POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl);
2509         if (rc) {
2510                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2511                                 rc);
2512                 return rc;
2513         }
2514
2515         iommu_init_table(tbl, pe->phb->hose->node);
2516
2517         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2518         if (rc) {
2519                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2520                                 rc);
2521                 iommu_tce_table_put(tbl);
2522                 return rc;
2523         }
2524
2525         if (!pnv_iommu_bypass_disabled)
2526                 pnv_pci_ioda2_set_bypass(pe, true);
2527
2528         return 0;
2529 }
2530
2531 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2532 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2533                 int num)
2534 {
2535         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2536                         table_group);
2537         struct pnv_phb *phb = pe->phb;
2538         long ret;
2539
2540         pe_info(pe, "Removing DMA window #%d\n", num);
2541
2542         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2543                         (pe->pe_number << 1) + num,
2544                         0/* levels */, 0/* table address */,
2545                         0/* table size */, 0/* page size */);
2546         if (ret)
2547                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2548         else
2549                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2550
2551         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2552
2553         return ret;
2554 }
2555 #endif
2556
2557 #ifdef CONFIG_IOMMU_API
2558 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2559                 __u64 window_size, __u32 levels)
2560 {
2561         unsigned long bytes = 0;
2562         const unsigned window_shift = ilog2(window_size);
2563         unsigned entries_shift = window_shift - page_shift;
2564         unsigned table_shift = entries_shift + 3;
2565         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2566         unsigned long direct_table_size;
2567
2568         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2569                         !is_power_of_2(window_size))
2570                 return 0;
2571
2572         /* Calculate a direct table size from window_size and levels */
2573         entries_shift = (entries_shift + levels - 1) / levels;
2574         table_shift = entries_shift + 3;
2575         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2576         direct_table_size =  1UL << table_shift;
2577
2578         for ( ; levels; --levels) {
2579                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2580
2581                 tce_table_size /= direct_table_size;
2582                 tce_table_size <<= 3;
2583                 tce_table_size = max_t(unsigned long,
2584                                 tce_table_size, direct_table_size);
2585         }
2586
2587         return bytes + bytes; /* one for HW table, one for userspace copy */
2588 }
2589
2590 static long pnv_pci_ioda2_create_table_userspace(
2591                 struct iommu_table_group *table_group,
2592                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2593                 struct iommu_table **ptbl)
2594 {
2595         return pnv_pci_ioda2_create_table(table_group,
2596                         num, page_shift, window_size, levels, true, ptbl);
2597 }
2598
2599 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2600 {
2601         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2602                                                 table_group);
2603         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2604         struct iommu_table *tbl = pe->table_group.tables[0];
2605
2606         pnv_pci_ioda2_set_bypass(pe, false);
2607         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2608         if (pe->pbus)
2609                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2610         iommu_tce_table_put(tbl);
2611 }
2612
2613 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2614 {
2615         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2616                                                 table_group);
2617
2618         pnv_pci_ioda2_setup_default_config(pe);
2619         if (pe->pbus)
2620                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2621 }
2622
2623 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2624         .get_table_size = pnv_pci_ioda2_get_table_size,
2625         .create_table = pnv_pci_ioda2_create_table_userspace,
2626         .set_window = pnv_pci_ioda2_set_window,
2627         .unset_window = pnv_pci_ioda2_unset_window,
2628         .take_ownership = pnv_ioda2_take_ownership,
2629         .release_ownership = pnv_ioda2_release_ownership,
2630 };
2631
2632 static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
2633                 struct iommu_table_group *table_group,
2634                 struct pci_bus *bus)
2635 {
2636         struct pci_dev *dev;
2637
2638         list_for_each_entry(dev, &bus->devices, bus_list) {
2639                 iommu_add_device(table_group, &dev->dev);
2640
2641                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2642                         pnv_ioda_setup_bus_iommu_group_add_devices(pe,
2643                                         table_group, dev->subordinate);
2644         }
2645 }
2646
2647 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
2648                 struct iommu_table_group *table_group, struct pci_bus *bus)
2649 {
2650
2651         if (pe->flags & PNV_IODA_PE_DEV)
2652                 iommu_add_device(table_group, &pe->pdev->dev);
2653
2654         if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
2655                 pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
2656                                 bus);
2657 }
2658
2659 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
2660
2661 static void pnv_pci_ioda_setup_iommu_api(void)
2662 {
2663         struct pci_controller *hose;
2664         struct pnv_phb *phb;
2665         struct pnv_ioda_pe *pe;
2666
2667         /*
2668          * There are 4 types of PEs:
2669          * - PNV_IODA_PE_BUS: a downstream port with an adapter,
2670          *   created from pnv_pci_setup_bridge();
2671          * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
2672          *   created from pnv_pci_setup_bridge();
2673          * - PNV_IODA_PE_VF: a SRIOV virtual function,
2674          *   created from pnv_pcibios_sriov_enable();
2675          * - PNV_IODA_PE_DEV: an NPU or OCAPI device,
2676          *   created from pnv_pci_ioda_fixup().
2677          *
2678          * Normally a PE is represented by an IOMMU group, however for
2679          * devices with side channels the groups need to be more strict.
2680          */
2681         list_for_each_entry(hose, &hose_list, list_node) {
2682                 phb = hose->private_data;
2683
2684                 if (phb->type == PNV_PHB_NPU_NVLINK)
2685                         continue;
2686
2687                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2688                         struct iommu_table_group *table_group;
2689
2690                         table_group = pnv_try_setup_npu_table_group(pe);
2691                         if (!table_group) {
2692                                 if (!pnv_pci_ioda_pe_dma_weight(pe))
2693                                         continue;
2694
2695                                 table_group = &pe->table_group;
2696                                 iommu_register_group(&pe->table_group,
2697                                                 pe->phb->hose->global_number,
2698                                                 pe->pe_number);
2699                         }
2700                         pnv_ioda_setup_bus_iommu_group(pe, table_group,
2701                                         pe->pbus);
2702                 }
2703         }
2704
2705         /*
2706          * Now we have all PHBs discovered, time to add NPU devices to
2707          * the corresponding IOMMU groups.
2708          */
2709         list_for_each_entry(hose, &hose_list, list_node) {
2710                 unsigned long  pgsizes;
2711
2712                 phb = hose->private_data;
2713
2714                 if (phb->type != PNV_PHB_NPU_NVLINK)
2715                         continue;
2716
2717                 pgsizes = pnv_ioda_parse_tce_sizes(phb);
2718                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2719                         /*
2720                          * IODA2 bridges get this set up from
2721                          * pci_controller_ops::setup_bridge but NPU bridges
2722                          * do not have this hook defined so we do it here.
2723                          */
2724                         pe->table_group.pgsizes = pgsizes;
2725                         pnv_npu_compound_attach(pe);
2726                 }
2727         }
2728 }
2729 #else /* !CONFIG_IOMMU_API */
2730 static void pnv_pci_ioda_setup_iommu_api(void) { };
2731 #endif
2732
2733 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2734 {
2735         struct pci_controller *hose = phb->hose;
2736         struct device_node *dn = hose->dn;
2737         unsigned long mask = 0;
2738         int i, rc, count;
2739         u32 val;
2740
2741         count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2742         if (count <= 0) {
2743                 mask = SZ_4K | SZ_64K;
2744                 /* Add 16M for POWER8 by default */
2745                 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2746                                 !cpu_has_feature(CPU_FTR_ARCH_300))
2747                         mask |= SZ_16M | SZ_256M;
2748                 return mask;
2749         }
2750
2751         for (i = 0; i < count; i++) {
2752                 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2753                                                 i, &val);
2754                 if (rc == 0)
2755                         mask |= 1ULL << val;
2756         }
2757
2758         return mask;
2759 }
2760
2761 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2762                                        struct pnv_ioda_pe *pe)
2763 {
2764         int64_t rc;
2765
2766         if (!pnv_pci_ioda_pe_dma_weight(pe))
2767                 return;
2768
2769         /* TVE #1 is selected by PCI address bit 59 */
2770         pe->tce_bypass_base = 1ull << 59;
2771
2772         /* The PE will reserve all possible 32-bits space */
2773         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2774                 phb->ioda.m32_pci_base);
2775
2776         /* Setup linux iommu table */
2777         pe->table_group.tce32_start = 0;
2778         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2779         pe->table_group.max_dynamic_windows_supported =
2780                         IOMMU_TABLE_GROUP_MAX_TABLES;
2781         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2782         pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2783 #ifdef CONFIG_IOMMU_API
2784         pe->table_group.ops = &pnv_pci_ioda2_ops;
2785 #endif
2786
2787         rc = pnv_pci_ioda2_setup_default_config(pe);
2788         if (rc)
2789                 return;
2790
2791         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2792                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2793 }
2794
2795 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2796 {
2797         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2798                                            ioda.irq_chip);
2799
2800         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2801 }
2802
2803 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2804 {
2805         int64_t rc;
2806         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2807         struct irq_chip *chip = irq_data_get_irq_chip(d);
2808
2809         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2810         WARN_ON_ONCE(rc);
2811
2812         icp_native_eoi(d);
2813 }
2814
2815
2816 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2817 {
2818         struct irq_data *idata;
2819         struct irq_chip *ichip;
2820
2821         /* The MSI EOI OPAL call is only needed on PHB3 */
2822         if (phb->model != PNV_PHB_MODEL_PHB3)
2823                 return;
2824
2825         if (!phb->ioda.irq_chip_init) {
2826                 /*
2827                  * First time we setup an MSI IRQ, we need to setup the
2828                  * corresponding IRQ chip to route correctly.
2829                  */
2830                 idata = irq_get_irq_data(virq);
2831                 ichip = irq_data_get_irq_chip(idata);
2832                 phb->ioda.irq_chip_init = 1;
2833                 phb->ioda.irq_chip = *ichip;
2834                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2835         }
2836         irq_set_chip(virq, &phb->ioda.irq_chip);
2837 }
2838
2839 /*
2840  * Returns true iff chip is something that we could call
2841  * pnv_opal_pci_msi_eoi for.
2842  */
2843 bool is_pnv_opal_msi(struct irq_chip *chip)
2844 {
2845         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2846 }
2847 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2848
2849 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2850                                   unsigned int hwirq, unsigned int virq,
2851                                   unsigned int is_64, struct msi_msg *msg)
2852 {
2853         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2854         unsigned int xive_num = hwirq - phb->msi_base;
2855         __be32 data;
2856         int rc;
2857
2858         /* No PE assigned ? bail out ... no MSI for you ! */
2859         if (pe == NULL)
2860                 return -ENXIO;
2861
2862         /* Check if we have an MVE */
2863         if (pe->mve_number < 0)
2864                 return -ENXIO;
2865
2866         /* Force 32-bit MSI on some broken devices */
2867         if (dev->no_64bit_msi)
2868                 is_64 = 0;
2869
2870         /* Assign XIVE to PE */
2871         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2872         if (rc) {
2873                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2874                         pci_name(dev), rc, xive_num);
2875                 return -EIO;
2876         }
2877
2878         if (is_64) {
2879                 __be64 addr64;
2880
2881                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2882                                      &addr64, &data);
2883                 if (rc) {
2884                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2885                                 pci_name(dev), rc);
2886                         return -EIO;
2887                 }
2888                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2889                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2890         } else {
2891                 __be32 addr32;
2892
2893                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2894                                      &addr32, &data);
2895                 if (rc) {
2896                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2897                                 pci_name(dev), rc);
2898                         return -EIO;
2899                 }
2900                 msg->address_hi = 0;
2901                 msg->address_lo = be32_to_cpu(addr32);
2902         }
2903         msg->data = be32_to_cpu(data);
2904
2905         pnv_set_msi_irq_chip(phb, virq);
2906
2907         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2908                  " address=%x_%08x data=%x PE# %x\n",
2909                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2910                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2911
2912         return 0;
2913 }
2914
2915 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2916 {
2917         unsigned int count;
2918         const __be32 *prop = of_get_property(phb->hose->dn,
2919                                              "ibm,opal-msi-ranges", NULL);
2920         if (!prop) {
2921                 /* BML Fallback */
2922                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2923         }
2924         if (!prop)
2925                 return;
2926
2927         phb->msi_base = be32_to_cpup(prop);
2928         count = be32_to_cpup(prop + 1);
2929         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2930                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2931                        phb->hose->global_number);
2932                 return;
2933         }
2934
2935         phb->msi_setup = pnv_pci_ioda_msi_setup;
2936         phb->msi32_support = 1;
2937         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2938                 count, phb->msi_base);
2939 }
2940
2941 #ifdef CONFIG_PCI_IOV
2942 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2943 {
2944         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2945         struct pnv_phb *phb = hose->private_data;
2946         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2947         struct resource *res;
2948         int i;
2949         resource_size_t size, total_vf_bar_sz;
2950         struct pci_dn *pdn;
2951         int mul, total_vfs;
2952
2953         if (!pdev->is_physfn || pci_dev_is_added(pdev))
2954                 return;
2955
2956         pdn = pci_get_pdn(pdev);
2957         pdn->vfs_expanded = 0;
2958         pdn->m64_single_mode = false;
2959
2960         total_vfs = pci_sriov_get_totalvfs(pdev);
2961         mul = phb->ioda.total_pe_num;
2962         total_vf_bar_sz = 0;
2963
2964         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2965                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2966                 if (!res->flags || res->parent)
2967                         continue;
2968                 if (!pnv_pci_is_m64_flags(res->flags)) {
2969                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
2970                                         " non M64 VF BAR%d: %pR. \n",
2971                                  i, res);
2972                         goto truncate_iov;
2973                 }
2974
2975                 total_vf_bar_sz += pci_iov_resource_size(pdev,
2976                                 i + PCI_IOV_RESOURCES);
2977
2978                 /*
2979                  * If bigger than quarter of M64 segment size, just round up
2980                  * power of two.
2981                  *
2982                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2983                  * with other devices, IOV BAR size is expanded to be
2984                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2985                  * segment size , the expanded size would equal to half of the
2986                  * whole M64 space size, which will exhaust the M64 Space and
2987                  * limit the system flexibility.  This is a design decision to
2988                  * set the boundary to quarter of the M64 segment size.
2989                  */
2990                 if (total_vf_bar_sz > gate) {
2991                         mul = roundup_pow_of_two(total_vfs);
2992                         dev_info(&pdev->dev,
2993                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2994                                 total_vf_bar_sz, gate, mul);
2995                         pdn->m64_single_mode = true;
2996                         break;
2997                 }
2998         }
2999
3000         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3001                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3002                 if (!res->flags || res->parent)
3003                         continue;
3004
3005                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3006                 /*
3007                  * On PHB3, the minimum size alignment of M64 BAR in single
3008                  * mode is 32MB.
3009                  */
3010                 if (pdn->m64_single_mode && (size < SZ_32M))
3011                         goto truncate_iov;
3012                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3013                 res->end = res->start + size * mul - 1;
3014                 dev_dbg(&pdev->dev, "                       %pR\n", res);
3015                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3016                          i, res, mul);
3017         }
3018         pdn->vfs_expanded = mul;
3019
3020         return;
3021
3022 truncate_iov:
3023         /* To save MMIO space, IOV BAR is truncated. */
3024         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3025                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3026                 res->flags = 0;
3027                 res->end = res->start - 1;
3028         }
3029 }
3030 #endif /* CONFIG_PCI_IOV */
3031
3032 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3033                                   struct resource *res)
3034 {
3035         struct pnv_phb *phb = pe->phb;
3036         struct pci_bus_region region;
3037         int index;
3038         int64_t rc;
3039
3040         if (!res || !res->flags || res->start > res->end)
3041                 return;
3042
3043         if (res->flags & IORESOURCE_IO) {
3044                 region.start = res->start - phb->ioda.io_pci_base;
3045                 region.end   = res->end - phb->ioda.io_pci_base;
3046                 index = region.start / phb->ioda.io_segsize;
3047
3048                 while (index < phb->ioda.total_pe_num &&
3049                        region.start <= region.end) {
3050                         phb->ioda.io_segmap[index] = pe->pe_number;
3051                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3052                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3053                         if (rc != OPAL_SUCCESS) {
3054                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3055                                        __func__, rc, index, pe->pe_number);
3056                                 break;
3057                         }
3058
3059                         region.start += phb->ioda.io_segsize;
3060                         index++;
3061                 }
3062         } else if ((res->flags & IORESOURCE_MEM) &&
3063                    !pnv_pci_is_m64(phb, res)) {
3064                 region.start = res->start -
3065                                phb->hose->mem_offset[0] -
3066                                phb->ioda.m32_pci_base;
3067                 region.end   = res->end -
3068                                phb->hose->mem_offset[0] -
3069                                phb->ioda.m32_pci_base;
3070                 index = region.start / phb->ioda.m32_segsize;
3071
3072                 while (index < phb->ioda.total_pe_num &&
3073                        region.start <= region.end) {
3074                         phb->ioda.m32_segmap[index] = pe->pe_number;
3075                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3076                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3077                         if (rc != OPAL_SUCCESS) {
3078                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3079                                        __func__, rc, index, pe->pe_number);
3080                                 break;
3081                         }
3082
3083                         region.start += phb->ioda.m32_segsize;
3084                         index++;
3085                 }
3086         }
3087 }
3088
3089 /*
3090  * This function is supposed to be called on basis of PE from top
3091  * to bottom style. So the the I/O or MMIO segment assigned to
3092  * parent PE could be overridden by its child PEs if necessary.
3093  */
3094 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3095 {
3096         struct pci_dev *pdev;
3097         int i;
3098
3099         /*
3100          * NOTE: We only care PCI bus based PE for now. For PCI
3101          * device based PE, for example SRIOV sensitive VF should
3102          * be figured out later.
3103          */
3104         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3105
3106         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3107                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3108                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3109
3110                 /*
3111                  * If the PE contains all subordinate PCI buses, the
3112                  * windows of the child bridges should be mapped to
3113                  * the PE as well.
3114                  */
3115                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3116                         continue;
3117                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3118                         pnv_ioda_setup_pe_res(pe,
3119                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3120         }
3121 }
3122
3123 #ifdef CONFIG_DEBUG_FS
3124 static int pnv_pci_diag_data_set(void *data, u64 val)
3125 {
3126         struct pci_controller *hose;
3127         struct pnv_phb *phb;
3128         s64 ret;
3129
3130         if (val != 1ULL)
3131                 return -EINVAL;
3132
3133         hose = (struct pci_controller *)data;
3134         if (!hose || !hose->private_data)
3135                 return -ENODEV;
3136
3137         phb = hose->private_data;
3138
3139         /* Retrieve the diag data from firmware */
3140         ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3141                                           phb->diag_data_size);
3142         if (ret != OPAL_SUCCESS)
3143                 return -EIO;
3144
3145         /* Print the diag data to the kernel log */
3146         pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3147         return 0;
3148 }
3149
3150 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3151                         pnv_pci_diag_data_set, "%llu\n");
3152
3153 #endif /* CONFIG_DEBUG_FS */
3154
3155 static void pnv_pci_ioda_create_dbgfs(void)
3156 {
3157 #ifdef CONFIG_DEBUG_FS
3158         struct pci_controller *hose, *tmp;
3159         struct pnv_phb *phb;
3160         char name[16];
3161
3162         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3163                 phb = hose->private_data;
3164
3165                 /* Notify initialization of PHB done */
3166                 phb->initialized = 1;
3167
3168                 sprintf(name, "PCI%04x", hose->global_number);
3169                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3170                 if (!phb->dbgfs) {
3171                         pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3172                                 __func__, hose->global_number);
3173                         continue;
3174                 }
3175
3176                 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3177                                     &pnv_pci_diag_data_fops);
3178         }
3179 #endif /* CONFIG_DEBUG_FS */
3180 }
3181
3182 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3183 {
3184         struct pci_dev *dev = bus->self;
3185         struct pci_bus *child;
3186
3187         /* Empty bus ? bail */
3188         if (list_empty(&bus->devices))
3189                 return;
3190
3191         /*
3192          * If there's a bridge associated with that bus enable it. This works
3193          * around races in the generic code if the enabling is done during
3194          * parallel probing. This can be removed once those races have been
3195          * fixed.
3196          */
3197         if (dev) {
3198                 int rc = pci_enable_device(dev);
3199                 if (rc)
3200                         pci_err(dev, "Error enabling bridge (%d)\n", rc);
3201                 pci_set_master(dev);
3202         }
3203
3204         /* Perform the same to child busses */
3205         list_for_each_entry(child, &bus->children, node)
3206                 pnv_pci_enable_bridge(child);
3207 }
3208
3209 static void pnv_pci_enable_bridges(void)
3210 {
3211         struct pci_controller *hose;
3212
3213         list_for_each_entry(hose, &hose_list, list_node)
3214                 pnv_pci_enable_bridge(hose->bus);
3215 }
3216
3217 static void pnv_pci_ioda_fixup(void)
3218 {
3219         pnv_pci_ioda_setup_PEs();
3220         pnv_pci_ioda_setup_iommu_api();
3221         pnv_pci_ioda_create_dbgfs();
3222
3223         pnv_pci_enable_bridges();
3224
3225 #ifdef CONFIG_EEH
3226         pnv_eeh_post_init();
3227 #endif
3228 }
3229
3230 /*
3231  * Returns the alignment for I/O or memory windows for P2P
3232  * bridges. That actually depends on how PEs are segmented.
3233  * For now, we return I/O or M32 segment size for PE sensitive
3234  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3235  * 1MiB for memory) will be returned.
3236  *
3237  * The current PCI bus might be put into one PE, which was
3238  * create against the parent PCI bridge. For that case, we
3239  * needn't enlarge the alignment so that we can save some
3240  * resources.
3241  */
3242 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3243                                                 unsigned long type)
3244 {
3245         struct pci_dev *bridge;
3246         struct pci_controller *hose = pci_bus_to_host(bus);
3247         struct pnv_phb *phb = hose->private_data;
3248         int num_pci_bridges = 0;
3249
3250         bridge = bus->self;
3251         while (bridge) {
3252                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3253                         num_pci_bridges++;
3254                         if (num_pci_bridges >= 2)
3255                                 return 1;
3256                 }
3257
3258                 bridge = bridge->bus->self;
3259         }
3260
3261         /*
3262          * We fall back to M32 if M64 isn't supported. We enforce the M64
3263          * alignment for any 64-bit resource, PCIe doesn't care and
3264          * bridges only do 64-bit prefetchable anyway.
3265          */
3266         if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3267                 return phb->ioda.m64_segsize;
3268         if (type & IORESOURCE_MEM)
3269                 return phb->ioda.m32_segsize;
3270
3271         return phb->ioda.io_segsize;
3272 }
3273
3274 /*
3275  * We are updating root port or the upstream port of the
3276  * bridge behind the root port with PHB's windows in order
3277  * to accommodate the changes on required resources during
3278  * PCI (slot) hotplug, which is connected to either root
3279  * port or the downstream ports of PCIe switch behind the
3280  * root port.
3281  */
3282 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3283                                            unsigned long type)
3284 {
3285         struct pci_controller *hose = pci_bus_to_host(bus);
3286         struct pnv_phb *phb = hose->private_data;
3287         struct pci_dev *bridge = bus->self;
3288         struct resource *r, *w;
3289         bool msi_region = false;
3290         int i;
3291
3292         /* Check if we need apply fixup to the bridge's windows */
3293         if (!pci_is_root_bus(bridge->bus) &&
3294             !pci_is_root_bus(bridge->bus->self->bus))
3295                 return;
3296
3297         /* Fixup the resources */
3298         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3299                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3300                 if (!r->flags || !r->parent)
3301                         continue;
3302
3303                 w = NULL;
3304                 if (r->flags & type & IORESOURCE_IO)
3305                         w = &hose->io_resource;
3306                 else if (pnv_pci_is_m64(phb, r) &&
3307                          (type & IORESOURCE_PREFETCH) &&
3308                          phb->ioda.m64_segsize)
3309                         w = &hose->mem_resources[1];
3310                 else if (r->flags & type & IORESOURCE_MEM) {
3311                         w = &hose->mem_resources[0];
3312                         msi_region = true;
3313                 }
3314
3315                 r->start = w->start;
3316                 r->end = w->end;
3317
3318                 /* The 64KB 32-bits MSI region shouldn't be included in
3319                  * the 32-bits bridge window. Otherwise, we can see strange
3320                  * issues. One of them is EEH error observed on Garrison.
3321                  *
3322                  * Exclude top 1MB region which is the minimal alignment of
3323                  * 32-bits bridge window.
3324                  */
3325                 if (msi_region) {
3326                         r->end += 0x10000;
3327                         r->end -= 0x100000;
3328                 }
3329         }
3330 }
3331
3332 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3333 {
3334         struct pci_controller *hose = pci_bus_to_host(bus);
3335         struct pnv_phb *phb = hose->private_data;
3336         struct pci_dev *bridge = bus->self;
3337         struct pnv_ioda_pe *pe;
3338         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3339
3340         /* Extend bridge's windows if necessary */
3341         pnv_pci_fixup_bridge_resources(bus, type);
3342
3343         /* The PE for root bus should be realized before any one else */
3344         if (!phb->ioda.root_pe_populated) {
3345                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3346                 if (pe) {
3347                         phb->ioda.root_pe_idx = pe->pe_number;
3348                         phb->ioda.root_pe_populated = true;
3349                 }
3350         }
3351
3352         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3353         if (list_empty(&bus->devices))
3354                 return;
3355
3356         /* Reserve PEs according to used M64 resources */
3357         pnv_ioda_reserve_m64_pe(bus, NULL, all);
3358
3359         /*
3360          * Assign PE. We might run here because of partial hotplug.
3361          * For the case, we just pick up the existing PE and should
3362          * not allocate resources again.
3363          */
3364         pe = pnv_ioda_setup_bus_PE(bus, all);
3365         if (!pe)
3366                 return;
3367
3368         pnv_ioda_setup_pe_seg(pe);
3369         switch (phb->type) {
3370         case PNV_PHB_IODA1:
3371                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3372                 break;
3373         case PNV_PHB_IODA2:
3374                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3375                 break;
3376         default:
3377                 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3378                         __func__, phb->hose->global_number, phb->type);
3379         }
3380 }
3381
3382 static resource_size_t pnv_pci_default_alignment(void)
3383 {
3384         return PAGE_SIZE;
3385 }
3386
3387 #ifdef CONFIG_PCI_IOV
3388 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3389                                                       int resno)
3390 {
3391         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3392         struct pnv_phb *phb = hose->private_data;
3393         struct pci_dn *pdn = pci_get_pdn(pdev);
3394         resource_size_t align;
3395
3396         /*
3397          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3398          * SR-IOV. While from hardware perspective, the range mapped by M64
3399          * BAR should be size aligned.
3400          *
3401          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3402          * powernv-specific hardware restriction is gone. But if just use the
3403          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3404          * in one segment of M64 #15, which introduces the PE conflict between
3405          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3406          * m64_segsize.
3407          *
3408          * This function returns the total IOV BAR size if M64 BAR is in
3409          * Shared PE mode or just VF BAR size if not.
3410          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3411          * M64 segment size if IOV BAR size is less.
3412          */
3413         align = pci_iov_resource_size(pdev, resno);
3414         if (!pdn->vfs_expanded)
3415                 return align;
3416         if (pdn->m64_single_mode)
3417                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3418
3419         return pdn->vfs_expanded * align;
3420 }
3421 #endif /* CONFIG_PCI_IOV */
3422
3423 /* Prevent enabling devices for which we couldn't properly
3424  * assign a PE
3425  */
3426 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3427 {
3428         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3429         struct pnv_phb *phb = hose->private_data;
3430         struct pci_dn *pdn;
3431
3432         /* The function is probably called while the PEs have
3433          * not be created yet. For example, resource reassignment
3434          * during PCI probe period. We just skip the check if
3435          * PEs isn't ready.
3436          */
3437         if (!phb->initialized)
3438                 return true;
3439
3440         pdn = pci_get_pdn(dev);
3441         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3442                 return false;
3443
3444         return true;
3445 }
3446
3447 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3448                                        int num)
3449 {
3450         struct pnv_ioda_pe *pe = container_of(table_group,
3451                                               struct pnv_ioda_pe, table_group);
3452         struct pnv_phb *phb = pe->phb;
3453         unsigned int idx;
3454         long rc;
3455
3456         pe_info(pe, "Removing DMA window #%d\n", num);
3457         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3458                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3459                         continue;
3460
3461                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3462                                                 idx, 0, 0ul, 0ul, 0ul);
3463                 if (rc != OPAL_SUCCESS) {
3464                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3465                                 rc, idx);
3466                         return rc;
3467                 }
3468
3469                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3470         }
3471
3472         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3473         return OPAL_SUCCESS;
3474 }
3475
3476 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3477 {
3478         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3479         struct iommu_table *tbl = pe->table_group.tables[0];
3480         int64_t rc;
3481
3482         if (!weight)
3483                 return;
3484
3485         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3486         if (rc != OPAL_SUCCESS)
3487                 return;
3488
3489         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3490         if (pe->table_group.group) {
3491                 iommu_group_put(pe->table_group.group);
3492                 WARN_ON(pe->table_group.group);
3493         }
3494
3495         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3496         iommu_tce_table_put(tbl);
3497 }
3498
3499 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3500 {
3501         struct iommu_table *tbl = pe->table_group.tables[0];
3502         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3503 #ifdef CONFIG_IOMMU_API
3504         int64_t rc;
3505 #endif
3506
3507         if (!weight)
3508                 return;
3509
3510 #ifdef CONFIG_IOMMU_API
3511         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3512         if (rc)
3513                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3514 #endif
3515
3516         pnv_pci_ioda2_set_bypass(pe, false);
3517         if (pe->table_group.group) {
3518                 iommu_group_put(pe->table_group.group);
3519                 WARN_ON(pe->table_group.group);
3520         }
3521
3522         iommu_tce_table_put(tbl);
3523 }
3524
3525 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3526                                  unsigned short win,
3527                                  unsigned int *map)
3528 {
3529         struct pnv_phb *phb = pe->phb;
3530         int idx;
3531         int64_t rc;
3532
3533         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3534                 if (map[idx] != pe->pe_number)
3535                         continue;
3536
3537                 if (win == OPAL_M64_WINDOW_TYPE)
3538                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3539                                         phb->ioda.reserved_pe_idx, win,
3540                                         idx / PNV_IODA1_M64_SEGS,
3541                                         idx % PNV_IODA1_M64_SEGS);
3542                 else
3543                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3544                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3545
3546                 if (rc != OPAL_SUCCESS)
3547                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3548                                 rc, win, idx);
3549
3550                 map[idx] = IODA_INVALID_PE;
3551         }
3552 }
3553
3554 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3555 {
3556         struct pnv_phb *phb = pe->phb;
3557
3558         if (phb->type == PNV_PHB_IODA1) {
3559                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3560                                      phb->ioda.io_segmap);
3561                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3562                                      phb->ioda.m32_segmap);
3563                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3564                                      phb->ioda.m64_segmap);
3565         } else if (phb->type == PNV_PHB_IODA2) {
3566                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3567                                      phb->ioda.m32_segmap);
3568         }
3569 }
3570
3571 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3572 {
3573         struct pnv_phb *phb = pe->phb;
3574         struct pnv_ioda_pe *slave, *tmp;
3575
3576         list_del(&pe->list);
3577         switch (phb->type) {
3578         case PNV_PHB_IODA1:
3579                 pnv_pci_ioda1_release_pe_dma(pe);
3580                 break;
3581         case PNV_PHB_IODA2:
3582                 pnv_pci_ioda2_release_pe_dma(pe);
3583                 break;
3584         default:
3585                 WARN_ON(1);
3586         }
3587
3588         pnv_ioda_release_pe_seg(pe);
3589         pnv_ioda_deconfigure_pe(pe->phb, pe);
3590
3591         /* Release slave PEs in the compound PE */
3592         if (pe->flags & PNV_IODA_PE_MASTER) {
3593                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3594                         list_del(&slave->list);
3595                         pnv_ioda_free_pe(slave);
3596                 }
3597         }
3598
3599         /*
3600          * The PE for root bus can be removed because of hotplug in EEH
3601          * recovery for fenced PHB error. We need to mark the PE dead so
3602          * that it can be populated again in PCI hot add path. The PE
3603          * shouldn't be destroyed as it's the global reserved resource.
3604          */
3605         if (phb->ioda.root_pe_populated &&
3606             phb->ioda.root_pe_idx == pe->pe_number)
3607                 phb->ioda.root_pe_populated = false;
3608         else
3609                 pnv_ioda_free_pe(pe);
3610 }
3611
3612 static void pnv_pci_release_device(struct pci_dev *pdev)
3613 {
3614         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3615         struct pnv_phb *phb = hose->private_data;
3616         struct pci_dn *pdn = pci_get_pdn(pdev);
3617         struct pnv_ioda_pe *pe;
3618
3619         if (pdev->is_virtfn)
3620                 return;
3621
3622         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3623                 return;
3624
3625         /*
3626          * PCI hotplug can happen as part of EEH error recovery. The @pdn
3627          * isn't removed and added afterwards in this scenario. We should
3628          * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3629          * device count is decreased on removing devices while failing to
3630          * be increased on adding devices. It leads to unbalanced PE's device
3631          * count and eventually make normal PCI hotplug path broken.
3632          */
3633         pe = &phb->ioda.pe_array[pdn->pe_number];
3634         pdn->pe_number = IODA_INVALID_PE;
3635
3636         WARN_ON(--pe->device_count < 0);
3637         if (pe->device_count == 0)
3638                 pnv_ioda_release_pe(pe);
3639 }
3640
3641 static void pnv_npu_disable_device(struct pci_dev *pdev)
3642 {
3643         struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
3644         struct eeh_pe *eehpe = edev ? edev->pe : NULL;
3645
3646         if (eehpe && eeh_ops && eeh_ops->reset)
3647                 eeh_ops->reset(eehpe, EEH_RESET_HOT);
3648 }
3649
3650 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3651 {
3652         struct pnv_phb *phb = hose->private_data;
3653
3654         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3655                        OPAL_ASSERT_RESET);
3656 }
3657
3658 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3659         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3660         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3661         .setup_msi_irqs         = pnv_setup_msi_irqs,
3662         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3663         .enable_device_hook     = pnv_pci_enable_device_hook,
3664         .release_device         = pnv_pci_release_device,
3665         .window_alignment       = pnv_pci_window_alignment,
3666         .setup_bridge           = pnv_pci_setup_bridge,
3667         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3668         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3669         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3670         .shutdown               = pnv_pci_ioda_shutdown,
3671 };
3672
3673 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3674 {
3675         dev_err_once(&npdev->dev,
3676                         "%s operation unsupported for NVLink devices\n",
3677                         __func__);
3678         return -EPERM;
3679 }
3680
3681 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3682         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3683         .setup_msi_irqs         = pnv_setup_msi_irqs,
3684         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3685         .enable_device_hook     = pnv_pci_enable_device_hook,
3686         .window_alignment       = pnv_pci_window_alignment,
3687         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3688         .dma_set_mask           = pnv_npu_dma_set_mask,
3689         .shutdown               = pnv_pci_ioda_shutdown,
3690         .disable_device         = pnv_npu_disable_device,
3691 };
3692
3693 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3694         .enable_device_hook     = pnv_pci_enable_device_hook,
3695         .window_alignment       = pnv_pci_window_alignment,
3696         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3697         .shutdown               = pnv_pci_ioda_shutdown,
3698 };
3699
3700 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3701                                          u64 hub_id, int ioda_type)
3702 {
3703         struct pci_controller *hose;
3704         struct pnv_phb *phb;
3705         unsigned long size, m64map_off, m32map_off, pemap_off;
3706         unsigned long iomap_off = 0, dma32map_off = 0;
3707         struct resource r;
3708         const __be64 *prop64;
3709         const __be32 *prop32;
3710         int len;
3711         unsigned int segno;
3712         u64 phb_id;
3713         void *aux;
3714         long rc;
3715
3716         if (!of_device_is_available(np))
3717                 return;
3718
3719         pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3720
3721         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3722         if (!prop64) {
3723                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3724                 return;
3725         }
3726         phb_id = be64_to_cpup(prop64);
3727         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3728
3729         phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
3730
3731         /* Allocate PCI controller */
3732         phb->hose = hose = pcibios_alloc_controller(np);
3733         if (!phb->hose) {
3734                 pr_err("  Can't allocate PCI controller for %pOF\n",
3735                        np);
3736                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3737                 return;
3738         }
3739
3740         spin_lock_init(&phb->lock);
3741         prop32 = of_get_property(np, "bus-range", &len);
3742         if (prop32 && len == 8) {
3743                 hose->first_busno = be32_to_cpu(prop32[0]);
3744                 hose->last_busno = be32_to_cpu(prop32[1]);
3745         } else {
3746                 pr_warn("  Broken <bus-range> on %pOF\n", np);
3747                 hose->first_busno = 0;
3748                 hose->last_busno = 0xff;
3749         }
3750         hose->private_data = phb;
3751         phb->hub_id = hub_id;
3752         phb->opal_id = phb_id;
3753         phb->type = ioda_type;
3754         mutex_init(&phb->ioda.pe_alloc_mutex);
3755
3756         /* Detect specific models for error handling */
3757         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3758                 phb->model = PNV_PHB_MODEL_P7IOC;
3759         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3760                 phb->model = PNV_PHB_MODEL_PHB3;
3761         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3762                 phb->model = PNV_PHB_MODEL_NPU;
3763         else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3764                 phb->model = PNV_PHB_MODEL_NPU2;
3765         else
3766                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3767
3768         /* Initialize diagnostic data buffer */
3769         prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3770         if (prop32)
3771                 phb->diag_data_size = be32_to_cpup(prop32);
3772         else
3773                 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3774
3775         phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
3776
3777         /* Parse 32-bit and IO ranges (if any) */
3778         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3779
3780         /* Get registers */
3781         if (!of_address_to_resource(np, 0, &r)) {
3782                 phb->regs_phys = r.start;
3783                 phb->regs = ioremap(r.start, resource_size(&r));
3784                 if (phb->regs == NULL)
3785                         pr_err("  Failed to map registers !\n");
3786         }
3787
3788         /* Initialize more IODA stuff */
3789         phb->ioda.total_pe_num = 1;
3790         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3791         if (prop32)
3792                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3793         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3794         if (prop32)
3795                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3796
3797         /* Invalidate RID to PE# mapping */
3798         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3799                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3800
3801         /* Parse 64-bit MMIO range */
3802         pnv_ioda_parse_m64_window(phb);
3803
3804         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3805         /* FW Has already off top 64k of M32 space (MSI space) */
3806         phb->ioda.m32_size += 0x10000;
3807
3808         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3809         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3810         phb->ioda.io_size = hose->pci_io_size;
3811         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3812         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3813
3814         /* Calculate how many 32-bit TCE segments we have */
3815         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3816                                 PNV_IODA1_DMA32_SEGSIZE;
3817
3818         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3819         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3820                         sizeof(unsigned long));
3821         m64map_off = size;
3822         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3823         m32map_off = size;
3824         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3825         if (phb->type == PNV_PHB_IODA1) {
3826                 iomap_off = size;
3827                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3828                 dma32map_off = size;
3829                 size += phb->ioda.dma32_count *
3830                         sizeof(phb->ioda.dma32_segmap[0]);
3831         }
3832         pemap_off = size;
3833         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3834         aux = memblock_alloc(size, SMP_CACHE_BYTES);
3835         phb->ioda.pe_alloc = aux;
3836         phb->ioda.m64_segmap = aux + m64map_off;
3837         phb->ioda.m32_segmap = aux + m32map_off;
3838         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3839                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3840                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3841         }
3842         if (phb->type == PNV_PHB_IODA1) {
3843                 phb->ioda.io_segmap = aux + iomap_off;
3844                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3845                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3846
3847                 phb->ioda.dma32_segmap = aux + dma32map_off;
3848                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3849                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3850         }
3851         phb->ioda.pe_array = aux + pemap_off;
3852
3853         /*
3854          * Choose PE number for root bus, which shouldn't have
3855          * M64 resources consumed by its child devices. To pick
3856          * the PE number adjacent to the reserved one if possible.
3857          */
3858         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3859         if (phb->ioda.reserved_pe_idx == 0) {
3860                 phb->ioda.root_pe_idx = 1;
3861                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3862         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3863                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3864                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3865         } else {
3866                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3867         }
3868
3869         INIT_LIST_HEAD(&phb->ioda.pe_list);
3870         mutex_init(&phb->ioda.pe_list_mutex);
3871
3872         /* Calculate how many 32-bit TCE segments we have */
3873         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3874                                 PNV_IODA1_DMA32_SEGSIZE;
3875
3876 #if 0 /* We should really do that ... */
3877         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3878                                          window_type,
3879                                          window_num,
3880                                          starting_real_address,
3881                                          starting_pci_address,
3882                                          segment_size);
3883 #endif
3884
3885         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3886                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3887                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3888         if (phb->ioda.m64_size)
3889                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3890                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3891         if (phb->ioda.io_size)
3892                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3893                         phb->ioda.io_size, phb->ioda.io_segsize);
3894
3895
3896         phb->hose->ops = &pnv_pci_ops;
3897         phb->get_pe_state = pnv_ioda_get_pe_state;
3898         phb->freeze_pe = pnv_ioda_freeze_pe;
3899         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3900
3901         /* Setup MSI support */
3902         pnv_pci_init_ioda_msis(phb);
3903
3904         /*
3905          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3906          * to let the PCI core do resource assignment. It's supposed
3907          * that the PCI core will do correct I/O and MMIO alignment
3908          * for the P2P bridge bars so that each PCI bus (excluding
3909          * the child P2P bridges) can form individual PE.
3910          */
3911         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3912
3913         switch (phb->type) {
3914         case PNV_PHB_NPU_NVLINK:
3915                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3916                 break;
3917         case PNV_PHB_NPU_OCAPI:
3918                 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3919                 break;
3920         default:
3921                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3922                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3923         }
3924
3925         ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3926
3927 #ifdef CONFIG_PCI_IOV
3928         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3929         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3930         ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3931         ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3932 #endif
3933
3934         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3935
3936         /* Reset IODA tables to a clean state */
3937         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3938         if (rc)
3939                 pr_warn("  OPAL Error %ld performing IODA table reset !\n", rc);
3940
3941         /*
3942          * If we're running in kdump kernel, the previous kernel never
3943          * shutdown PCI devices correctly. We already got IODA table
3944          * cleaned out. So we have to issue PHB reset to stop all PCI
3945          * transactions from previous kernel. The ppc_pci_reset_phbs
3946          * kernel parameter will force this reset too.
3947          */
3948         if (is_kdump_kernel() || pci_reset_phbs) {
3949                 pr_info("  Issue PHB reset ...\n");
3950                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3951                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3952         }
3953
3954         /* Remove M64 resource if we can't configure it successfully */
3955         if (!phb->init_m64 || phb->init_m64(phb))
3956                 hose->mem_resources[1].flags = 0;
3957 }
3958
3959 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3960 {
3961         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3962 }
3963
3964 void __init pnv_pci_init_npu_phb(struct device_node *np)
3965 {
3966         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
3967 }
3968
3969 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3970 {
3971         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
3972 }
3973
3974 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3975 {
3976         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3977         struct pnv_phb *phb = hose->private_data;
3978
3979         if (!machine_is(powernv))
3980                 return;
3981
3982         if (phb->type == PNV_PHB_NPU_OCAPI)
3983                 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
3984 }
3985 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
3986
3987 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3988 {
3989         struct device_node *phbn;
3990         const __be64 *prop64;
3991         u64 hub_id;
3992
3993         pr_info("Probing IODA IO-Hub %pOF\n", np);
3994
3995         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3996         if (!prop64) {
3997                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3998                 return;
3999         }
4000         hub_id = be64_to_cpup(prop64);
4001         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
4002
4003         /* Count child PHBs */
4004         for_each_child_of_node(np, phbn) {
4005                 /* Look for IODA1 PHBs */
4006                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
4007                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
4008         }
4009 }