arch/powerpc/platforms/cell/spufs/switch.c

   1 /*
   2  * spu_switch.c
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  *
   6  * Author: Mark Nutter <mnutter@us.ibm.com>
   7  *
   8  * Host-side part of SPU context switch sequence outlined in
   9  * Synergistic Processor Element, Book IV.
  10  *
  11  * A fully premptive switch of an SPE is very expensive in terms
  12  * of time and system resources.  SPE Book IV indicates that SPE
  13  * allocation should follow a "serially reusable device" model,
  14  * in which the SPE is assigned a task until it completes.  When
  15  * this is not possible, this sequence may be used to premptively
  16  * save, and then later (optionally) restore the context of a
  17  * program executing on an SPE.
  18  *
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2, or (at your option)
  23  * any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/errno.h>
  37 #include <linux/sched.h>
  38 #include <linux/kernel.h>
  39 #include <linux/mm.h>
  40 #include <linux/vmalloc.h>
  41 #include <linux/smp.h>
  42 #include <linux/stddef.h>
  43 #include <linux/unistd.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/spu.h>
  47 #include <asm/spu_priv1.h>
  48 #include <asm/spu_csa.h>
  49 #include <asm/mmu_context.h>
  50
  51 #include "spu_save_dump.h"
  52 #include "spu_restore_dump.h"
  53
  54 #if 0
  55 #define POLL_WHILE_TRUE(_c) {                           \
  56     do {                                                \
  57     } while (_c);                                       \
  58   }
  59 #else
  60 #define RELAX_SPIN_COUNT                                1000
  61 #define POLL_WHILE_TRUE(_c) {                           \
  62     do {                                                \
  63         int _i;                                         \
  64         for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
  65             cpu_relax();                                \
  66         }                                               \
  67         if (unlikely(_c)) yield();                      \
  68         else break;                                     \
  69     } while (_c);                                       \
  70   }
  71 #endif                          /* debug */
  72
  73 #define POLL_WHILE_FALSE(_c)    POLL_WHILE_TRUE(!(_c))
  74
  75 static inline void acquire_spu_lock(struct spu *spu)
  76 {
  77         /* Save, Step 1:
  78          * Restore, Step 1:
  79          *    Acquire SPU-specific mutual exclusion lock.
  80          *    TBD.
  81          */
  82 }
  83
  84 static inline void release_spu_lock(struct spu *spu)
  85 {
  86         /* Restore, Step 76:
  87          *    Release SPU-specific mutual exclusion lock.
  88          *    TBD.
  89          */
  90 }
  91
  92 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
  93 {
  94         struct spu_problem __iomem *prob = spu->problem;
  95         u32 isolate_state;
  96
  97         /* Save, Step 2:
  98          * Save, Step 6:
  99          *     If SPU_Status[E,L,IS] any field is '1', this
 100          *     SPU is in isolate state and cannot be context
 101          *     saved at this time.
 102          */
 103         isolate_state = SPU_STATUS_ISOLATED_STATE |
 104             SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
 105         return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
 106 }
 107
 108 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
 109 {
 110         /* Save, Step 3:
 111          * Restore, Step 2:
 112          *     Save INT_Mask_class0 in CSA.
 113          *     Write INT_MASK_class0 with value of 0.
 114          *     Save INT_Mask_class1 in CSA.
 115          *     Write INT_MASK_class1 with value of 0.
 116          *     Save INT_Mask_class2 in CSA.
 117          *     Write INT_MASK_class2 with value of 0.
 118          */
 119         spin_lock_irq(&spu->register_lock);
 120         if (csa) {
 121                 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
 122                 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
 123                 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
 124         }
 125         spu_int_mask_set(spu, 0, 0ul);
 126         spu_int_mask_set(spu, 1, 0ul);
 127         spu_int_mask_set(spu, 2, 0ul);
 128         eieio();
 129         spin_unlock_irq(&spu->register_lock);
 130 }
 131
 132 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
 133 {
 134         /* Save, Step 4:
 135          * Restore, Step 25.
 136          *    Set a software watchdog timer, which specifies the
 137          *    maximum allowable time for a context save sequence.
 138          *
 139          *    For present, this implementation will not set a global
 140          *    watchdog timer, as virtualization & variable system load
 141          *    may cause unpredictable execution times.
 142          */
 143 }
 144
 145 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
 146 {
 147         /* Save, Step 5:
 148          * Restore, Step 3:
 149          *     Inhibit user-space access (if provided) to this
 150          *     SPU by unmapping the virtual pages assigned to
 151          *     the SPU memory-mapped I/O (MMIO) for problem
 152          *     state. TBD.
 153          */
 154 }
 155
 156 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
 157 {
 158         /* Save, Step 7:
 159          * Restore, Step 5:
 160          *     Set a software context switch pending flag.
 161          */
 162         set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 163         mb();
 164 }
 165
 166 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
 167 {
 168         struct spu_priv2 __iomem *priv2 = spu->priv2;
 169
 170         /* Save, Step 8:
 171          *     Suspend DMA and save MFC_CNTL.
 172          */
 173         switch (in_be64(&priv2->mfc_control_RW) &
 174                MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
 175         case MFC_CNTL_SUSPEND_IN_PROGRESS:
 176                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 177                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 178                                  MFC_CNTL_SUSPEND_COMPLETE);
 179                 /* fall through */
 180         case MFC_CNTL_SUSPEND_COMPLETE:
 181                 if (csa) {
 182                         csa->priv2.mfc_control_RW =
 183                                 in_be64(&priv2->mfc_control_RW) |
 184                                 MFC_CNTL_SUSPEND_DMA_QUEUE;
 185                 }
 186                 break;
 187         case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
 188                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
 189                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 190                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 191                                  MFC_CNTL_SUSPEND_COMPLETE);
 192                 if (csa) {
 193                         csa->priv2.mfc_control_RW =
 194                                 in_be64(&priv2->mfc_control_RW) &
 195                                 ~MFC_CNTL_SUSPEND_DMA_QUEUE;
 196                 }
 197                 break;
 198         }
 199 }
 200
 201 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
 202 {
 203         struct spu_problem __iomem *prob = spu->problem;
 204
 205         /* Save, Step 9:
 206          *     Save SPU_Runcntl in the CSA.  This value contains
 207          *     the "Application Desired State".
 208          */
 209         csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
 210 }
 211
 212 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
 213 {
 214         /* Save, Step 10:
 215          *     Save MFC_SR1 in the CSA.
 216          */
 217         csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
 218 }
 219
 220 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
 221 {
 222         struct spu_problem __iomem *prob = spu->problem;
 223
 224         /* Save, Step 11:
 225          *     Read SPU_Status[R], and save to CSA.
 226          */
 227         if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
 228                 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 229         } else {
 230                 u32 stopped;
 231
 232                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
 233                 eieio();
 234                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
 235                                 SPU_STATUS_RUNNING);
 236                 stopped =
 237                     SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
 238                     SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
 239                 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
 240                         csa->prob.spu_status_R = SPU_STATUS_RUNNING;
 241                 else
 242                         csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 243         }
 244 }
 245
 246 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
 247 {
 248         struct spu_priv2 __iomem *priv2 = spu->priv2;
 249
 250         /* Save, Step 12:
 251          *     Read MFC_CNTL[Ds].  Update saved copy of
 252          *     CSA.MFC_CNTL[Ds].
 253          */
 254         if (in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING) {
 255                 csa->priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
 256                 csa->suspend_time = get_cycles();
 257                 out_be64(&priv2->spu_chnlcntptr_RW, 7ULL);
 258                 eieio();
 259                 csa->spu_chnldata_RW[7] = in_be64(&priv2->spu_chnldata_RW);
 260                 eieio();
 261         } else {
 262                 csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
 263         }
 264 }
 265
 266 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
 267 {
 268         struct spu_priv2 __iomem *priv2 = spu->priv2;
 269
 270         /* Save, Step 13:
 271          *     Write MFC_CNTL[Dh] set to a '1' to halt
 272          *     the decrementer.
 273          */
 274         out_be64(&priv2->mfc_control_RW, MFC_CNTL_DECREMENTER_HALTED);
 275         eieio();
 276 }
 277
 278 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
 279 {
 280         /* Save, Step 14:
 281          *    Read PPE Timebase High and Timebase low registers
 282          *    and save in CSA.  TBD.
 283          */
 284         csa->suspend_time = get_cycles();
 285 }
 286
 287 static inline void remove_other_spu_access(struct spu_state *csa,
 288                                            struct spu *spu)
 289 {
 290         /* Save, Step 15:
 291          *     Remove other SPU access to this SPU by unmapping
 292          *     this SPU's pages from their address space.  TBD.
 293          */
 294 }
 295
 296 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
 297 {
 298         struct spu_problem __iomem *prob = spu->problem;
 299
 300         /* Save, Step 16:
 301          * Restore, Step 11.
 302          *     Write SPU_MSSync register. Poll SPU_MSSync[P]
 303          *     for a value of 0.
 304          */
 305         out_be64(&prob->spc_mssync_RW, 1UL);
 306         POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
 307 }
 308
 309 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
 310 {
 311         /* Save, Step 17:
 312          * Restore, Step 12.
 313          * Restore, Step 48.
 314          *     Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
 315          *     Then issue a PPE sync instruction.
 316          */
 317         spu_tlb_invalidate(spu);
 318         mb();
 319 }
 320
 321 static inline void handle_pending_interrupts(struct spu_state *csa,
 322                                              struct spu *spu)
 323 {
 324         /* Save, Step 18:
 325          *     Handle any pending interrupts from this SPU
 326          *     here.  This is OS or hypervisor specific.  One
 327          *     option is to re-enable interrupts to handle any
 328          *     pending interrupts, with the interrupt handlers
 329          *     recognizing the software Context Switch Pending
 330          *     flag, to ensure the SPU execution or MFC command
 331          *     queue is not restarted.  TBD.
 332          */
 333 }
 334
 335 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
 336 {
 337         struct spu_priv2 __iomem *priv2 = spu->priv2;
 338         int i;
 339
 340         /* Save, Step 19:
 341          *     If MFC_Cntl[Se]=0 then save
 342          *     MFC command queues.
 343          */
 344         if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
 345                 for (i = 0; i < 8; i++) {
 346                         csa->priv2.puq[i].mfc_cq_data0_RW =
 347                             in_be64(&priv2->puq[i].mfc_cq_data0_RW);
 348                         csa->priv2.puq[i].mfc_cq_data1_RW =
 349                             in_be64(&priv2->puq[i].mfc_cq_data1_RW);
 350                         csa->priv2.puq[i].mfc_cq_data2_RW =
 351                             in_be64(&priv2->puq[i].mfc_cq_data2_RW);
 352                         csa->priv2.puq[i].mfc_cq_data3_RW =
 353                             in_be64(&priv2->puq[i].mfc_cq_data3_RW);
 354                 }
 355                 for (i = 0; i < 16; i++) {
 356                         csa->priv2.spuq[i].mfc_cq_data0_RW =
 357                             in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
 358                         csa->priv2.spuq[i].mfc_cq_data1_RW =
 359                             in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
 360                         csa->priv2.spuq[i].mfc_cq_data2_RW =
 361                             in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
 362                         csa->priv2.spuq[i].mfc_cq_data3_RW =
 363                             in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
 364                 }
 365         }
 366 }
 367
 368 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
 369 {
 370         struct spu_problem __iomem *prob = spu->problem;
 371
 372         /* Save, Step 20:
 373          *     Save the PPU_QueryMask register
 374          *     in the CSA.
 375          */
 376         csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
 377 }
 378
 379 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
 380 {
 381         struct spu_problem __iomem *prob = spu->problem;
 382
 383         /* Save, Step 21:
 384          *     Save the PPU_QueryType register
 385          *     in the CSA.
 386          */
 387         csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
 388 }
 389
 390 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
 391 {
 392         struct spu_priv2 __iomem *priv2 = spu->priv2;
 393
 394         /* Save, Step 22:
 395          *     Save the MFC_CSR_TSQ register
 396          *     in the LSCSA.
 397          */
 398         csa->priv2.spu_tag_status_query_RW =
 399             in_be64(&priv2->spu_tag_status_query_RW);
 400 }
 401
 402 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
 403 {
 404         struct spu_priv2 __iomem *priv2 = spu->priv2;
 405
 406         /* Save, Step 23:
 407          *     Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
 408          *     registers in the CSA.
 409          */
 410         csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
 411         csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
 412 }
 413
 414 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
 415 {
 416         struct spu_priv2 __iomem *priv2 = spu->priv2;
 417
 418         /* Save, Step 24:
 419          *     Save the MFC_CSR_ATO register in
 420          *     the CSA.
 421          */
 422         csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
 423 }
 424
 425 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 426 {
 427         /* Save, Step 25:
 428          *     Save the MFC_TCLASS_ID register in
 429          *     the CSA.
 430          */
 431         csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
 432 }
 433
 434 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 435 {
 436         /* Save, Step 26:
 437          * Restore, Step 23.
 438          *     Write the MFC_TCLASS_ID register with
 439          *     the value 0x10000000.
 440          */
 441         spu_mfc_tclass_id_set(spu, 0x10000000);
 442         eieio();
 443 }
 444
 445 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
 446 {
 447         struct spu_priv2 __iomem *priv2 = spu->priv2;
 448
 449         /* Save, Step 27:
 450          * Restore, Step 14.
 451          *     Write MFC_CNTL[Pc]=1 (purge queue).
 452          */
 453         out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST);
 454         eieio();
 455 }
 456
 457 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
 458 {
 459         struct spu_priv2 __iomem *priv2 = spu->priv2;
 460
 461         /* Save, Step 28:
 462          *     Poll MFC_CNTL[Ps] until value '11' is read
 463          *     (purge complete).
 464          */
 465         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 466                          MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
 467                          MFC_CNTL_PURGE_DMA_COMPLETE);
 468 }
 469
 470 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
 471 {
 472         /* Save, Step 30:
 473          * Restore, Step 18:
 474          *     Write MFC_SR1 with MFC_SR1[D=0,S=1] and
 475          *     MFC_SR1[TL,R,Pr,T] set correctly for the
 476          *     OS specific environment.
 477          *
 478          *     Implementation note: The SPU-side code
 479          *     for save/restore is privileged, so the
 480          *     MFC_SR1[Pr] bit is not set.
 481          *
 482          */
 483         spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
 484                               MFC_STATE1_RELOCATE_MASK |
 485                               MFC_STATE1_BUS_TLBIE_MASK));
 486 }
 487
 488 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
 489 {
 490         struct spu_problem __iomem *prob = spu->problem;
 491
 492         /* Save, Step 31:
 493          *     Save SPU_NPC in the CSA.
 494          */
 495         csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
 496 }
 497
 498 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
 499 {
 500         struct spu_priv2 __iomem *priv2 = spu->priv2;
 501
 502         /* Save, Step 32:
 503          *     Save SPU_PrivCntl in the CSA.
 504          */
 505         csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
 506 }
 507
 508 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
 509 {
 510         struct spu_priv2 __iomem *priv2 = spu->priv2;
 511
 512         /* Save, Step 33:
 513          * Restore, Step 16:
 514          *     Write SPU_PrivCntl[S,Le,A] fields reset to 0.
 515          */
 516         out_be64(&priv2->spu_privcntl_RW, 0UL);
 517         eieio();
 518 }
 519
 520 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
 521 {
 522         struct spu_priv2 __iomem *priv2 = spu->priv2;
 523
 524         /* Save, Step 34:
 525          *     Save SPU_LSLR in the CSA.
 526          */
 527         csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
 528 }
 529
 530 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
 531 {
 532         struct spu_priv2 __iomem *priv2 = spu->priv2;
 533
 534         /* Save, Step 35:
 535          * Restore, Step 17.
 536          *     Reset SPU_LSLR.
 537          */
 538         out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
 539         eieio();
 540 }
 541
 542 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
 543 {
 544         struct spu_priv2 __iomem *priv2 = spu->priv2;
 545
 546         /* Save, Step 36:
 547          *     Save SPU_Cfg in the CSA.
 548          */
 549         csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
 550 }
 551
 552 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
 553 {
 554         /* Save, Step 37:
 555          *     Save PM_Trace_Tag_Wait_Mask in the CSA.
 556          *     Not performed by this implementation.
 557          */
 558 }
 559
 560 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
 561 {
 562         /* Save, Step 38:
 563          *     Save RA_GROUP_ID register and the
 564          *     RA_ENABLE reigster in the CSA.
 565          */
 566         csa->priv1.resource_allocation_groupID_RW =
 567                 spu_resource_allocation_groupID_get(spu);
 568         csa->priv1.resource_allocation_enable_RW =
 569                 spu_resource_allocation_enable_get(spu);
 570 }
 571
 572 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
 573 {
 574         struct spu_problem __iomem *prob = spu->problem;
 575
 576         /* Save, Step 39:
 577          *     Save MB_Stat register in the CSA.
 578          */
 579         csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
 580 }
 581
 582 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
 583 {
 584         struct spu_problem __iomem *prob = spu->problem;
 585
 586         /* Save, Step 40:
 587          *     Save the PPU_MB register in the CSA.
 588          */
 589         csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
 590 }
 591
 592 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
 593 {
 594         struct spu_priv2 __iomem *priv2 = spu->priv2;
 595
 596         /* Save, Step 41:
 597          *     Save the PPUINT_MB register in the CSA.
 598          */
 599         csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
 600 }
 601
 602 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
 603 {
 604         struct spu_priv2 __iomem *priv2 = spu->priv2;
 605         u64 idx, ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
 606         int i;
 607
 608         /* Save, Step 42:
 609          */
 610
 611         /* Save CH 1, without channel count */
 612         out_be64(&priv2->spu_chnlcntptr_RW, 1);
 613         csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
 614
 615         /* Save the following CH: [0,3,4,24,25,27] */
 616         for (i = 0; i < 7; i++) {
 617                 idx = ch_indices[i];
 618                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 619                 eieio();
 620                 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
 621                 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
 622                 out_be64(&priv2->spu_chnldata_RW, 0UL);
 623                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 624                 eieio();
 625         }
 626 }
 627
 628 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
 629 {
 630         struct spu_priv2 __iomem *priv2 = spu->priv2;
 631         int i;
 632
 633         /* Save, Step 43:
 634          *     Save SPU Read Mailbox Channel.
 635          */
 636         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
 637         eieio();
 638         csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
 639         for (i = 0; i < 4; i++) {
 640                 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
 641         }
 642         out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 643         eieio();
 644 }
 645
 646 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
 647 {
 648         struct spu_priv2 __iomem *priv2 = spu->priv2;
 649
 650         /* Save, Step 44:
 651          *     Save MFC_CMD Channel.
 652          */
 653         out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
 654         eieio();
 655         csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
 656         eieio();
 657 }
 658
 659 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
 660 {
 661         struct spu_priv2 __iomem *priv2 = spu->priv2;
 662         u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
 663         u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
 664         u64 idx;
 665         int i;
 666
 667         /* Save, Step 45:
 668          *     Reset the following CH: [21, 23, 28, 30]
 669          */
 670         for (i = 0; i < 4; i++) {
 671                 idx = ch_indices[i];
 672                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 673                 eieio();
 674                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
 675                 eieio();
 676         }
 677 }
 678
 679 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
 680 {
 681         struct spu_priv2 __iomem *priv2 = spu->priv2;
 682
 683         /* Save, Step 46:
 684          * Restore, Step 25.
 685          *     Write MFC_CNTL[Sc]=0 (resume queue processing).
 686          */
 687         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
 688 }
 689
 690 static inline void get_kernel_slb(u64 ea, u64 slb[2])
 691 {
 692         u64 llp;
 693
 694         if (REGION_ID(ea) == KERNEL_REGION_ID)
 695                 llp = mmu_psize_defs[mmu_linear_psize].sllp;
 696         else
 697                 llp = mmu_psize_defs[mmu_virtual_psize].sllp;
 698         slb[0] = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
 699                 SLB_VSID_KERNEL | llp;
 700         slb[1] = (ea & ESID_MASK) | SLB_ESID_V;
 701 }
 702
 703 static inline void load_mfc_slb(struct spu *spu, u64 slb[2], int slbe)
 704 {
 705         struct spu_priv2 __iomem *priv2 = spu->priv2;
 706
 707         out_be64(&priv2->slb_index_W, slbe);
 708         eieio();
 709         out_be64(&priv2->slb_vsid_RW, slb[0]);
 710         out_be64(&priv2->slb_esid_RW, slb[1]);
 711         eieio();
 712 }
 713
 714 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu)
 715 {
 716         u64 code_slb[2];
 717         u64 lscsa_slb[2];
 718
 719         /* Save, Step 47:
 720          * Restore, Step 30.
 721          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
 722          *     register, then initialize SLB_VSID and SLB_ESID
 723          *     to provide access to SPU context save code and
 724          *     LSCSA.
 725          *
 726          *     This implementation places both the context
 727          *     switch code and LSCSA in kernel address space.
 728          *
 729          *     Further this implementation assumes that the
 730          *     MFC_SR1[R]=1 (in other words, assume that
 731          *     translation is desired by OS environment).
 732          */
 733         spu_invalidate_slbs(spu);
 734         get_kernel_slb((unsigned long)&spu_save_code[0], code_slb);
 735         get_kernel_slb((unsigned long)csa->lscsa, lscsa_slb);
 736         load_mfc_slb(spu, code_slb, 0);
 737         if ((lscsa_slb[0] != code_slb[0]) || (lscsa_slb[1] != code_slb[1]))
 738                 load_mfc_slb(spu, lscsa_slb, 1);
 739 }
 740
 741 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
 742 {
 743         /* Save, Step 48:
 744          * Restore, Step 23.
 745          *     Change the software context switch pending flag
 746          *     to context switch active.
 747          */
 748         set_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
 749         clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 750         mb();
 751 }
 752
 753 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
 754 {
 755         unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
 756             CLASS1_ENABLE_STORAGE_FAULT_INTR;
 757
 758         /* Save, Step 49:
 759          * Restore, Step 22:
 760          *     Reset and then enable interrupts, as
 761          *     needed by OS.
 762          *
 763          *     This implementation enables only class1
 764          *     (translation) interrupts.
 765          */
 766         spin_lock_irq(&spu->register_lock);
 767         spu_int_stat_clear(spu, 0, ~0ul);
 768         spu_int_stat_clear(spu, 1, ~0ul);
 769         spu_int_stat_clear(spu, 2, ~0ul);
 770         spu_int_mask_set(spu, 0, 0ul);
 771         spu_int_mask_set(spu, 1, class1_mask);
 772         spu_int_mask_set(spu, 2, 0ul);
 773         spin_unlock_irq(&spu->register_lock);
 774 }
 775
 776 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
 777                                unsigned int ls_offset, unsigned int size,
 778                                unsigned int tag, unsigned int rclass,
 779                                unsigned int cmd)
 780 {
 781         struct spu_problem __iomem *prob = spu->problem;
 782         union mfc_tag_size_class_cmd command;
 783         unsigned int transfer_size;
 784         volatile unsigned int status = 0x0;
 785
 786         while (size > 0) {
 787                 transfer_size =
 788                     (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
 789                 command.u.mfc_size = transfer_size;
 790                 command.u.mfc_tag = tag;
 791                 command.u.mfc_rclassid = rclass;
 792                 command.u.mfc_cmd = cmd;
 793                 do {
 794                         out_be32(&prob->mfc_lsa_W, ls_offset);
 795                         out_be64(&prob->mfc_ea_W, ea);
 796                         out_be64(&prob->mfc_union_W.all64, command.all64);
 797                         status =
 798                             in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
 799                         if (unlikely(status & 0x2)) {
 800                                 cpu_relax();
 801                         }
 802                 } while (status & 0x3);
 803                 size -= transfer_size;
 804                 ea += transfer_size;
 805                 ls_offset += transfer_size;
 806         }
 807         return 0;
 808 }
 809
 810 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
 811 {
 812         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
 813         unsigned int ls_offset = 0x0;
 814         unsigned int size = 16384;
 815         unsigned int tag = 0;
 816         unsigned int rclass = 0;
 817         unsigned int cmd = MFC_PUT_CMD;
 818
 819         /* Save, Step 50:
 820          *     Issue a DMA command to copy the first 16K bytes
 821          *     of local storage to the CSA.
 822          */
 823         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 824 }
 825
 826 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
 827 {
 828         struct spu_problem __iomem *prob = spu->problem;
 829
 830         /* Save, Step 51:
 831          * Restore, Step 31.
 832          *     Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
 833          *     point address of context save code in local
 834          *     storage.
 835          *
 836          *     This implementation uses SPU-side save/restore
 837          *     programs with entry points at LSA of 0.
 838          */
 839         out_be32(&prob->spu_npc_RW, 0);
 840         eieio();
 841 }
 842
 843 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
 844 {
 845         struct spu_problem __iomem *prob = spu->problem;
 846         union {
 847                 u64 ull;
 848                 u32 ui[2];
 849         } addr64;
 850
 851         /* Save, Step 52:
 852          * Restore, Step 32:
 853          *    Write SPU_Sig_Notify_1 register with upper 32-bits
 854          *    of the CSA.LSCSA effective address.
 855          */
 856         addr64.ull = (u64) csa->lscsa;
 857         out_be32(&prob->signal_notify1, addr64.ui[0]);
 858         eieio();
 859 }
 860
 861 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
 862 {
 863         struct spu_problem __iomem *prob = spu->problem;
 864         union {
 865                 u64 ull;
 866                 u32 ui[2];
 867         } addr64;
 868
 869         /* Save, Step 53:
 870          * Restore, Step 33:
 871          *    Write SPU_Sig_Notify_2 register with lower 32-bits
 872          *    of the CSA.LSCSA effective address.
 873          */
 874         addr64.ull = (u64) csa->lscsa;
 875         out_be32(&prob->signal_notify2, addr64.ui[1]);
 876         eieio();
 877 }
 878
 879 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
 880 {
 881         unsigned long addr = (unsigned long)&spu_save_code[0];
 882         unsigned int ls_offset = 0x0;
 883         unsigned int size = sizeof(spu_save_code);
 884         unsigned int tag = 0;
 885         unsigned int rclass = 0;
 886         unsigned int cmd = MFC_GETFS_CMD;
 887
 888         /* Save, Step 54:
 889          *     Issue a DMA command to copy context save code
 890          *     to local storage and start SPU.
 891          */
 892         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 893 }
 894
 895 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
 896 {
 897         struct spu_problem __iomem *prob = spu->problem;
 898
 899         /* Save, Step 55:
 900          * Restore, Step 38.
 901          *     Write PPU_QueryMask=1 (enable Tag Group 0)
 902          *     and issue eieio instruction.
 903          */
 904         out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
 905         eieio();
 906 }
 907
 908 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
 909 {
 910         struct spu_problem __iomem *prob = spu->problem;
 911         u32 mask = MFC_TAGID_TO_TAGMASK(0);
 912         unsigned long flags;
 913
 914         /* Save, Step 56:
 915          * Restore, Step 39.
 916          * Restore, Step 39.
 917          * Restore, Step 46.
 918          *     Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
 919          *     or write PPU_QueryType[TS]=01 and wait for Tag Group
 920          *     Complete Interrupt.  Write INT_Stat_Class0 or
 921          *     INT_Stat_Class2 with value of 'handled'.
 922          */
 923         POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
 924
 925         local_irq_save(flags);
 926         spu_int_stat_clear(spu, 0, ~(0ul));
 927         spu_int_stat_clear(spu, 2, ~(0ul));
 928         local_irq_restore(flags);
 929 }
 930
 931 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
 932 {
 933         struct spu_problem __iomem *prob = spu->problem;
 934         unsigned long flags;
 935
 936         /* Save, Step 57:
 937          * Restore, Step 40.
 938          *     Poll until SPU_Status[R]=0 or wait for SPU Class 0
 939          *     or SPU Class 2 interrupt.  Write INT_Stat_class0
 940          *     or INT_Stat_class2 with value of handled.
 941          */
 942         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
 943
 944         local_irq_save(flags);
 945         spu_int_stat_clear(spu, 0, ~(0ul));
 946         spu_int_stat_clear(spu, 2, ~(0ul));
 947         local_irq_restore(flags);
 948 }
 949
 950 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
 951 {
 952         struct spu_problem __iomem *prob = spu->problem;
 953         u32 complete;
 954
 955         /* Save, Step 54:
 956          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
 957          *     context save succeeded, otherwise context save
 958          *     failed.
 959          */
 960         complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
 961                     SPU_STATUS_STOPPED_BY_STOP);
 962         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
 963 }
 964
 965 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
 966 {
 967         /* Restore, Step 4:
 968          *    If required, notify the "using application" that
 969          *    the SPU task has been terminated.  TBD.
 970          */
 971 }
 972
 973 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
 974 {
 975         struct spu_priv2 __iomem *priv2 = spu->priv2;
 976
 977         /* Restore, Step 7:
 978          * Restore, Step 47.
 979          *     Write MFC_Cntl[Dh,Sc]='1','1' to suspend
 980          *     the queue and halt the decrementer.
 981          */
 982         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
 983                  MFC_CNTL_DECREMENTER_HALTED);
 984         eieio();
 985 }
 986
 987 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
 988                                              struct spu *spu)
 989 {
 990         struct spu_priv2 __iomem *priv2 = spu->priv2;
 991
 992         /* Restore, Step 8:
 993          * Restore, Step 47.
 994          *     Poll MFC_CNTL[Ss] until 11 is returned.
 995          */
 996         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 997                          MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 998                          MFC_CNTL_SUSPEND_COMPLETE);
 999 }
1000
1001 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
1002 {
1003         struct spu_problem __iomem *prob = spu->problem;
1004
1005         /* Restore, Step 9:
1006          *    If SPU_Status[R]=1, stop SPU execution
1007          *    and wait for stop to complete.
1008          *
1009          *    Returns       1 if SPU_Status[R]=1 on entry.
1010          *                  0 otherwise
1011          */
1012         if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
1013                 if (in_be32(&prob->spu_status_R) &
1014                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1015                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1016                                         SPU_STATUS_RUNNING);
1017                 }
1018                 if ((in_be32(&prob->spu_status_R) &
1019                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1020                     || (in_be32(&prob->spu_status_R) &
1021                         SPU_STATUS_ISOLATED_STATE)) {
1022                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1023                         eieio();
1024                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1025                                         SPU_STATUS_RUNNING);
1026                         out_be32(&prob->spu_runcntl_RW, 0x2);
1027                         eieio();
1028                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1029                                         SPU_STATUS_RUNNING);
1030                 }
1031                 if (in_be32(&prob->spu_status_R) &
1032                     SPU_STATUS_WAITING_FOR_CHANNEL) {
1033                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1034                         eieio();
1035                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1036                                         SPU_STATUS_RUNNING);
1037                 }
1038                 return 1;
1039         }
1040         return 0;
1041 }
1042
1043 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1044 {
1045         struct spu_problem __iomem *prob = spu->problem;
1046
1047         /* Restore, Step 10:
1048          *    If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1049          *    release SPU from isolate state.
1050          */
1051         if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1052                 if (in_be32(&prob->spu_status_R) &
1053                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1054                         spu_mfc_sr1_set(spu,
1055                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1056                         eieio();
1057                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1058                         eieio();
1059                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1060                                         SPU_STATUS_RUNNING);
1061                 }
1062                 if ((in_be32(&prob->spu_status_R) &
1063                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1064                     || (in_be32(&prob->spu_status_R) &
1065                         SPU_STATUS_ISOLATED_STATE)) {
1066                         spu_mfc_sr1_set(spu,
1067                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1068                         eieio();
1069                         out_be32(&prob->spu_runcntl_RW, 0x2);
1070                         eieio();
1071                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1072                                         SPU_STATUS_RUNNING);
1073                 }
1074         }
1075 }
1076
1077 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1078 {
1079         struct spu_priv2 __iomem *priv2 = spu->priv2;
1080         u64 ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1081         u64 idx;
1082         int i;
1083
1084         /* Restore, Step 20:
1085          */
1086
1087         /* Reset CH 1 */
1088         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1089         out_be64(&priv2->spu_chnldata_RW, 0UL);
1090
1091         /* Reset the following CH: [0,3,4,24,25,27] */
1092         for (i = 0; i < 7; i++) {
1093                 idx = ch_indices[i];
1094                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1095                 eieio();
1096                 out_be64(&priv2->spu_chnldata_RW, 0UL);
1097                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1098                 eieio();
1099         }
1100 }
1101
1102 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1103 {
1104         struct spu_priv2 __iomem *priv2 = spu->priv2;
1105         u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1106         u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1107         u64 idx;
1108         int i;
1109
1110         /* Restore, Step 21:
1111          *     Reset the following CH: [21, 23, 28, 29, 30]
1112          */
1113         for (i = 0; i < 5; i++) {
1114                 idx = ch_indices[i];
1115                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1116                 eieio();
1117                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1118                 eieio();
1119         }
1120 }
1121
1122 static inline void setup_spu_status_part1(struct spu_state *csa,
1123                                           struct spu *spu)
1124 {
1125         u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1126         u32 status_I = SPU_STATUS_INVALID_INSTR;
1127         u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1128         u32 status_S = SPU_STATUS_SINGLE_STEP;
1129         u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1130         u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1131         u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1132         u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1133         u32 status_code;
1134
1135         /* Restore, Step 27:
1136          *     If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1137          *     instruction sequence to the end of the SPU based restore
1138          *     code (after the "context restored" stop and signal) to
1139          *     restore the correct SPU status.
1140          *
1141          *     NOTE: Rather than modifying the SPU executable, we
1142          *     instead add a new 'stopped_status' field to the
1143          *     LSCSA.  The SPU-side restore reads this field and
1144          *     takes the appropriate action when exiting.
1145          */
1146
1147         status_code =
1148             (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1149         if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1150
1151                 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1152                  * by Stop and Signal instruction, followed by 'br -4'.
1153                  *
1154                  */
1155                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1156                 csa->lscsa->stopped_status.slot[1] = status_code;
1157
1158         } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1159
1160                 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1161                  * by Stop and Signal instruction, followed by
1162                  * 'br -4'.
1163                  */
1164                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1165                 csa->lscsa->stopped_status.slot[1] = status_code;
1166
1167         } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1168
1169                 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1170                  * followed by 'br -4'.
1171                  */
1172                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1173                 csa->lscsa->stopped_status.slot[1] = status_code;
1174
1175         } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1176
1177                 /* SPU_Status[S,I]=1 - Illegal instruction followed
1178                  * by 'br -4'.
1179                  */
1180                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1181                 csa->lscsa->stopped_status.slot[1] = status_code;
1182
1183         } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1184
1185                 /* SPU_Status[P]=1 - Stop and Signal instruction
1186                  * followed by 'br -4'.
1187                  */
1188                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1189                 csa->lscsa->stopped_status.slot[1] = status_code;
1190
1191         } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1192
1193                 /* SPU_Status[H]=1 - Halt Conditional, followed
1194                  * by 'br -4'.
1195                  */
1196                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1197
1198         } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1199
1200                 /* SPU_Status[S]=1 - Two nop instructions.
1201                  */
1202                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1203
1204         } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1205
1206                 /* SPU_Status[I]=1 - Illegal instruction followed
1207                  * by 'br -4'.
1208                  */
1209                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1210
1211         }
1212 }
1213
1214 static inline void setup_spu_status_part2(struct spu_state *csa,
1215                                           struct spu *spu)
1216 {
1217         u32 mask;
1218
1219         /* Restore, Step 28:
1220          *     If the CSA.SPU_Status[I,S,H,P,R]=0 then
1221          *     add a 'br *' instruction to the end of
1222          *     the SPU based restore code.
1223          *
1224          *     NOTE: Rather than modifying the SPU executable, we
1225          *     instead add a new 'stopped_status' field to the
1226          *     LSCSA.  The SPU-side restore reads this field and
1227          *     takes the appropriate action when exiting.
1228          */
1229         mask = SPU_STATUS_INVALID_INSTR |
1230             SPU_STATUS_SINGLE_STEP |
1231             SPU_STATUS_STOPPED_BY_HALT |
1232             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1233         if (!(csa->prob.spu_status_R & mask)) {
1234                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1235         }
1236 }
1237
1238 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1239 {
1240         /* Restore, Step 29:
1241          *     Restore RA_GROUP_ID register and the
1242          *     RA_ENABLE reigster from the CSA.
1243          */
1244         spu_resource_allocation_groupID_set(spu,
1245                         csa->priv1.resource_allocation_groupID_RW);
1246         spu_resource_allocation_enable_set(spu,
1247                         csa->priv1.resource_allocation_enable_RW);
1248 }
1249
1250 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1251 {
1252         unsigned long addr = (unsigned long)&spu_restore_code[0];
1253         unsigned int ls_offset = 0x0;
1254         unsigned int size = sizeof(spu_restore_code);
1255         unsigned int tag = 0;
1256         unsigned int rclass = 0;
1257         unsigned int cmd = MFC_GETFS_CMD;
1258
1259         /* Restore, Step 37:
1260          *     Issue MFC DMA command to copy context
1261          *     restore code to local storage.
1262          */
1263         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1264 }
1265
1266 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1267 {
1268         /* Restore, Step 34:
1269          *     If CSA.MFC_CNTL[Ds]=1 (decrementer was
1270          *     running) then adjust decrementer, set
1271          *     decrementer running status in LSCSA,
1272          *     and set decrementer "wrapped" status
1273          *     in LSCSA.
1274          */
1275         if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1276                 cycles_t resume_time = get_cycles();
1277                 cycles_t delta_time = resume_time - csa->suspend_time;
1278
1279                 csa->lscsa->decr.slot[0] -= delta_time;
1280         }
1281 }
1282
1283 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1284 {
1285         /* Restore, Step 35:
1286          *     Copy the CSA.PU_MB data into the LSCSA.
1287          */
1288         csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1289 }
1290
1291 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1292 {
1293         /* Restore, Step 36:
1294          *     Copy the CSA.PUINT_MB data into the LSCSA.
1295          */
1296         csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1297 }
1298
1299 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1300 {
1301         struct spu_problem __iomem *prob = spu->problem;
1302         u32 complete;
1303
1304         /* Restore, Step 40:
1305          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1306          *     context restore succeeded, otherwise context restore
1307          *     failed.
1308          */
1309         complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1310                     SPU_STATUS_STOPPED_BY_STOP);
1311         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1312 }
1313
1314 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1315 {
1316         struct spu_priv2 __iomem *priv2 = spu->priv2;
1317
1318         /* Restore, Step 41:
1319          *     Restore SPU_PrivCntl from the CSA.
1320          */
1321         out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1322         eieio();
1323 }
1324
1325 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1326 {
1327         struct spu_problem __iomem *prob = spu->problem;
1328         u32 mask;
1329
1330         /* Restore, Step 42:
1331          *     If any CSA.SPU_Status[I,S,H,P]=1, then
1332          *     restore the error or single step state.
1333          */
1334         mask = SPU_STATUS_INVALID_INSTR |
1335             SPU_STATUS_SINGLE_STEP |
1336             SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1337         if (csa->prob.spu_status_R & mask) {
1338                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1339                 eieio();
1340                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1341                                 SPU_STATUS_RUNNING);
1342         }
1343 }
1344
1345 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1346 {
1347         struct spu_problem __iomem *prob = spu->problem;
1348         u32 mask;
1349
1350         /* Restore, Step 43:
1351          *     If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1352          *     SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1353          *     then write '00' to SPU_RunCntl[R0R1] and wait
1354          *     for SPU_Status[R]=0.
1355          */
1356         mask = SPU_STATUS_INVALID_INSTR |
1357             SPU_STATUS_SINGLE_STEP |
1358             SPU_STATUS_STOPPED_BY_HALT |
1359             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1360         if (!(csa->prob.spu_status_R & mask)) {
1361                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1362                 eieio();
1363                 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1364                                  SPU_STATUS_RUNNING);
1365                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1366                 eieio();
1367                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1368                                 SPU_STATUS_RUNNING);
1369         }
1370 }
1371
1372 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1373 {
1374         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1375         unsigned int ls_offset = 0x0;
1376         unsigned int size = 16384;
1377         unsigned int tag = 0;
1378         unsigned int rclass = 0;
1379         unsigned int cmd = MFC_GET_CMD;
1380
1381         /* Restore, Step 44:
1382          *     Issue a DMA command to restore the first
1383          *     16kb of local storage from CSA.
1384          */
1385         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1386 }
1387
1388 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1389 {
1390         /* Restore, Step 49:
1391          *     Write INT_MASK_class0 with value of 0.
1392          *     Write INT_MASK_class1 with value of 0.
1393          *     Write INT_MASK_class2 with value of 0.
1394          *     Write INT_STAT_class0 with value of -1.
1395          *     Write INT_STAT_class1 with value of -1.
1396          *     Write INT_STAT_class2 with value of -1.
1397          */
1398         spin_lock_irq(&spu->register_lock);
1399         spu_int_mask_set(spu, 0, 0ul);
1400         spu_int_mask_set(spu, 1, 0ul);
1401         spu_int_mask_set(spu, 2, 0ul);
1402         spu_int_stat_clear(spu, 0, ~0ul);
1403         spu_int_stat_clear(spu, 1, ~0ul);
1404         spu_int_stat_clear(spu, 2, ~0ul);
1405         spin_unlock_irq(&spu->register_lock);
1406 }
1407
1408 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1409 {
1410         struct spu_priv2 __iomem *priv2 = spu->priv2;
1411         int i;
1412
1413         /* Restore, Step 50:
1414          *     If MFC_Cntl[Se]!=0 then restore
1415          *     MFC command queues.
1416          */
1417         if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1418                 for (i = 0; i < 8; i++) {
1419                         out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1420                                  csa->priv2.puq[i].mfc_cq_data0_RW);
1421                         out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1422                                  csa->priv2.puq[i].mfc_cq_data1_RW);
1423                         out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1424                                  csa->priv2.puq[i].mfc_cq_data2_RW);
1425                         out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1426                                  csa->priv2.puq[i].mfc_cq_data3_RW);
1427                 }
1428                 for (i = 0; i < 16; i++) {
1429                         out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1430                                  csa->priv2.spuq[i].mfc_cq_data0_RW);
1431                         out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1432                                  csa->priv2.spuq[i].mfc_cq_data1_RW);
1433                         out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1434                                  csa->priv2.spuq[i].mfc_cq_data2_RW);
1435                         out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1436                                  csa->priv2.spuq[i].mfc_cq_data3_RW);
1437                 }
1438         }
1439         eieio();
1440 }
1441
1442 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1443 {
1444         struct spu_problem __iomem *prob = spu->problem;
1445
1446         /* Restore, Step 51:
1447          *     Restore the PPU_QueryMask register from CSA.
1448          */
1449         out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1450         eieio();
1451 }
1452
1453 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1454 {
1455         struct spu_problem __iomem *prob = spu->problem;
1456
1457         /* Restore, Step 52:
1458          *     Restore the PPU_QueryType register from CSA.
1459          */
1460         out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1461         eieio();
1462 }
1463
1464 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1465 {
1466         struct spu_priv2 __iomem *priv2 = spu->priv2;
1467
1468         /* Restore, Step 53:
1469          *     Restore the MFC_CSR_TSQ register from CSA.
1470          */
1471         out_be64(&priv2->spu_tag_status_query_RW,
1472                  csa->priv2.spu_tag_status_query_RW);
1473         eieio();
1474 }
1475
1476 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1477 {
1478         struct spu_priv2 __iomem *priv2 = spu->priv2;
1479
1480         /* Restore, Step 54:
1481          *     Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1482          *     registers from CSA.
1483          */
1484         out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1485         out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1486         eieio();
1487 }
1488
1489 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1490 {
1491         struct spu_priv2 __iomem *priv2 = spu->priv2;
1492
1493         /* Restore, Step 55:
1494          *     Restore the MFC_CSR_ATO register from CSA.
1495          */
1496         out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1497 }
1498
1499 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1500 {
1501         /* Restore, Step 56:
1502          *     Restore the MFC_TCLASS_ID register from CSA.
1503          */
1504         spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1505         eieio();
1506 }
1507
1508 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1509 {
1510         u64 ch0_cnt, ch0_data;
1511         u64 ch1_data;
1512
1513         /* Restore, Step 57:
1514          *    Set the Lock Line Reservation Lost Event by:
1515          *      1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1516          *      2. If CSA.SPU_Channel_0_Count=0 and
1517          *         CSA.SPU_Wr_Event_Mask[Lr]=1 and
1518          *         CSA.SPU_Event_Status[Lr]=0 then set
1519          *         CSA.SPU_Event_Status_Count=1.
1520          */
1521         ch0_cnt = csa->spu_chnlcnt_RW[0];
1522         ch0_data = csa->spu_chnldata_RW[0];
1523         ch1_data = csa->spu_chnldata_RW[1];
1524         csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1525         if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1526             (ch1_data & MFC_LLR_LOST_EVENT)) {
1527                 csa->spu_chnlcnt_RW[0] = 1;
1528         }
1529 }
1530
1531 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1532 {
1533         /* Restore, Step 58:
1534          *     If the status of the CSA software decrementer
1535          *     "wrapped" flag is set, OR in a '1' to
1536          *     CSA.SPU_Event_Status[Tm].
1537          */
1538         if (csa->lscsa->decr_status.slot[0] == 1) {
1539                 csa->spu_chnldata_RW[0] |= 0x20;
1540         }
1541         if ((csa->lscsa->decr_status.slot[0] == 1) &&
1542             (csa->spu_chnlcnt_RW[0] == 0 &&
1543              ((csa->spu_chnldata_RW[2] & 0x20) == 0x0) &&
1544              ((csa->spu_chnldata_RW[0] & 0x20) != 0x1))) {
1545                 csa->spu_chnlcnt_RW[0] = 1;
1546         }
1547 }
1548
1549 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1550 {
1551         struct spu_priv2 __iomem *priv2 = spu->priv2;
1552         u64 idx, ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1553         int i;
1554
1555         /* Restore, Step 59:
1556          */
1557
1558         /* Restore CH 1 without count */
1559         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1560         out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[1]);
1561
1562         /* Restore the following CH: [0,3,4,24,25,27] */
1563         for (i = 0; i < 7; i++) {
1564                 idx = ch_indices[i];
1565                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1566                 eieio();
1567                 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1568                 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1569                 eieio();
1570         }
1571 }
1572
1573 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1574 {
1575         struct spu_priv2 __iomem *priv2 = spu->priv2;
1576         u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1577         u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1578         u64 idx;
1579         int i;
1580
1581         /* Restore, Step 60:
1582          *     Restore the following CH: [9,21,23].
1583          */
1584         ch_counts[0] = 1UL;
1585         ch_counts[1] = csa->spu_chnlcnt_RW[21];
1586         ch_counts[2] = 1UL;
1587         for (i = 0; i < 3; i++) {
1588                 idx = ch_indices[i];
1589                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1590                 eieio();
1591                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1592                 eieio();
1593         }
1594 }
1595
1596 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1597 {
1598         struct spu_priv2 __iomem *priv2 = spu->priv2;
1599
1600         /* Restore, Step 61:
1601          *     Restore the SPU_LSLR register from CSA.
1602          */
1603         out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1604         eieio();
1605 }
1606
1607 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1608 {
1609         struct spu_priv2 __iomem *priv2 = spu->priv2;
1610
1611         /* Restore, Step 62:
1612          *     Restore the SPU_Cfg register from CSA.
1613          */
1614         out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1615         eieio();
1616 }
1617
1618 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1619 {
1620         /* Restore, Step 63:
1621          *     Restore PM_Trace_Tag_Wait_Mask from CSA.
1622          *     Not performed by this implementation.
1623          */
1624 }
1625
1626 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1627 {
1628         struct spu_problem __iomem *prob = spu->problem;
1629
1630         /* Restore, Step 64:
1631          *     Restore SPU_NPC from CSA.
1632          */
1633         out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1634         eieio();
1635 }
1636
1637 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1638 {
1639         struct spu_priv2 __iomem *priv2 = spu->priv2;
1640         int i;
1641
1642         /* Restore, Step 65:
1643          *     Restore MFC_RdSPU_MB from CSA.
1644          */
1645         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1646         eieio();
1647         out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1648         for (i = 0; i < 4; i++) {
1649                 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1650         }
1651         eieio();
1652 }
1653
1654 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1655 {
1656         struct spu_problem __iomem *prob = spu->problem;
1657         u32 dummy = 0;
1658
1659         /* Restore, Step 66:
1660          *     If CSA.MB_Stat[P]=0 (mailbox empty) then
1661          *     read from the PPU_MB register.
1662          */
1663         if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1664                 dummy = in_be32(&prob->pu_mb_R);
1665                 eieio();
1666         }
1667 }
1668
1669 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1670 {
1671         struct spu_priv2 __iomem *priv2 = spu->priv2;
1672         u64 dummy = 0UL;
1673
1674         /* Restore, Step 66:
1675          *     If CSA.MB_Stat[I]=0 (mailbox empty) then
1676          *     read from the PPUINT_MB register.
1677          */
1678         if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1679                 dummy = in_be64(&priv2->puint_mb_R);
1680                 eieio();
1681                 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1682                 eieio();
1683         }
1684 }
1685
1686 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1687 {
1688         /* Restore, Step 69:
1689          *     Restore the MFC_SR1 register from CSA.
1690          */
1691         spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1692         eieio();
1693 }
1694
1695 static inline void restore_other_spu_access(struct spu_state *csa,
1696                                             struct spu *spu)
1697 {
1698         /* Restore, Step 70:
1699          *     Restore other SPU mappings to this SPU. TBD.
1700          */
1701 }
1702
1703 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1704 {
1705         struct spu_problem __iomem *prob = spu->problem;
1706
1707         /* Restore, Step 71:
1708          *     If CSA.SPU_Status[R]=1 then write
1709          *     SPU_RunCntl[R0R1]='01'.
1710          */
1711         if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1712                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1713                 eieio();
1714         }
1715 }
1716
1717 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1718 {
1719         struct spu_priv2 __iomem *priv2 = spu->priv2;
1720
1721         /* Restore, Step 72:
1722          *    Restore the MFC_CNTL register for the CSA.
1723          */
1724         out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1725         eieio();
1726         /*
1727          * FIXME: this is to restart a DMA that we were processing
1728          *        before the save. better remember the fault information
1729          *        in the csa instead.
1730          */
1731         if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1732                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1733                 eieio();
1734         }
1735 }
1736
1737 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1738 {
1739         /* Restore, Step 73:
1740          *     Enable user-space access (if provided) to this
1741          *     SPU by mapping the virtual pages assigned to
1742          *     the SPU memory-mapped I/O (MMIO) for problem
1743          *     state. TBD.
1744          */
1745 }
1746
1747 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1748 {
1749         /* Restore, Step 74:
1750          *     Reset the "context switch active" flag.
1751          */
1752         clear_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
1753         mb();
1754 }
1755
1756 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1757 {
1758         /* Restore, Step 75:
1759          *     Re-enable SPU interrupts.
1760          */
1761         spin_lock_irq(&spu->register_lock);
1762         spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1763         spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1764         spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1765         spin_unlock_irq(&spu->register_lock);
1766 }
1767
1768 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1769 {
1770         /*
1771          * Combined steps 2-18 of SPU context save sequence, which
1772          * quiesce the SPU state (disable SPU execution, MFC command
1773          * queues, decrementer, SPU interrupts, etc.).
1774          *
1775          * Returns      0 on success.
1776          *              2 if failed step 2.
1777          *              6 if failed step 6.
1778          */
1779
1780         if (check_spu_isolate(prev, spu)) {     /* Step 2. */
1781                 return 2;
1782         }
1783         disable_interrupts(prev, spu);          /* Step 3. */
1784         set_watchdog_timer(prev, spu);          /* Step 4. */
1785         inhibit_user_access(prev, spu);         /* Step 5. */
1786         if (check_spu_isolate(prev, spu)) {     /* Step 6. */
1787                 return 6;
1788         }
1789         set_switch_pending(prev, spu);          /* Step 7. */
1790         save_mfc_cntl(prev, spu);               /* Step 8. */
1791         save_spu_runcntl(prev, spu);            /* Step 9. */
1792         save_mfc_sr1(prev, spu);                /* Step 10. */
1793         save_spu_status(prev, spu);             /* Step 11. */
1794         save_mfc_decr(prev, spu);               /* Step 12. */
1795         halt_mfc_decr(prev, spu);               /* Step 13. */
1796         save_timebase(prev, spu);               /* Step 14. */
1797         remove_other_spu_access(prev, spu);     /* Step 15. */
1798         do_mfc_mssync(prev, spu);               /* Step 16. */
1799         issue_mfc_tlbie(prev, spu);             /* Step 17. */
1800         handle_pending_interrupts(prev, spu);   /* Step 18. */
1801
1802         return 0;
1803 }
1804
1805 static void save_csa(struct spu_state *prev, struct spu *spu)
1806 {
1807         /*
1808          * Combine steps 19-44 of SPU context save sequence, which
1809          * save regions of the privileged & problem state areas.
1810          */
1811
1812         save_mfc_queues(prev, spu);     /* Step 19. */
1813         save_ppu_querymask(prev, spu);  /* Step 20. */
1814         save_ppu_querytype(prev, spu);  /* Step 21. */
1815         save_mfc_csr_tsq(prev, spu);    /* Step 22. */
1816         save_mfc_csr_cmd(prev, spu);    /* Step 23. */
1817         save_mfc_csr_ato(prev, spu);    /* Step 24. */
1818         save_mfc_tclass_id(prev, spu);  /* Step 25. */
1819         set_mfc_tclass_id(prev, spu);   /* Step 26. */
1820         purge_mfc_queue(prev, spu);     /* Step 27. */
1821         wait_purge_complete(prev, spu); /* Step 28. */
1822         setup_mfc_sr1(prev, spu);       /* Step 30. */
1823         save_spu_npc(prev, spu);        /* Step 31. */
1824         save_spu_privcntl(prev, spu);   /* Step 32. */
1825         reset_spu_privcntl(prev, spu);  /* Step 33. */
1826         save_spu_lslr(prev, spu);       /* Step 34. */
1827         reset_spu_lslr(prev, spu);      /* Step 35. */
1828         save_spu_cfg(prev, spu);        /* Step 36. */
1829         save_pm_trace(prev, spu);       /* Step 37. */
1830         save_mfc_rag(prev, spu);        /* Step 38. */
1831         save_ppu_mb_stat(prev, spu);    /* Step 39. */
1832         save_ppu_mb(prev, spu);         /* Step 40. */
1833         save_ppuint_mb(prev, spu);      /* Step 41. */
1834         save_ch_part1(prev, spu);       /* Step 42. */
1835         save_spu_mb(prev, spu);         /* Step 43. */
1836         save_mfc_cmd(prev, spu);        /* Step 44. */
1837         reset_ch(prev, spu);            /* Step 45. */
1838 }
1839
1840 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1841 {
1842         /*
1843          * Perform steps 46-57 of SPU context save sequence,
1844          * which save regions of the local store and register
1845          * file.
1846          */
1847
1848         resume_mfc_queue(prev, spu);    /* Step 46. */
1849         setup_mfc_slbs(prev, spu);      /* Step 47. */
1850         set_switch_active(prev, spu);   /* Step 48. */
1851         enable_interrupts(prev, spu);   /* Step 49. */
1852         save_ls_16kb(prev, spu);        /* Step 50. */
1853         set_spu_npc(prev, spu);         /* Step 51. */
1854         set_signot1(prev, spu);         /* Step 52. */
1855         set_signot2(prev, spu);         /* Step 53. */
1856         send_save_code(prev, spu);      /* Step 54. */
1857         set_ppu_querymask(prev, spu);   /* Step 55. */
1858         wait_tag_complete(prev, spu);   /* Step 56. */
1859         wait_spu_stopped(prev, spu);    /* Step 57. */
1860 }
1861
1862 static void force_spu_isolate_exit(struct spu *spu)
1863 {
1864         struct spu_problem __iomem *prob = spu->problem;
1865         struct spu_priv2 __iomem *priv2 = spu->priv2;
1866
1867         /* Stop SPE execution and wait for completion. */
1868         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1869         iobarrier_rw();
1870         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1871
1872         /* Restart SPE master runcntl. */
1873         spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1874         iobarrier_w();
1875
1876         /* Initiate isolate exit request and wait for completion. */
1877         out_be64(&priv2->spu_privcntl_RW, 4LL);
1878         iobarrier_w();
1879         out_be32(&prob->spu_runcntl_RW, 2);
1880         iobarrier_rw();
1881         POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1882                                 & SPU_STATUS_STOPPED_BY_STOP));
1883
1884         /* Reset load request to normal. */
1885         out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1886         iobarrier_w();
1887 }
1888
1889 /**
1890  * stop_spu_isolate
1891  *      Check SPU run-control state and force isolated
1892  *      exit function as necessary.
1893  */
1894 static void stop_spu_isolate(struct spu *spu)
1895 {
1896         struct spu_problem __iomem *prob = spu->problem;
1897
1898         if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1899                 /* The SPU is in isolated state; the only way
1900                  * to get it out is to perform an isolated
1901                  * exit (clean) operation.
1902                  */
1903                 force_spu_isolate_exit(spu);
1904         }
1905 }
1906
1907 static void harvest(struct spu_state *prev, struct spu *spu)
1908 {
1909         /*
1910          * Perform steps 2-25 of SPU context restore sequence,
1911          * which resets an SPU either after a failed save, or
1912          * when using SPU for first time.
1913          */
1914
1915         disable_interrupts(prev, spu);          /* Step 2.  */
1916         inhibit_user_access(prev, spu);         /* Step 3.  */
1917         terminate_spu_app(prev, spu);           /* Step 4.  */
1918         set_switch_pending(prev, spu);          /* Step 5.  */
1919         stop_spu_isolate(spu);                  /* NEW.     */
1920         remove_other_spu_access(prev, spu);     /* Step 6.  */
1921         suspend_mfc(prev, spu);                 /* Step 7.  */
1922         wait_suspend_mfc_complete(prev, spu);   /* Step 8.  */
1923         if (!suspend_spe(prev, spu))            /* Step 9.  */
1924                 clear_spu_status(prev, spu);    /* Step 10. */
1925         do_mfc_mssync(prev, spu);               /* Step 11. */
1926         issue_mfc_tlbie(prev, spu);             /* Step 12. */
1927         handle_pending_interrupts(prev, spu);   /* Step 13. */
1928         purge_mfc_queue(prev, spu);             /* Step 14. */
1929         wait_purge_complete(prev, spu);         /* Step 15. */
1930         reset_spu_privcntl(prev, spu);          /* Step 16. */
1931         reset_spu_lslr(prev, spu);              /* Step 17. */
1932         setup_mfc_sr1(prev, spu);               /* Step 18. */
1933         spu_invalidate_slbs(spu);               /* Step 19. */
1934         reset_ch_part1(prev, spu);              /* Step 20. */
1935         reset_ch_part2(prev, spu);              /* Step 21. */
1936         enable_interrupts(prev, spu);           /* Step 22. */
1937         set_switch_active(prev, spu);           /* Step 23. */
1938         set_mfc_tclass_id(prev, spu);           /* Step 24. */
1939         resume_mfc_queue(prev, spu);            /* Step 25. */
1940 }
1941
1942 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1943 {
1944         /*
1945          * Perform steps 26-40 of SPU context restore sequence,
1946          * which restores regions of the local store and register
1947          * file.
1948          */
1949
1950         set_watchdog_timer(next, spu);          /* Step 26. */
1951         setup_spu_status_part1(next, spu);      /* Step 27. */
1952         setup_spu_status_part2(next, spu);      /* Step 28. */
1953         restore_mfc_rag(next, spu);             /* Step 29. */
1954         setup_mfc_slbs(next, spu);              /* Step 30. */
1955         set_spu_npc(next, spu);                 /* Step 31. */
1956         set_signot1(next, spu);                 /* Step 32. */
1957         set_signot2(next, spu);                 /* Step 33. */
1958         setup_decr(next, spu);                  /* Step 34. */
1959         setup_ppu_mb(next, spu);                /* Step 35. */
1960         setup_ppuint_mb(next, spu);             /* Step 36. */
1961         send_restore_code(next, spu);           /* Step 37. */
1962         set_ppu_querymask(next, spu);           /* Step 38. */
1963         wait_tag_complete(next, spu);           /* Step 39. */
1964         wait_spu_stopped(next, spu);            /* Step 40. */
1965 }
1966
1967 static void restore_csa(struct spu_state *next, struct spu *spu)
1968 {
1969         /*
1970          * Combine steps 41-76 of SPU context restore sequence, which
1971          * restore regions of the privileged & problem state areas.
1972          */
1973
1974         restore_spu_privcntl(next, spu);        /* Step 41. */
1975         restore_status_part1(next, spu);        /* Step 42. */
1976         restore_status_part2(next, spu);        /* Step 43. */
1977         restore_ls_16kb(next, spu);             /* Step 44. */
1978         wait_tag_complete(next, spu);           /* Step 45. */
1979         suspend_mfc(next, spu);                 /* Step 46. */
1980         wait_suspend_mfc_complete(next, spu);   /* Step 47. */
1981         issue_mfc_tlbie(next, spu);             /* Step 48. */
1982         clear_interrupts(next, spu);            /* Step 49. */
1983         restore_mfc_queues(next, spu);          /* Step 50. */
1984         restore_ppu_querymask(next, spu);       /* Step 51. */
1985         restore_ppu_querytype(next, spu);       /* Step 52. */
1986         restore_mfc_csr_tsq(next, spu);         /* Step 53. */
1987         restore_mfc_csr_cmd(next, spu);         /* Step 54. */
1988         restore_mfc_csr_ato(next, spu);         /* Step 55. */
1989         restore_mfc_tclass_id(next, spu);       /* Step 56. */
1990         set_llr_event(next, spu);               /* Step 57. */
1991         restore_decr_wrapped(next, spu);        /* Step 58. */
1992         restore_ch_part1(next, spu);            /* Step 59. */
1993         restore_ch_part2(next, spu);            /* Step 60. */
1994         restore_spu_lslr(next, spu);            /* Step 61. */
1995         restore_spu_cfg(next, spu);             /* Step 62. */
1996         restore_pm_trace(next, spu);            /* Step 63. */
1997         restore_spu_npc(next, spu);             /* Step 64. */
1998         restore_spu_mb(next, spu);              /* Step 65. */
1999         check_ppu_mb_stat(next, spu);           /* Step 66. */
2000         check_ppuint_mb_stat(next, spu);        /* Step 67. */
2001         spu_invalidate_slbs(spu);               /* Modified Step 68. */
2002         restore_mfc_sr1(next, spu);             /* Step 69. */
2003         restore_other_spu_access(next, spu);    /* Step 70. */
2004         restore_spu_runcntl(next, spu);         /* Step 71. */
2005         restore_mfc_cntl(next, spu);            /* Step 72. */
2006         enable_user_access(next, spu);          /* Step 73. */
2007         reset_switch_active(next, spu);         /* Step 74. */
2008         reenable_interrupts(next, spu);         /* Step 75. */
2009 }
2010
2011 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2012 {
2013         int rc;
2014
2015         /*
2016          * SPU context save can be broken into three phases:
2017          *
2018          *     (a) quiesce [steps 2-16].
2019          *     (b) save of CSA, performed by PPE [steps 17-42]
2020          *     (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2021          *
2022          * Returns      0 on success.
2023          *              2,6 if failed to quiece SPU
2024          *              53 if SPU-side of save failed.
2025          */
2026
2027         rc = quiece_spu(prev, spu);             /* Steps 2-16. */
2028         switch (rc) {
2029         default:
2030         case 2:
2031         case 6:
2032                 harvest(prev, spu);
2033                 return rc;
2034                 break;
2035         case 0:
2036                 break;
2037         }
2038         save_csa(prev, spu);                    /* Steps 17-43. */
2039         save_lscsa(prev, spu);                  /* Steps 44-53. */
2040         return check_save_status(prev, spu);    /* Step 54.     */
2041 }
2042
2043 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2044 {
2045         int rc;
2046
2047         /*
2048          * SPU context restore can be broken into three phases:
2049          *
2050          *    (a) harvest (or reset) SPU [steps 2-24].
2051          *    (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2052          *    (c) restore CSA [steps 41-76], performed by PPE.
2053          *
2054          * The 'harvest' step is not performed here, but rather
2055          * as needed below.
2056          */
2057
2058         restore_lscsa(next, spu);               /* Steps 24-39. */
2059         rc = check_restore_status(next, spu);   /* Step 40.     */
2060         switch (rc) {
2061         default:
2062                 /* Failed. Return now. */
2063                 return rc;
2064                 break;
2065         case 0:
2066                 /* Fall through to next step. */
2067                 break;
2068         }
2069         restore_csa(next, spu);
2070
2071         return 0;
2072 }
2073
2074 /**
2075  * spu_save - SPU context save, with locking.
2076  * @prev: pointer to SPU context save area, to be saved.
2077  * @spu: pointer to SPU iomem structure.
2078  *
2079  * Acquire locks, perform the save operation then return.
2080  */
2081 int spu_save(struct spu_state *prev, struct spu *spu)
2082 {
2083         int rc;
2084
2085         acquire_spu_lock(spu);          /* Step 1.     */
2086         prev->dar = spu->dar;
2087         prev->dsisr = spu->dsisr;
2088         spu->dar = 0;
2089         spu->dsisr = 0;
2090         rc = __do_spu_save(prev, spu);  /* Steps 2-53. */
2091         release_spu_lock(spu);
2092         if (rc != 0 && rc != 2 && rc != 6) {
2093                 panic("%s failed on SPU[%d], rc=%d.\n",
2094                       __func__, spu->number, rc);
2095         }
2096         return 0;
2097 }
2098 EXPORT_SYMBOL_GPL(spu_save);
2099
2100 /**
2101  * spu_restore - SPU context restore, with harvest and locking.
2102  * @new: pointer to SPU context save area, to be restored.
2103  * @spu: pointer to SPU iomem structure.
2104  *
2105  * Perform harvest + restore, as we may not be coming
2106  * from a previous successful save operation, and the
2107  * hardware state is unknown.
2108  */
2109 int spu_restore(struct spu_state *new, struct spu *spu)
2110 {
2111         int rc;
2112
2113         acquire_spu_lock(spu);
2114         harvest(NULL, spu);
2115         spu->slb_replace = 0;
2116         new->dar = 0;
2117         new->dsisr = 0;
2118         spu->class_0_pending = 0;
2119         rc = __do_spu_restore(new, spu);
2120         release_spu_lock(spu);
2121         if (rc) {
2122                 panic("%s failed on SPU[%d] rc=%d.\n",
2123                        __func__, spu->number, rc);
2124         }
2125         return rc;
2126 }
2127 EXPORT_SYMBOL_GPL(spu_restore);
2128
2129 /**
2130  * spu_harvest - SPU harvest (reset) operation
2131  * @spu: pointer to SPU iomem structure.
2132  *
2133  * Perform SPU harvest (reset) operation.
2134  */
2135 void spu_harvest(struct spu *spu)
2136 {
2137         acquire_spu_lock(spu);
2138         harvest(NULL, spu);
2139         release_spu_lock(spu);
2140 }
2141
2142 static void init_prob(struct spu_state *csa)
2143 {
2144         csa->spu_chnlcnt_RW[9] = 1;
2145         csa->spu_chnlcnt_RW[21] = 16;
2146         csa->spu_chnlcnt_RW[23] = 1;
2147         csa->spu_chnlcnt_RW[28] = 1;
2148         csa->spu_chnlcnt_RW[30] = 1;
2149         csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2150         csa->prob.mb_stat_R = 0x000400;
2151 }
2152
2153 static void init_priv1(struct spu_state *csa)
2154 {
2155         /* Enable decode, relocate, tlbie response, master runcntl. */
2156         csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2157             MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2158             MFC_STATE1_PROBLEM_STATE_MASK |
2159             MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2160
2161         /* Enable OS-specific set of interrupts. */
2162         csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2163             CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2164             CLASS0_ENABLE_SPU_ERROR_INTR;
2165         csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2166             CLASS1_ENABLE_STORAGE_FAULT_INTR;
2167         csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2168             CLASS2_ENABLE_SPU_HALT_INTR |
2169             CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2170 }
2171
2172 static void init_priv2(struct spu_state *csa)
2173 {
2174         csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2175         csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2176             MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2177             MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2178 }
2179
2180 /**
2181  * spu_alloc_csa - allocate and initialize an SPU context save area.
2182  *
2183  * Allocate and initialize the contents of an SPU context save area.
2184  * This includes enabling address translation, interrupt masks, etc.,
2185  * as appropriate for the given OS environment.
2186  *
2187  * Note that storage for the 'lscsa' is allocated separately,
2188  * as it is by far the largest of the context save regions,
2189  * and may need to be pinned or otherwise specially aligned.
2190  */
2191 void spu_init_csa(struct spu_state *csa)
2192 {
2193         struct spu_lscsa *lscsa;
2194         unsigned char *p;
2195
2196         if (!csa)
2197                 return;
2198         memset(csa, 0, sizeof(struct spu_state));
2199
2200         lscsa = vmalloc(sizeof(struct spu_lscsa));
2201         if (!lscsa)
2202                 return;
2203
2204         memset(lscsa, 0, sizeof(struct spu_lscsa));
2205         csa->lscsa = lscsa;
2206         spin_lock_init(&csa->register_lock);
2207
2208         /* Set LS pages reserved to allow for user-space mapping. */
2209         for (p = lscsa->ls; p < lscsa->ls + LS_SIZE; p += PAGE_SIZE)
2210                 SetPageReserved(vmalloc_to_page(p));
2211
2212         init_prob(csa);
2213         init_priv1(csa);
2214         init_priv2(csa);
2215 }
2216 EXPORT_SYMBOL_GPL(spu_init_csa);
2217
2218 void spu_fini_csa(struct spu_state *csa)
2219 {
2220         /* Clear reserved bit before vfree. */
2221         unsigned char *p;
2222         for (p = csa->lscsa->ls; p < csa->lscsa->ls + LS_SIZE; p += PAGE_SIZE)
2223                 ClearPageReserved(vmalloc_to_page(p));
2224
2225         vfree(csa->lscsa);
2226 }
2227 EXPORT_SYMBOL_GPL(spu_fini_csa);