arch/powerpc/platforms/cell/setup.c

   1 /*
   2  *  linux/arch/powerpc/platforms/cell/cell_setup.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Adapted from 'alpha' version by Gary Thomas
   6  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   7  *  Modified by PPC64 Team, IBM Corp
   8  *  Modified by Cell Team, IBM Deutschland Entwicklung GmbH
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/sched.h>
  18 #include <linux/kernel.h>
  19 #include <linux/mm.h>
  20 #include <linux/stddef.h>
  21 #include <linux/unistd.h>
  22 #include <linux/slab.h>
  23 #include <linux/user.h>
  24 #include <linux/reboot.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/irq.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/root_dev.h>
  30 #include <linux/console.h>
  31 #include <linux/mutex.h>
  32 #include <linux/memory_hotplug.h>
  33 #include <linux/of_platform.h>
  34
  35 #include <asm/mmu.h>
  36 #include <asm/processor.h>
  37 #include <asm/io.h>
  38 #include <asm/kexec.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/prom.h>
  41 #include <asm/rtas.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/iommu.h>
  44 #include <asm/dma.h>
  45 #include <asm/machdep.h>
  46 #include <asm/time.h>
  47 #include <asm/nvram.h>
  48 #include <asm/cputable.h>
  49 #include <asm/ppc-pci.h>
  50 #include <asm/irq.h>
  51 #include <asm/spu.h>
  52 #include <asm/spu_priv1.h>
  53 #include <asm/udbg.h>
  54 #include <asm/mpic.h>
  55 #include <asm/cell-regs.h>
  56
  57 #include "interrupt.h"
  58 #include "pervasive.h"
  59 #include "ras.h"
  60
  61 #ifdef DEBUG
  62 #define DBG(fmt...) udbg_printf(fmt)
  63 #else
  64 #define DBG(fmt...)
  65 #endif
  66
  67 static void cell_show_cpuinfo(struct seq_file *m)
  68 {
  69         struct device_node *root;
  70         const char *model = "";
  71
  72         root = of_find_node_by_path("/");
  73         if (root)
  74                 model = of_get_property(root, "model", NULL);
  75         seq_printf(m, "machine\t\t: CHRP %s\n", model);
  76         of_node_put(root);
  77 }
  78
  79 static void cell_progress(char *s, unsigned short hex)
  80 {
  81         printk("*** %04x : %s\n", hex, s ? s : "");
  82 }
  83
  84 static int __init cell_publish_devices(void)
  85 {
  86         int node;
  87
  88         /* Publish OF platform devices for southbridge IOs */
  89         of_platform_bus_probe(NULL, NULL, NULL);
  90
  91         /* There is no device for the MIC memory controller, thus we create
  92          * a platform device for it to attach the EDAC driver to.
  93          */
  94         for_each_online_node(node) {
  95                 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
  96                         continue;
  97                 platform_device_register_simple("cbe-mic", node, NULL, 0);
  98         }
  99         return 0;
 100 }
 101 machine_subsys_initcall(cell, cell_publish_devices);
 102
 103 static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc)
 104 {
 105         struct mpic *mpic = desc->handler_data;
 106         unsigned int virq;
 107
 108         virq = mpic_get_one_irq(mpic);
 109         if (virq != NO_IRQ)
 110                 generic_handle_irq(virq);
 111         desc->chip->eoi(irq);
 112 }
 113
 114 static void __init mpic_init_IRQ(void)
 115 {
 116         struct device_node *dn;
 117         struct mpic *mpic;
 118         unsigned int virq;
 119
 120         for (dn = NULL;
 121              (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
 122                 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
 123                         continue;
 124
 125                 /* The MPIC driver will get everything it needs from the
 126                  * device-tree, just pass 0 to all arguments
 127                  */
 128                 mpic = mpic_alloc(dn, 0, 0, 0, 0, " MPIC     ");
 129                 if (mpic == NULL)
 130                         continue;
 131                 mpic_init(mpic);
 132
 133                 virq = irq_of_parse_and_map(dn, 0);
 134                 if (virq == NO_IRQ)
 135                         continue;
 136
 137                 printk(KERN_INFO "%s : hooking up to IRQ %d\n",
 138                        dn->full_name, virq);
 139                 set_irq_data(virq, mpic);
 140                 set_irq_chained_handler(virq, cell_mpic_cascade);
 141         }
 142 }
 143
 144
 145 static void __init cell_init_irq(void)
 146 {
 147         iic_init_IRQ();
 148         spider_init_IRQ();
 149         mpic_init_IRQ();
 150 }
 151
 152 static void __init cell_set_dabrx(void)
 153 {
 154         mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
 155 }
 156
 157 static void __init cell_setup_arch(void)
 158 {
 159 #ifdef CONFIG_SPU_BASE
 160         spu_priv1_ops = &spu_priv1_mmio_ops;
 161         spu_management_ops = &spu_management_of_ops;
 162 #endif
 163
 164         cbe_regs_init();
 165
 166         cell_set_dabrx();
 167
 168 #ifdef CONFIG_CBE_RAS
 169         cbe_ras_init();
 170 #endif
 171
 172 #ifdef CONFIG_SMP
 173         smp_init_cell();
 174 #endif
 175         /* init to some ~sane value until calibrate_delay() runs */
 176         loops_per_jiffy = 50000000;
 177
 178         /* Find and initialize PCI host bridges */
 179         init_pci_config_tokens();
 180         find_and_init_phbs();
 181         cbe_pervasive_init();
 182 #ifdef CONFIG_DUMMY_CONSOLE
 183         conswitchp = &dummy_con;
 184 #endif
 185
 186         mmio_nvram_init();
 187 }
 188
 189 static int __init cell_probe(void)
 190 {
 191         unsigned long root = of_get_flat_dt_root();
 192
 193         if (!of_flat_dt_is_compatible(root, "IBM,CBEA") &&
 194             !of_flat_dt_is_compatible(root, "IBM,CPBW-1.0"))
 195                 return 0;
 196
 197         hpte_init_native();
 198
 199         return 1;
 200 }
 201
 202 define_machine(cell) {
 203         .name                   = "Cell",
 204         .probe                  = cell_probe,
 205         .setup_arch             = cell_setup_arch,
 206         .show_cpuinfo           = cell_show_cpuinfo,
 207         .restart                = rtas_restart,
 208         .power_off              = rtas_power_off,
 209         .halt                   = rtas_halt,
 210         .get_boot_time          = rtas_get_boot_time,
 211         .get_rtc_time           = rtas_get_rtc_time,
 212         .set_rtc_time           = rtas_set_rtc_time,
 213         .calibrate_decr         = generic_calibrate_decr,
 214         .progress               = cell_progress,
 215         .init_IRQ               = cell_init_irq,
 216         .pci_setup_phb          = rtas_setup_phb,
 217 #ifdef CONFIG_KEXEC
 218         .machine_kexec          = default_machine_kexec,
 219         .machine_kexec_prepare  = default_machine_kexec_prepare,
 220         .machine_crash_shutdown = default_machine_crash_shutdown,
 221 #endif
 222 };