arch/powerpc/platforms/85xx/twr_p102x.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Michael Johnston <michael.johnston@freescale.com>
   6  *
   7  * Description:
   8  * TWR-P102x Board Setup
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/errno.h>
  14 #include <linux/fsl/guts.h>
  15 #include <linux/pci.h>
  16 #include <linux/of_platform.h>
  17
  18 #include <asm/pci-bridge.h>
  19 #include <asm/udbg.h>
  20 #include <asm/mpic.h>
  21 #include <soc/fsl/qe/qe.h>
  22 #include <soc/fsl/qe/qe_ic.h>
  23
  24 #include <sysdev/fsl_soc.h>
  25 #include <sysdev/fsl_pci.h>
  26 #include "smp.h"
  27
  28 #include "mpc85xx.h"
  29
  30 static void __init twr_p1025_pic_init(void)
  31 {
  32         struct mpic *mpic;
  33
  34 #ifdef CONFIG_QUICC_ENGINE
  35         struct device_node *np;
  36 #endif
  37
  38         mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
  39                         MPIC_SINGLE_DEST_CPU,
  40                         0, 256, " OpenPIC  ");
  41
  42         BUG_ON(mpic == NULL);
  43         mpic_init(mpic);
  44
  45 #ifdef CONFIG_QUICC_ENGINE
  46         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  47         if (np) {
  48                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
  49                                 qe_ic_cascade_high_mpic);
  50                 of_node_put(np);
  51         } else
  52                 pr_err("Could not find qe-ic node\n");
  53 #endif
  54 }
  55
  56 /* ************************************************************************
  57  *
  58  * Setup the architecture
  59  *
  60  */
  61 static void __init twr_p1025_setup_arch(void)
  62 {
  63         if (ppc_md.progress)
  64                 ppc_md.progress("twr_p1025_setup_arch()", 0);
  65
  66         mpc85xx_smp_init();
  67
  68         fsl_pci_assign_primary();
  69
  70 #ifdef CONFIG_QUICC_ENGINE
  71         mpc85xx_qe_par_io_init();
  72
  73 #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
  74         if (machine_is(twr_p1025)) {
  75                 struct ccsr_guts __iomem *guts;
  76                 struct device_node *np;
  77
  78                 np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
  79                 if (np) {
  80                         guts = of_iomap(np, 0);
  81                         if (!guts)
  82                                 pr_err("twr_p1025: could not map global utilities register\n");
  83                         else {
  84                         /* P1025 has pins muxed for QE and other functions. To
  85                          * enable QE UEC mode, we need to set bit QE0 for UCC1
  86                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
  87                          * and QE12 for QE MII management signals in PMUXCR
  88                          * register.
  89                          * Set QE mux bits in PMUXCR */
  90                         setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
  91                                         MPC85xx_PMUXCR_QE(3) |
  92                                         MPC85xx_PMUXCR_QE(9) |
  93                                         MPC85xx_PMUXCR_QE(12));
  94                         iounmap(guts);
  95
  96 #if IS_ENABLED(CONFIG_SERIAL_QE)
  97                         /* On P1025TWR board, the UCC7 acted as UART port.
  98                          * However, The UCC7's CTS pin is low level in default,
  99                          * it will impact the transmission in full duplex
 100                          * communication. So disable the Flow control pin PA18.
 101                          * The UCC7 UART just can use RXD and TXD pins.
 102                          */
 103                         par_io_config_pin(0, 18, 0, 0, 0, 0);
 104 #endif
 105                         /* Drive PB29 to CPLD low - CPLD will then change
 106                          * muxing from LBC to QE */
 107                         par_io_config_pin(1, 29, 1, 0, 0, 0);
 108                         par_io_data_set(1, 29, 0);
 109                         }
 110                         of_node_put(np);
 111                 }
 112         }
 113 #endif
 114 #endif  /* CONFIG_QUICC_ENGINE */
 115
 116         pr_info("TWR-P1025 board from Freescale Semiconductor\n");
 117 }
 118
 119 machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
 120
 121 static int __init twr_p1025_probe(void)
 122 {
 123         return of_machine_is_compatible("fsl,TWR-P1025");
 124 }
 125
 126 define_machine(twr_p1025) {
 127         .name                   = "TWR-P1025",
 128         .probe                  = twr_p1025_probe,
 129         .setup_arch             = twr_p1025_setup_arch,
 130         .init_IRQ               = twr_p1025_pic_init,
 131 #ifdef CONFIG_PCI
 132         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 133 #endif
 134         .get_irq                = mpic_get_irq,
 135         .calibrate_decr         = generic_calibrate_decr,
 136         .progress               = udbg_progress,
 137 };