arch/powerpc/platforms/85xx/twr_p102x.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Michael Johnston <michael.johnston@freescale.com>
   6  *
   7  * Description:
   8  * TWR-P102x Board Setup
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/errno.h>
  14 #include <linux/fsl/guts.h>
  15 #include <linux/pci.h>
  16 #include <linux/of_platform.h>
  17
  18 #include <asm/pci-bridge.h>
  19 #include <asm/udbg.h>
  20 #include <asm/mpic.h>
  21 #include <soc/fsl/qe/qe.h>
  22
  23 #include <sysdev/fsl_soc.h>
  24 #include <sysdev/fsl_pci.h>
  25 #include "smp.h"
  26
  27 #include "mpc85xx.h"
  28
  29 static void __init twr_p1025_pic_init(void)
  30 {
  31         struct mpic *mpic;
  32
  33         mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
  34                         MPIC_SINGLE_DEST_CPU,
  35                         0, 256, " OpenPIC  ");
  36
  37         BUG_ON(mpic == NULL);
  38         mpic_init(mpic);
  39 }
  40
  41 /* ************************************************************************
  42  *
  43  * Setup the architecture
  44  *
  45  */
  46 static void __init twr_p1025_setup_arch(void)
  47 {
  48 #ifdef CONFIG_QUICC_ENGINE
  49         struct device_node *np;
  50 #endif
  51
  52         if (ppc_md.progress)
  53                 ppc_md.progress("twr_p1025_setup_arch()", 0);
  54
  55         mpc85xx_smp_init();
  56
  57         fsl_pci_assign_primary();
  58
  59 #ifdef CONFIG_QUICC_ENGINE
  60         mpc85xx_qe_par_io_init();
  61
  62 #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
  63         if (machine_is(twr_p1025)) {
  64                 struct ccsr_guts __iomem *guts;
  65
  66                 np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
  67                 if (np) {
  68                         guts = of_iomap(np, 0);
  69                         if (!guts)
  70                                 pr_err("twr_p1025: could not map global utilities register\n");
  71                         else {
  72                         /* P1025 has pins muxed for QE and other functions. To
  73                          * enable QE UEC mode, we need to set bit QE0 for UCC1
  74                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
  75                          * and QE12 for QE MII management signals in PMUXCR
  76                          * register.
  77                          * Set QE mux bits in PMUXCR */
  78                         setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
  79                                         MPC85xx_PMUXCR_QE(3) |
  80                                         MPC85xx_PMUXCR_QE(9) |
  81                                         MPC85xx_PMUXCR_QE(12));
  82                         iounmap(guts);
  83
  84 #if IS_ENABLED(CONFIG_SERIAL_QE)
  85                         /* On P1025TWR board, the UCC7 acted as UART port.
  86                          * However, The UCC7's CTS pin is low level in default,
  87                          * it will impact the transmission in full duplex
  88                          * communication. So disable the Flow control pin PA18.
  89                          * The UCC7 UART just can use RXD and TXD pins.
  90                          */
  91                         par_io_config_pin(0, 18, 0, 0, 0, 0);
  92 #endif
  93                         /* Drive PB29 to CPLD low - CPLD will then change
  94                          * muxing from LBC to QE */
  95                         par_io_config_pin(1, 29, 1, 0, 0, 0);
  96                         par_io_data_set(1, 29, 0);
  97                         }
  98                         of_node_put(np);
  99                 }
 100         }
 101 #endif
 102 #endif  /* CONFIG_QUICC_ENGINE */
 103
 104         pr_info("TWR-P1025 board from Freescale Semiconductor\n");
 105 }
 106
 107 machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
 108
 109 static int __init twr_p1025_probe(void)
 110 {
 111         return of_machine_is_compatible("fsl,TWR-P1025");
 112 }
 113
 114 define_machine(twr_p1025) {
 115         .name                   = "TWR-P1025",
 116         .probe                  = twr_p1025_probe,
 117         .setup_arch             = twr_p1025_setup_arch,
 118         .init_IRQ               = twr_p1025_pic_init,
 119 #ifdef CONFIG_PCI
 120         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 121 #endif
 122         .get_irq                = mpic_get_irq,
 123         .calibrate_decr         = generic_calibrate_decr,
 124         .progress               = udbg_progress,
 125 };