arch/powerpc/perf/power9-events-list.h

   1 /*
   2  * Performance counter support for POWER9 processors.
   3  *
   4  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 /*
  13  * Power9 event codes.
  14  */
  15 EVENT(PM_CYC,                                   0x0001e)
  16 EVENT(PM_ICT_NOSLOT_CYC,                        0x100f8)
  17 EVENT(PM_CMPLU_STALL,                           0x1e054)
  18 EVENT(PM_INST_CMPL,                             0x00002)
  19 EVENT(PM_BRU_CMPL,                              0x10012)
  20 EVENT(PM_BR_MPRED_CMPL,                         0x400f6)
  21
  22 /* All L1 D cache load references counted at finish, gated by reject */
  23 EVENT(PM_LD_REF_L1,                             0x100fc)
  24 /* Load Missed L1 */
  25 EVENT(PM_LD_MISS_L1_FIN,                        0x2c04e)
  26 /* Store Missed L1 */
  27 EVENT(PM_ST_MISS_L1,                            0x300f0)
  28 /* L1 cache data prefetches */
  29 EVENT(PM_L1_PREF,                               0x20054)
  30 /* Instruction fetches from L1 */
  31 EVENT(PM_INST_FROM_L1,                          0x04080)
  32 /* Demand iCache Miss */
  33 EVENT(PM_L1_ICACHE_MISS,                        0x200fd)
  34 /* Instruction Demand sectors wriittent into IL1 */
  35 EVENT(PM_L1_DEMAND_WRITE,                       0x0408c)
  36 /* Instruction prefetch written into IL1 */
  37 EVENT(PM_IC_PREF_WRITE,                         0x0488c)
  38 /* The data cache was reloaded from local core's L3 due to a demand load */
  39 EVENT(PM_DATA_FROM_L3,                          0x4c042)
  40 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
  41 EVENT(PM_DATA_FROM_L3MISS,                      0x300fe)
  42 /* All successful D-side store dispatches for this thread */
  43 EVENT(PM_L2_ST,                                 0x16880)
  44 /* All successful D-side store dispatches for this thread that were L2 Miss */
  45 EVENT(PM_L2_ST_MISS,                            0x26880)
  46 /* Total HW L3 prefetches(Load+store) */
  47 EVENT(PM_L3_PREF_ALL,                           0x4e052)
  48 /* Data PTEG reload */
  49 EVENT(PM_DTLB_MISS,                             0x300fc)
  50 /* ITLB Reloaded */
  51 EVENT(PM_ITLB_MISS,                             0x400fc)
  52 /* Run_Instructions */
  53 EVENT(PM_RUN_INST_CMPL,                         0x500fa)
  54 /* Run_cycles */
  55 EVENT(PM_RUN_CYC,                               0x600f4)