2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
16 #include <linux/uaccess.h>
19 #include <asm/machdep.h>
20 #include <asm/firmware.h>
21 #include <asm/ptrace.h>
22 #include <asm/code-patching.h>
24 #define BHRB_MAX_ENTRIES 32
25 #define BHRB_TARGET 0x0000000000000002
26 #define BHRB_PREDICTION 0x0000000000000001
27 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
29 struct cpu_hw_events {
36 struct perf_event *event[MAX_HWEVENTS];
37 u64 events[MAX_HWEVENTS];
38 unsigned int flags[MAX_HWEVENTS];
40 * The order of the MMCR array is:
41 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
42 * - 32-bit, MMCR0, MMCR1, MMCR2
44 unsigned long mmcr[4];
45 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
46 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
47 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
48 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
49 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
51 unsigned int txn_flags;
55 u64 bhrb_filter; /* BHRB HW branch filter */
56 unsigned int bhrb_users;
58 struct perf_branch_stack bhrb_stack;
59 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
63 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
65 static struct power_pmu *ppmu;
68 * Normally, to ignore kernel events we set the FCS (freeze counters
69 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
70 * hypervisor bit set in the MSR, or if we are running on a processor
71 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
72 * then we need to use the FCHV bit to ignore kernel events.
74 static unsigned int freeze_events_kernel = MMCR0_FCS;
77 * 32-bit doesn't have MMCRA but does have an MMCR2,
78 * and a few other names are different.
83 #define MMCR0_PMCjCE MMCR0_PMCnCE
89 #define MMCR0_PMCC_U6 0
91 #define SPRN_MMCRA SPRN_MMCR2
92 #define MMCRA_SAMPLE_ENABLE 0
94 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
98 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
99 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
103 static inline void perf_read_regs(struct pt_regs *regs)
107 static inline int perf_intr_is_nmi(struct pt_regs *regs)
112 static inline int siar_valid(struct pt_regs *regs)
117 static bool is_ebb_event(struct perf_event *event) { return false; }
118 static int ebb_event_check(struct perf_event *event) { return 0; }
119 static void ebb_event_add(struct perf_event *event) { }
120 static void ebb_switch_out(unsigned long mmcr0) { }
121 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
123 return cpuhw->mmcr[0];
126 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
127 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
128 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
129 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
130 static void pmao_restore_workaround(bool ebb) { }
131 static bool use_ic(u64 event)
135 #endif /* CONFIG_PPC32 */
137 static bool regs_use_siar(struct pt_regs *regs)
140 * When we take a performance monitor exception the regs are setup
141 * using perf_read_regs() which overloads some fields, in particular
142 * regs->result to tell us whether to use SIAR.
144 * However if the regs are from another exception, eg. a syscall, then
145 * they have not been setup using perf_read_regs() and so regs->result
146 * is something random.
148 return ((TRAP(regs) == 0xf00) && regs->result);
152 * Things that are specific to 64-bit implementations.
156 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
158 unsigned long mmcra = regs->dsisr;
160 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
161 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
163 return 4 * (slot - 1);
170 * The user wants a data address recorded.
171 * If we're not doing instruction sampling, give them the SDAR
172 * (sampled data address). If we are doing instruction sampling, then
173 * only give them the SDAR if it corresponds to the instruction
174 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
175 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
177 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
179 unsigned long mmcra = regs->dsisr;
182 if (ppmu->flags & PPMU_HAS_SIER)
183 sdar_valid = regs->dar & SIER_SDAR_VALID;
185 unsigned long sdsync;
187 if (ppmu->flags & PPMU_SIAR_VALID)
188 sdsync = POWER7P_MMCRA_SDAR_VALID;
189 else if (ppmu->flags & PPMU_ALT_SIPR)
190 sdsync = POWER6_MMCRA_SDSYNC;
191 else if (ppmu->flags & PPMU_NO_SIAR)
192 sdsync = MMCRA_SAMPLE_ENABLE;
194 sdsync = MMCRA_SDSYNC;
196 sdar_valid = mmcra & sdsync;
199 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
200 *addrp = mfspr(SPRN_SDAR);
203 static bool regs_sihv(struct pt_regs *regs)
205 unsigned long sihv = MMCRA_SIHV;
207 if (ppmu->flags & PPMU_HAS_SIER)
208 return !!(regs->dar & SIER_SIHV);
210 if (ppmu->flags & PPMU_ALT_SIPR)
211 sihv = POWER6_MMCRA_SIHV;
213 return !!(regs->dsisr & sihv);
216 static bool regs_sipr(struct pt_regs *regs)
218 unsigned long sipr = MMCRA_SIPR;
220 if (ppmu->flags & PPMU_HAS_SIER)
221 return !!(regs->dar & SIER_SIPR);
223 if (ppmu->flags & PPMU_ALT_SIPR)
224 sipr = POWER6_MMCRA_SIPR;
226 return !!(regs->dsisr & sipr);
229 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
231 if (regs->msr & MSR_PR)
232 return PERF_RECORD_MISC_USER;
233 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
234 return PERF_RECORD_MISC_HYPERVISOR;
235 return PERF_RECORD_MISC_KERNEL;
238 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
240 bool use_siar = regs_use_siar(regs);
243 return perf_flags_from_msr(regs);
246 * If we don't have flags in MMCRA, rather than using
247 * the MSR, we intuit the flags from the address in
248 * SIAR which should give slightly more reliable
251 if (ppmu->flags & PPMU_NO_SIPR) {
252 unsigned long siar = mfspr(SPRN_SIAR);
253 if (is_kernel_addr(siar))
254 return PERF_RECORD_MISC_KERNEL;
255 return PERF_RECORD_MISC_USER;
258 /* PR has priority over HV, so order below is important */
260 return PERF_RECORD_MISC_USER;
262 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
263 return PERF_RECORD_MISC_HYPERVISOR;
265 return PERF_RECORD_MISC_KERNEL;
269 * Overload regs->dsisr to store MMCRA so we only need to read it once
271 * Overload regs->dar to store SIER if we have it.
272 * Overload regs->result to specify whether we should use the MSR (result
273 * is zero) or the SIAR (result is non zero).
275 static inline void perf_read_regs(struct pt_regs *regs)
277 unsigned long mmcra = mfspr(SPRN_MMCRA);
278 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
283 if (ppmu->flags & PPMU_HAS_SIER)
284 regs->dar = mfspr(SPRN_SIER);
287 * If this isn't a PMU exception (eg a software event) the SIAR is
288 * not valid. Use pt_regs.
290 * If it is a marked event use the SIAR.
292 * If the PMU doesn't update the SIAR for non marked events use
295 * If the PMU has HV/PR flags then check to see if they
296 * place the exception in userspace. If so, use pt_regs. In
297 * continuous sampling mode the SIAR and the PMU exception are
298 * not synchronised, so they may be many instructions apart.
299 * This can result in confusing backtraces. We still want
300 * hypervisor samples as well as samples in the kernel with
301 * interrupts off hence the userspace check.
303 if (TRAP(regs) != 0xf00)
305 else if ((ppmu->flags & PPMU_NO_SIAR))
309 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
311 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
316 regs->result = use_siar;
320 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
323 static inline int perf_intr_is_nmi(struct pt_regs *regs)
329 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
330 * must be sampled only if the SIAR-valid bit is set.
332 * For unmarked instructions and for processors that don't have the SIAR-Valid
333 * bit, assume that SIAR is valid.
335 static inline int siar_valid(struct pt_regs *regs)
337 unsigned long mmcra = regs->dsisr;
338 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
341 if (ppmu->flags & PPMU_HAS_SIER)
342 return regs->dar & SIER_SIAR_VALID;
344 if (ppmu->flags & PPMU_SIAR_VALID)
345 return mmcra & POWER7P_MMCRA_SIAR_VALID;
352 /* Reset all possible BHRB entries */
353 static void power_pmu_bhrb_reset(void)
355 asm volatile(PPC_CLRBHRB);
358 static void power_pmu_bhrb_enable(struct perf_event *event)
360 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
365 /* Clear BHRB if we changed task context to avoid data leaks */
366 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
367 power_pmu_bhrb_reset();
368 cpuhw->bhrb_context = event->ctx;
371 perf_sched_cb_inc(event->ctx->pmu);
374 static void power_pmu_bhrb_disable(struct perf_event *event)
376 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
381 WARN_ON_ONCE(!cpuhw->bhrb_users);
383 perf_sched_cb_dec(event->ctx->pmu);
385 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
386 /* BHRB cannot be turned off when other
387 * events are active on the PMU.
390 /* avoid stale pointer */
391 cpuhw->bhrb_context = NULL;
395 /* Called from ctxsw to prevent one process's branch entries to
396 * mingle with the other process's entries during context switch.
398 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
404 power_pmu_bhrb_reset();
406 /* Calculate the to address for a branch */
407 static __u64 power_pmu_bhrb_to(u64 addr)
413 if (is_kernel_addr(addr)) {
414 if (probe_kernel_read(&instr, (void *)addr, sizeof(instr)))
417 return branch_target(&instr);
420 /* Userspace: need copy instruction here then translate it */
422 ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
429 target = branch_target(&instr);
430 if ((!target) || (instr & BRANCH_ABSOLUTE))
433 /* Translate relative branch target from kernel to user address */
434 return target - (unsigned long)&instr + addr;
437 /* Processing BHRB entries */
438 static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
442 int r_index, u_index, pred;
446 while (r_index < ppmu->bhrb_nr) {
447 /* Assembly read function */
448 val = read_bhrb(r_index++);
450 /* Terminal marker: End of valid BHRB entries */
453 addr = val & BHRB_EA;
454 pred = val & BHRB_PREDICTION;
460 /* Branches are read most recent first (ie. mfbhrb 0 is
461 * the most recent branch).
462 * There are two types of valid entries:
463 * 1) a target entry which is the to address of a
464 * computed goto like a blr,bctr,btar. The next
465 * entry read from the bhrb will be branch
466 * corresponding to this target (ie. the actual
467 * blr/bctr/btar instruction).
468 * 2) a from address which is an actual branch. If a
469 * target entry proceeds this, then this is the
470 * matching branch for that target. If this is not
471 * following a target entry, then this is a branch
472 * where the target is given as an immediate field
473 * in the instruction (ie. an i or b form branch).
474 * In this case we need to read the instruction from
475 * memory to determine the target/to address.
478 if (val & BHRB_TARGET) {
479 /* Target branches use two entries
480 * (ie. computed gotos/XL form)
482 cpuhw->bhrb_entries[u_index].to = addr;
483 cpuhw->bhrb_entries[u_index].mispred = pred;
484 cpuhw->bhrb_entries[u_index].predicted = ~pred;
486 /* Get from address in next entry */
487 val = read_bhrb(r_index++);
488 addr = val & BHRB_EA;
489 if (val & BHRB_TARGET) {
490 /* Shouldn't have two targets in a
491 row.. Reset index and try again */
495 cpuhw->bhrb_entries[u_index].from = addr;
497 /* Branches to immediate field
499 cpuhw->bhrb_entries[u_index].from = addr;
500 cpuhw->bhrb_entries[u_index].to =
501 power_pmu_bhrb_to(addr);
502 cpuhw->bhrb_entries[u_index].mispred = pred;
503 cpuhw->bhrb_entries[u_index].predicted = ~pred;
509 cpuhw->bhrb_stack.nr = u_index;
513 static bool is_ebb_event(struct perf_event *event)
516 * This could be a per-PMU callback, but we'd rather avoid the cost. We
517 * check that the PMU supports EBB, meaning those that don't can still
518 * use bit 63 of the event code for something else if they wish.
520 return (ppmu->flags & PPMU_ARCH_207S) &&
521 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
524 static int ebb_event_check(struct perf_event *event)
526 struct perf_event *leader = event->group_leader;
528 /* Event and group leader must agree on EBB */
529 if (is_ebb_event(leader) != is_ebb_event(event))
532 if (is_ebb_event(event)) {
533 if (!(event->attach_state & PERF_ATTACH_TASK))
536 if (!leader->attr.pinned || !leader->attr.exclusive)
539 if (event->attr.freq ||
540 event->attr.inherit ||
541 event->attr.sample_type ||
542 event->attr.sample_period ||
543 event->attr.enable_on_exec)
550 static void ebb_event_add(struct perf_event *event)
552 if (!is_ebb_event(event) || current->thread.used_ebb)
556 * IFF this is the first time we've added an EBB event, set
557 * PMXE in the user MMCR0 so we can detect when it's cleared by
558 * userspace. We need this so that we can context switch while
559 * userspace is in the EBB handler (where PMXE is 0).
561 current->thread.used_ebb = 1;
562 current->thread.mmcr0 |= MMCR0_PMXE;
565 static void ebb_switch_out(unsigned long mmcr0)
567 if (!(mmcr0 & MMCR0_EBE))
570 current->thread.siar = mfspr(SPRN_SIAR);
571 current->thread.sier = mfspr(SPRN_SIER);
572 current->thread.sdar = mfspr(SPRN_SDAR);
573 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
574 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
577 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
579 unsigned long mmcr0 = cpuhw->mmcr[0];
584 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
585 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
588 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
589 * with pmao_restore_workaround() because we may add PMAO but we never
592 mmcr0 |= current->thread.mmcr0;
595 * Be careful not to set PMXE if userspace had it cleared. This is also
596 * compatible with pmao_restore_workaround() because it has already
597 * cleared PMXE and we leave PMAO alone.
599 if (!(current->thread.mmcr0 & MMCR0_PMXE))
600 mmcr0 &= ~MMCR0_PMXE;
602 mtspr(SPRN_SIAR, current->thread.siar);
603 mtspr(SPRN_SIER, current->thread.sier);
604 mtspr(SPRN_SDAR, current->thread.sdar);
607 * Merge the kernel & user values of MMCR2. The semantics we implement
608 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
609 * but not clear bits. If a task wants to be able to clear bits, ie.
610 * unfreeze counters, it should not set exclude_xxx in its events and
611 * instead manage the MMCR2 entirely by itself.
613 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
618 static void pmao_restore_workaround(bool ebb)
622 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
626 * On POWER8E there is a hardware defect which affects the PMU context
627 * switch logic, ie. power_pmu_disable/enable().
629 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
630 * by the hardware. Sometime later the actual PMU exception is
633 * If we context switch, or simply disable/enable, the PMU prior to the
634 * exception arriving, the exception will be lost when we clear PMAO.
636 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
637 * set, and this _should_ generate an exception. However because of the
638 * defect no exception is generated when we write PMAO, and we get
639 * stuck with no counters counting but no exception delivered.
641 * The workaround is to detect this case and tweak the hardware to
642 * create another pending PMU exception.
644 * We do that by setting up PMC6 (cycles) for an imminent overflow and
645 * enabling the PMU. That causes a new exception to be generated in the
646 * chip, but we don't take it yet because we have interrupts hard
647 * disabled. We then write back the PMU state as we want it to be seen
648 * by the exception handler. When we reenable interrupts the exception
649 * handler will be called and see the correct state.
651 * The logic is the same for EBB, except that the exception is gated by
652 * us having interrupts hard disabled as well as the fact that we are
653 * not in userspace. The exception is finally delivered when we return
657 /* Only if PMAO is set and PMAO_SYNC is clear */
658 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
661 /* If we're doing EBB, only if BESCR[GE] is set */
662 if (ebb && !(current->thread.bescr & BESCR_GE))
666 * We are already soft-disabled in power_pmu_enable(). We need to hard
667 * disable to actually prevent the PMU exception from firing.
672 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
673 * Using read/write_pmc() in a for loop adds 12 function calls and
674 * almost doubles our code size.
676 pmcs[0] = mfspr(SPRN_PMC1);
677 pmcs[1] = mfspr(SPRN_PMC2);
678 pmcs[2] = mfspr(SPRN_PMC3);
679 pmcs[3] = mfspr(SPRN_PMC4);
680 pmcs[4] = mfspr(SPRN_PMC5);
681 pmcs[5] = mfspr(SPRN_PMC6);
683 /* Ensure all freeze bits are unset */
684 mtspr(SPRN_MMCR2, 0);
686 /* Set up PMC6 to overflow in one cycle */
687 mtspr(SPRN_PMC6, 0x7FFFFFFE);
689 /* Enable exceptions and unfreeze PMC6 */
690 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
692 /* Now we need to refreeze and restore the PMCs */
693 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
695 mtspr(SPRN_PMC1, pmcs[0]);
696 mtspr(SPRN_PMC2, pmcs[1]);
697 mtspr(SPRN_PMC3, pmcs[2]);
698 mtspr(SPRN_PMC4, pmcs[3]);
699 mtspr(SPRN_PMC5, pmcs[4]);
700 mtspr(SPRN_PMC6, pmcs[5]);
703 static bool use_ic(u64 event)
705 if (cpu_has_feature(CPU_FTR_POWER9_DD1) &&
706 (event == 0x200f2 || event == 0x300f2))
711 #endif /* CONFIG_PPC64 */
713 static void perf_event_interrupt(struct pt_regs *regs);
716 * Read one performance monitor counter (PMC).
718 static unsigned long read_pmc(int idx)
724 val = mfspr(SPRN_PMC1);
727 val = mfspr(SPRN_PMC2);
730 val = mfspr(SPRN_PMC3);
733 val = mfspr(SPRN_PMC4);
736 val = mfspr(SPRN_PMC5);
739 val = mfspr(SPRN_PMC6);
743 val = mfspr(SPRN_PMC7);
746 val = mfspr(SPRN_PMC8);
748 #endif /* CONFIG_PPC64 */
750 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
759 static void write_pmc(int idx, unsigned long val)
763 mtspr(SPRN_PMC1, val);
766 mtspr(SPRN_PMC2, val);
769 mtspr(SPRN_PMC3, val);
772 mtspr(SPRN_PMC4, val);
775 mtspr(SPRN_PMC5, val);
778 mtspr(SPRN_PMC6, val);
782 mtspr(SPRN_PMC7, val);
785 mtspr(SPRN_PMC8, val);
787 #endif /* CONFIG_PPC64 */
789 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
793 /* Called from sysrq_handle_showregs() */
794 void perf_event_print_debug(void)
796 unsigned long sdar, sier, flags;
797 u32 pmcs[MAX_HWEVENTS];
801 pr_info("Performance monitor hardware not registered.\n");
805 if (!ppmu->n_counter)
808 local_irq_save(flags);
810 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
811 smp_processor_id(), ppmu->name, ppmu->n_counter);
813 for (i = 0; i < ppmu->n_counter; i++)
814 pmcs[i] = read_pmc(i + 1);
816 for (; i < MAX_HWEVENTS; i++)
817 pmcs[i] = 0xdeadbeef;
819 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
820 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
822 if (ppmu->n_counter > 4)
823 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
824 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
826 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
827 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
831 sdar = mfspr(SPRN_SDAR);
833 if (ppmu->flags & PPMU_HAS_SIER)
834 sier = mfspr(SPRN_SIER);
836 if (ppmu->flags & PPMU_ARCH_207S) {
837 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
838 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
839 pr_info("EBBRR: %016lx BESCR: %016lx\n",
840 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
843 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
844 mfspr(SPRN_SIAR), sdar, sier);
846 local_irq_restore(flags);
850 * Check if a set of events can all go on the PMU at once.
851 * If they can't, this will look at alternative codes for the events
852 * and see if any combination of alternative codes is feasible.
853 * The feasible set is returned in event_id[].
855 static int power_check_constraints(struct cpu_hw_events *cpuhw,
856 u64 event_id[], unsigned int cflags[],
859 unsigned long mask, value, nv;
860 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
861 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
863 unsigned long addf = ppmu->add_fields;
864 unsigned long tadd = ppmu->test_adder;
866 if (n_ev > ppmu->n_counter)
869 /* First see if the events will go on as-is */
870 for (i = 0; i < n_ev; ++i) {
871 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
872 && !ppmu->limited_pmc_event(event_id[i])) {
873 ppmu->get_alternatives(event_id[i], cflags[i],
874 cpuhw->alternatives[i]);
875 event_id[i] = cpuhw->alternatives[i][0];
877 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
878 &cpuhw->avalues[i][0]))
882 for (i = 0; i < n_ev; ++i) {
883 nv = (value | cpuhw->avalues[i][0]) +
884 (value & cpuhw->avalues[i][0] & addf);
885 if ((((nv + tadd) ^ value) & mask) != 0 ||
886 (((nv + tadd) ^ cpuhw->avalues[i][0]) &
887 cpuhw->amasks[i][0]) != 0)
890 mask |= cpuhw->amasks[i][0];
893 return 0; /* all OK */
895 /* doesn't work, gather alternatives... */
896 if (!ppmu->get_alternatives)
898 for (i = 0; i < n_ev; ++i) {
900 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
901 cpuhw->alternatives[i]);
902 for (j = 1; j < n_alt[i]; ++j)
903 ppmu->get_constraint(cpuhw->alternatives[i][j],
904 &cpuhw->amasks[i][j],
905 &cpuhw->avalues[i][j]);
908 /* enumerate all possibilities and see if any will work */
911 value = mask = nv = 0;
914 /* we're backtracking, restore context */
920 * See if any alternative k for event_id i,
921 * where k > j, will satisfy the constraints.
923 while (++j < n_alt[i]) {
924 nv = (value | cpuhw->avalues[i][j]) +
925 (value & cpuhw->avalues[i][j] & addf);
926 if ((((nv + tadd) ^ value) & mask) == 0 &&
927 (((nv + tadd) ^ cpuhw->avalues[i][j])
928 & cpuhw->amasks[i][j]) == 0)
933 * No feasible alternative, backtrack
934 * to event_id i-1 and continue enumerating its
935 * alternatives from where we got up to.
941 * Found a feasible alternative for event_id i,
942 * remember where we got up to with this event_id,
943 * go on to the next event_id, and start with
944 * the first alternative for it.
950 mask |= cpuhw->amasks[i][j];
956 /* OK, we have a feasible combination, tell the caller the solution */
957 for (i = 0; i < n_ev; ++i)
958 event_id[i] = cpuhw->alternatives[i][choice[i]];
963 * Check if newly-added events have consistent settings for
964 * exclude_{user,kernel,hv} with each other and any previously
967 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
968 int n_prev, int n_new)
970 int eu = 0, ek = 0, eh = 0;
972 struct perf_event *event;
975 * If the PMU we're on supports per event exclude settings then we
976 * don't need to do any of this logic. NB. This assumes no PMU has both
977 * per event exclude and limited PMCs.
979 if (ppmu->flags & PPMU_ARCH_207S)
987 for (i = 0; i < n; ++i) {
988 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
989 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
994 eu = event->attr.exclude_user;
995 ek = event->attr.exclude_kernel;
996 eh = event->attr.exclude_hv;
998 } else if (event->attr.exclude_user != eu ||
999 event->attr.exclude_kernel != ek ||
1000 event->attr.exclude_hv != eh) {
1006 for (i = 0; i < n; ++i)
1007 if (cflags[i] & PPMU_LIMITED_PMC_OK)
1008 cflags[i] |= PPMU_LIMITED_PMC_REQD;
1013 static u64 check_and_compute_delta(u64 prev, u64 val)
1015 u64 delta = (val - prev) & 0xfffffffful;
1018 * POWER7 can roll back counter values, if the new value is smaller
1019 * than the previous value it will cause the delta and the counter to
1020 * have bogus values unless we rolled a counter over. If a coutner is
1021 * rolled back, it will be smaller, but within 256, which is the maximum
1022 * number of events to rollback at once. If we detect a rollback
1023 * return 0. This can lead to a small lack of precision in the
1026 if (prev > val && (prev - val) < 256)
1032 static void power_pmu_read(struct perf_event *event)
1034 s64 val, delta, prev;
1035 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1037 if (event->hw.state & PERF_HES_STOPPED)
1043 if (is_ebb_event(event)) {
1044 val = read_pmc(event->hw.idx);
1045 if (use_ic(event->attr.config)) {
1046 val = mfspr(SPRN_IC);
1047 if (val > cpuhw->ic_init)
1048 val = val - cpuhw->ic_init;
1050 val = val + (0 - cpuhw->ic_init);
1052 local64_set(&event->hw.prev_count, val);
1057 * Performance monitor interrupts come even when interrupts
1058 * are soft-disabled, as long as interrupts are hard-enabled.
1059 * Therefore we treat them like NMIs.
1062 prev = local64_read(&event->hw.prev_count);
1064 val = read_pmc(event->hw.idx);
1065 if (use_ic(event->attr.config)) {
1066 val = mfspr(SPRN_IC);
1067 if (val > cpuhw->ic_init)
1068 val = val - cpuhw->ic_init;
1070 val = val + (0 - cpuhw->ic_init);
1072 delta = check_and_compute_delta(prev, val);
1075 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1077 local64_add(delta, &event->count);
1080 * A number of places program the PMC with (0x80000000 - period_left).
1081 * We never want period_left to be less than 1 because we will program
1082 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1083 * roll around to 0 before taking an exception. We have seen this
1086 * To fix this, clamp the minimum value of period_left to 1.
1089 prev = local64_read(&event->hw.period_left);
1093 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1097 * On some machines, PMC5 and PMC6 can't be written, don't respect
1098 * the freeze conditions, and don't generate interrupts. This tells
1099 * us if `event' is using such a PMC.
1101 static int is_limited_pmc(int pmcnum)
1103 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1104 && (pmcnum == 5 || pmcnum == 6);
1107 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1108 unsigned long pmc5, unsigned long pmc6)
1110 struct perf_event *event;
1111 u64 val, prev, delta;
1114 for (i = 0; i < cpuhw->n_limited; ++i) {
1115 event = cpuhw->limited_counter[i];
1118 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1119 prev = local64_read(&event->hw.prev_count);
1121 delta = check_and_compute_delta(prev, val);
1123 local64_add(delta, &event->count);
1127 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1128 unsigned long pmc5, unsigned long pmc6)
1130 struct perf_event *event;
1134 for (i = 0; i < cpuhw->n_limited; ++i) {
1135 event = cpuhw->limited_counter[i];
1136 event->hw.idx = cpuhw->limited_hwidx[i];
1137 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1138 prev = local64_read(&event->hw.prev_count);
1139 if (check_and_compute_delta(prev, val))
1140 local64_set(&event->hw.prev_count, val);
1141 perf_event_update_userpage(event);
1146 * Since limited events don't respect the freeze conditions, we
1147 * have to read them immediately after freezing or unfreezing the
1148 * other events. We try to keep the values from the limited
1149 * events as consistent as possible by keeping the delay (in
1150 * cycles and instructions) between freezing/unfreezing and reading
1151 * the limited events as small and consistent as possible.
1152 * Therefore, if any limited events are in use, we read them
1153 * both, and always in the same order, to minimize variability,
1154 * and do it inside the same asm that writes MMCR0.
1156 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1158 unsigned long pmc5, pmc6;
1160 if (!cpuhw->n_limited) {
1161 mtspr(SPRN_MMCR0, mmcr0);
1166 * Write MMCR0, then read PMC5 and PMC6 immediately.
1167 * To ensure we don't get a performance monitor interrupt
1168 * between writing MMCR0 and freezing/thawing the limited
1169 * events, we first write MMCR0 with the event overflow
1170 * interrupt enable bits turned off.
1172 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1173 : "=&r" (pmc5), "=&r" (pmc6)
1174 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1176 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1178 if (mmcr0 & MMCR0_FC)
1179 freeze_limited_counters(cpuhw, pmc5, pmc6);
1181 thaw_limited_counters(cpuhw, pmc5, pmc6);
1184 * Write the full MMCR0 including the event overflow interrupt
1185 * enable bits, if necessary.
1187 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1188 mtspr(SPRN_MMCR0, mmcr0);
1192 * Disable all events to prevent PMU interrupts and to allow
1193 * events to be added or removed.
1195 static void power_pmu_disable(struct pmu *pmu)
1197 struct cpu_hw_events *cpuhw;
1198 unsigned long flags, mmcr0, val;
1202 local_irq_save(flags);
1203 cpuhw = this_cpu_ptr(&cpu_hw_events);
1205 if (!cpuhw->disabled) {
1207 * Check if we ever enabled the PMU on this cpu.
1209 if (!cpuhw->pmcs_enabled) {
1211 cpuhw->pmcs_enabled = 1;
1215 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1217 val = mmcr0 = mfspr(SPRN_MMCR0);
1219 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1223 * The barrier is to make sure the mtspr has been
1224 * executed and the PMU has frozen the events etc.
1227 write_mmcr0(cpuhw, val);
1231 * Disable instruction sampling if it was enabled
1233 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1235 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1239 cpuhw->disabled = 1;
1242 ebb_switch_out(mmcr0);
1245 local_irq_restore(flags);
1249 * Re-enable all events if disable == 0.
1250 * If we were previously disabled and events were added, then
1251 * put the new config on the PMU.
1253 static void power_pmu_enable(struct pmu *pmu)
1255 struct perf_event *event;
1256 struct cpu_hw_events *cpuhw;
1257 unsigned long flags;
1259 unsigned long val, mmcr0;
1261 unsigned int hwc_index[MAX_HWEVENTS];
1268 local_irq_save(flags);
1270 cpuhw = this_cpu_ptr(&cpu_hw_events);
1271 if (!cpuhw->disabled)
1274 if (cpuhw->n_events == 0) {
1275 ppc_set_pmu_inuse(0);
1279 cpuhw->disabled = 0;
1282 * EBB requires an exclusive group and all events must have the EBB
1283 * flag set, or not set, so we can just check a single event. Also we
1284 * know we have at least one event.
1286 ebb = is_ebb_event(cpuhw->event[0]);
1289 * If we didn't change anything, or only removed events,
1290 * no need to recalculate MMCR* settings and reset the PMCs.
1291 * Just reenable the PMU with the current MMCR* settings
1292 * (possibly updated for removal of events).
1294 if (!cpuhw->n_added) {
1295 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1296 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1301 * Clear all MMCR settings and recompute them for the new set of events.
1303 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1305 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1306 cpuhw->mmcr, cpuhw->event)) {
1307 /* shouldn't ever get here */
1308 printk(KERN_ERR "oops compute_mmcr failed\n");
1312 if (!(ppmu->flags & PPMU_ARCH_207S)) {
1314 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1315 * bits for the first event. We have already checked that all
1316 * events have the same value for these bits as the first event.
1318 event = cpuhw->event[0];
1319 if (event->attr.exclude_user)
1320 cpuhw->mmcr[0] |= MMCR0_FCP;
1321 if (event->attr.exclude_kernel)
1322 cpuhw->mmcr[0] |= freeze_events_kernel;
1323 if (event->attr.exclude_hv)
1324 cpuhw->mmcr[0] |= MMCR0_FCHV;
1328 * Write the new configuration to MMCR* with the freeze
1329 * bit set and set the hardware events to their initial values.
1330 * Then unfreeze the events.
1332 ppc_set_pmu_inuse(1);
1333 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1334 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1335 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1337 if (ppmu->flags & PPMU_ARCH_207S)
1338 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
1341 * Read off any pre-existing events that need to move
1344 for (i = 0; i < cpuhw->n_events; ++i) {
1345 event = cpuhw->event[i];
1346 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1347 power_pmu_read(event);
1348 write_pmc(event->hw.idx, 0);
1354 * Initialize the PMCs for all the new and moved events.
1356 cpuhw->n_limited = n_lim = 0;
1357 for (i = 0; i < cpuhw->n_events; ++i) {
1358 event = cpuhw->event[i];
1361 idx = hwc_index[i] + 1;
1362 if (is_limited_pmc(idx)) {
1363 cpuhw->limited_counter[n_lim] = event;
1364 cpuhw->limited_hwidx[n_lim] = idx;
1370 val = local64_read(&event->hw.prev_count);
1373 if (event->hw.sample_period) {
1374 left = local64_read(&event->hw.period_left);
1375 if (left < 0x80000000L)
1376 val = 0x80000000L - left;
1378 local64_set(&event->hw.prev_count, val);
1381 event->hw.idx = idx;
1382 if (event->hw.state & PERF_HES_STOPPED)
1384 write_pmc(idx, val);
1386 perf_event_update_userpage(event);
1388 cpuhw->n_limited = n_lim;
1389 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1392 pmao_restore_workaround(ebb);
1394 mmcr0 = ebb_switch_in(ebb, cpuhw);
1397 if (cpuhw->bhrb_users)
1398 ppmu->config_bhrb(cpuhw->bhrb_filter);
1400 write_mmcr0(cpuhw, mmcr0);
1403 * Enable instruction sampling if necessary
1405 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1407 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1412 local_irq_restore(flags);
1415 static int collect_events(struct perf_event *group, int max_count,
1416 struct perf_event *ctrs[], u64 *events,
1417 unsigned int *flags)
1420 struct perf_event *event;
1422 if (group->pmu->task_ctx_nr == perf_hw_context) {
1426 flags[n] = group->hw.event_base;
1427 events[n++] = group->hw.config;
1429 list_for_each_entry(event, &group->sibling_list, group_entry) {
1430 if (event->pmu->task_ctx_nr == perf_hw_context &&
1431 event->state != PERF_EVENT_STATE_OFF) {
1435 flags[n] = event->hw.event_base;
1436 events[n++] = event->hw.config;
1443 * Add a event to the PMU.
1444 * If all events are not already frozen, then we disable and
1445 * re-enable the PMU in order to get hw_perf_enable to do the
1446 * actual work of reconfiguring the PMU.
1448 static int power_pmu_add(struct perf_event *event, int ef_flags)
1450 struct cpu_hw_events *cpuhw;
1451 unsigned long flags;
1455 local_irq_save(flags);
1456 perf_pmu_disable(event->pmu);
1459 * Add the event to the list (if there is room)
1460 * and check whether the total set is still feasible.
1462 cpuhw = this_cpu_ptr(&cpu_hw_events);
1463 n0 = cpuhw->n_events;
1464 if (n0 >= ppmu->n_counter)
1466 cpuhw->event[n0] = event;
1467 cpuhw->events[n0] = event->hw.config;
1468 cpuhw->flags[n0] = event->hw.event_base;
1471 * This event may have been disabled/stopped in record_and_restart()
1472 * because we exceeded the ->event_limit. If re-starting the event,
1473 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1474 * notification is re-enabled.
1476 if (!(ef_flags & PERF_EF_START))
1477 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1479 event->hw.state = 0;
1482 * If group events scheduling transaction was started,
1483 * skip the schedulability test here, it will be performed
1484 * at commit time(->commit_txn) as a whole
1486 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1489 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1491 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1493 event->hw.config = cpuhw->events[n0];
1496 ebb_event_add(event);
1503 if (has_branch_stack(event)) {
1504 power_pmu_bhrb_enable(event);
1505 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1506 event->attr.branch_sample_type);
1510 * Workaround for POWER9 DD1 to use the Instruction Counter
1511 * register value for instruction counting
1513 if (use_ic(event->attr.config))
1514 cpuhw->ic_init = mfspr(SPRN_IC);
1516 perf_pmu_enable(event->pmu);
1517 local_irq_restore(flags);
1522 * Remove a event from the PMU.
1524 static void power_pmu_del(struct perf_event *event, int ef_flags)
1526 struct cpu_hw_events *cpuhw;
1528 unsigned long flags;
1530 local_irq_save(flags);
1531 perf_pmu_disable(event->pmu);
1533 power_pmu_read(event);
1535 cpuhw = this_cpu_ptr(&cpu_hw_events);
1536 for (i = 0; i < cpuhw->n_events; ++i) {
1537 if (event == cpuhw->event[i]) {
1538 while (++i < cpuhw->n_events) {
1539 cpuhw->event[i-1] = cpuhw->event[i];
1540 cpuhw->events[i-1] = cpuhw->events[i];
1541 cpuhw->flags[i-1] = cpuhw->flags[i];
1544 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1545 if (event->hw.idx) {
1546 write_pmc(event->hw.idx, 0);
1549 perf_event_update_userpage(event);
1553 for (i = 0; i < cpuhw->n_limited; ++i)
1554 if (event == cpuhw->limited_counter[i])
1556 if (i < cpuhw->n_limited) {
1557 while (++i < cpuhw->n_limited) {
1558 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1559 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1563 if (cpuhw->n_events == 0) {
1564 /* disable exceptions if no events are running */
1565 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1568 if (has_branch_stack(event))
1569 power_pmu_bhrb_disable(event);
1571 perf_pmu_enable(event->pmu);
1572 local_irq_restore(flags);
1576 * POWER-PMU does not support disabling individual counters, hence
1577 * program their cycle counter to their max value and ignore the interrupts.
1580 static void power_pmu_start(struct perf_event *event, int ef_flags)
1582 unsigned long flags;
1586 if (!event->hw.idx || !event->hw.sample_period)
1589 if (!(event->hw.state & PERF_HES_STOPPED))
1592 if (ef_flags & PERF_EF_RELOAD)
1593 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1595 local_irq_save(flags);
1596 perf_pmu_disable(event->pmu);
1598 event->hw.state = 0;
1599 left = local64_read(&event->hw.period_left);
1602 if (left < 0x80000000L)
1603 val = 0x80000000L - left;
1605 write_pmc(event->hw.idx, val);
1607 perf_event_update_userpage(event);
1608 perf_pmu_enable(event->pmu);
1609 local_irq_restore(flags);
1612 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1614 unsigned long flags;
1616 if (!event->hw.idx || !event->hw.sample_period)
1619 if (event->hw.state & PERF_HES_STOPPED)
1622 local_irq_save(flags);
1623 perf_pmu_disable(event->pmu);
1625 power_pmu_read(event);
1626 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1627 write_pmc(event->hw.idx, 0);
1629 perf_event_update_userpage(event);
1630 perf_pmu_enable(event->pmu);
1631 local_irq_restore(flags);
1635 * Start group events scheduling transaction
1636 * Set the flag to make pmu::enable() not perform the
1637 * schedulability test, it will be performed at commit time
1639 * We only support PERF_PMU_TXN_ADD transactions. Save the
1640 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1643 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1645 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1647 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1649 cpuhw->txn_flags = txn_flags;
1650 if (txn_flags & ~PERF_PMU_TXN_ADD)
1653 perf_pmu_disable(pmu);
1654 cpuhw->n_txn_start = cpuhw->n_events;
1658 * Stop group events scheduling transaction
1659 * Clear the flag and pmu::enable() will perform the
1660 * schedulability test.
1662 static void power_pmu_cancel_txn(struct pmu *pmu)
1664 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1665 unsigned int txn_flags;
1667 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1669 txn_flags = cpuhw->txn_flags;
1670 cpuhw->txn_flags = 0;
1671 if (txn_flags & ~PERF_PMU_TXN_ADD)
1674 perf_pmu_enable(pmu);
1678 * Commit group events scheduling transaction
1679 * Perform the group schedulability test as a whole
1680 * Return 0 if success
1682 static int power_pmu_commit_txn(struct pmu *pmu)
1684 struct cpu_hw_events *cpuhw;
1690 cpuhw = this_cpu_ptr(&cpu_hw_events);
1691 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1693 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1694 cpuhw->txn_flags = 0;
1698 n = cpuhw->n_events;
1699 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1701 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1705 for (i = cpuhw->n_txn_start; i < n; ++i)
1706 cpuhw->event[i]->hw.config = cpuhw->events[i];
1708 cpuhw->txn_flags = 0;
1709 perf_pmu_enable(pmu);
1714 * Return 1 if we might be able to put event on a limited PMC,
1716 * A event can only go on a limited PMC if it counts something
1717 * that a limited PMC can count, doesn't require interrupts, and
1718 * doesn't exclude any processor mode.
1720 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1724 u64 alt[MAX_EVENT_ALTERNATIVES];
1726 if (event->attr.exclude_user
1727 || event->attr.exclude_kernel
1728 || event->attr.exclude_hv
1729 || event->attr.sample_period)
1732 if (ppmu->limited_pmc_event(ev))
1736 * The requested event_id isn't on a limited PMC already;
1737 * see if any alternative code goes on a limited PMC.
1739 if (!ppmu->get_alternatives)
1742 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1743 n = ppmu->get_alternatives(ev, flags, alt);
1749 * Find an alternative event_id that goes on a normal PMC, if possible,
1750 * and return the event_id code, or 0 if there is no such alternative.
1751 * (Note: event_id code 0 is "don't count" on all machines.)
1753 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1755 u64 alt[MAX_EVENT_ALTERNATIVES];
1758 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1759 n = ppmu->get_alternatives(ev, flags, alt);
1765 /* Number of perf_events counting hardware events */
1766 static atomic_t num_events;
1767 /* Used to avoid races in calling reserve/release_pmc_hardware */
1768 static DEFINE_MUTEX(pmc_reserve_mutex);
1771 * Release the PMU if this is the last perf_event.
1773 static void hw_perf_event_destroy(struct perf_event *event)
1775 if (!atomic_add_unless(&num_events, -1, 1)) {
1776 mutex_lock(&pmc_reserve_mutex);
1777 if (atomic_dec_return(&num_events) == 0)
1778 release_pmc_hardware();
1779 mutex_unlock(&pmc_reserve_mutex);
1784 * Translate a generic cache event_id config to a raw event_id code.
1786 static int hw_perf_cache_event(u64 config, u64 *eventp)
1788 unsigned long type, op, result;
1791 if (!ppmu->cache_events)
1795 type = config & 0xff;
1796 op = (config >> 8) & 0xff;
1797 result = (config >> 16) & 0xff;
1799 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1800 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1801 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1804 ev = (*ppmu->cache_events)[type][op][result];
1813 static int power_pmu_event_init(struct perf_event *event)
1816 unsigned long flags;
1817 struct perf_event *ctrs[MAX_HWEVENTS];
1818 u64 events[MAX_HWEVENTS];
1819 unsigned int cflags[MAX_HWEVENTS];
1822 struct cpu_hw_events *cpuhw;
1827 if (has_branch_stack(event)) {
1828 /* PMU has BHRB enabled */
1829 if (!(ppmu->flags & PPMU_ARCH_207S))
1833 switch (event->attr.type) {
1834 case PERF_TYPE_HARDWARE:
1835 ev = event->attr.config;
1836 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1838 ev = ppmu->generic_events[ev];
1840 case PERF_TYPE_HW_CACHE:
1841 err = hw_perf_cache_event(event->attr.config, &ev);
1846 ev = event->attr.config;
1852 event->hw.config_base = ev;
1856 * If we are not running on a hypervisor, force the
1857 * exclude_hv bit to 0 so that we don't care what
1858 * the user set it to.
1860 if (!firmware_has_feature(FW_FEATURE_LPAR))
1861 event->attr.exclude_hv = 0;
1864 * If this is a per-task event, then we can use
1865 * PM_RUN_* events interchangeably with their non RUN_*
1866 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1867 * XXX we should check if the task is an idle task.
1870 if (event->attach_state & PERF_ATTACH_TASK)
1871 flags |= PPMU_ONLY_COUNT_RUN;
1874 * If this machine has limited events, check whether this
1875 * event_id could go on a limited event.
1877 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1878 if (can_go_on_limited_pmc(event, ev, flags)) {
1879 flags |= PPMU_LIMITED_PMC_OK;
1880 } else if (ppmu->limited_pmc_event(ev)) {
1882 * The requested event_id is on a limited PMC,
1883 * but we can't use a limited PMC; see if any
1884 * alternative goes on a normal PMC.
1886 ev = normal_pmc_alternative(ev, flags);
1892 /* Extra checks for EBB */
1893 err = ebb_event_check(event);
1898 * If this is in a group, check if it can go on with all the
1899 * other hardware events in the group. We assume the event
1900 * hasn't been linked into its leader's sibling list at this point.
1903 if (event->group_leader != event) {
1904 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1905 ctrs, events, cflags);
1912 if (check_excludes(ctrs, cflags, n, 1))
1915 cpuhw = &get_cpu_var(cpu_hw_events);
1916 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1918 if (has_branch_stack(event)) {
1919 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1920 event->attr.branch_sample_type);
1922 if (cpuhw->bhrb_filter == -1) {
1923 put_cpu_var(cpu_hw_events);
1928 put_cpu_var(cpu_hw_events);
1932 event->hw.config = events[n];
1933 event->hw.event_base = cflags[n];
1934 event->hw.last_period = event->hw.sample_period;
1935 local64_set(&event->hw.period_left, event->hw.last_period);
1938 * For EBB events we just context switch the PMC value, we don't do any
1939 * of the sample_period logic. We use hw.prev_count for this.
1941 if (is_ebb_event(event))
1942 local64_set(&event->hw.prev_count, 0);
1945 * See if we need to reserve the PMU.
1946 * If no events are currently in use, then we have to take a
1947 * mutex to ensure that we don't race with another task doing
1948 * reserve_pmc_hardware or release_pmc_hardware.
1951 if (!atomic_inc_not_zero(&num_events)) {
1952 mutex_lock(&pmc_reserve_mutex);
1953 if (atomic_read(&num_events) == 0 &&
1954 reserve_pmc_hardware(perf_event_interrupt))
1957 atomic_inc(&num_events);
1958 mutex_unlock(&pmc_reserve_mutex);
1960 event->destroy = hw_perf_event_destroy;
1965 static int power_pmu_event_idx(struct perf_event *event)
1967 return event->hw.idx;
1970 ssize_t power_events_sysfs_show(struct device *dev,
1971 struct device_attribute *attr, char *page)
1973 struct perf_pmu_events_attr *pmu_attr;
1975 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
1977 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
1980 static struct pmu power_pmu = {
1981 .pmu_enable = power_pmu_enable,
1982 .pmu_disable = power_pmu_disable,
1983 .event_init = power_pmu_event_init,
1984 .add = power_pmu_add,
1985 .del = power_pmu_del,
1986 .start = power_pmu_start,
1987 .stop = power_pmu_stop,
1988 .read = power_pmu_read,
1989 .start_txn = power_pmu_start_txn,
1990 .cancel_txn = power_pmu_cancel_txn,
1991 .commit_txn = power_pmu_commit_txn,
1992 .event_idx = power_pmu_event_idx,
1993 .sched_task = power_pmu_sched_task,
1997 * A counter has overflowed; update its count and record
1998 * things if requested. Note that interrupts are hard-disabled
1999 * here so there is no possibility of being interrupted.
2001 static void record_and_restart(struct perf_event *event, unsigned long val,
2002 struct pt_regs *regs)
2004 u64 period = event->hw.sample_period;
2005 s64 prev, delta, left;
2008 if (event->hw.state & PERF_HES_STOPPED) {
2009 write_pmc(event->hw.idx, 0);
2013 /* we don't have to worry about interrupts here */
2014 prev = local64_read(&event->hw.prev_count);
2015 delta = check_and_compute_delta(prev, val);
2016 local64_add(delta, &event->count);
2019 * See if the total period for this event has expired,
2020 * and update for the next period.
2023 left = local64_read(&event->hw.period_left) - delta;
2031 record = siar_valid(regs);
2032 event->hw.last_period = event->hw.sample_period;
2034 if (left < 0x80000000LL)
2035 val = 0x80000000LL - left;
2038 write_pmc(event->hw.idx, val);
2039 local64_set(&event->hw.prev_count, val);
2040 local64_set(&event->hw.period_left, left);
2041 perf_event_update_userpage(event);
2044 * Finally record data if requested.
2047 struct perf_sample_data data;
2049 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
2051 if (event->attr.sample_type &
2052 (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR))
2053 perf_get_data_addr(regs, &data.addr);
2055 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2056 struct cpu_hw_events *cpuhw;
2057 cpuhw = this_cpu_ptr(&cpu_hw_events);
2058 power_pmu_bhrb_read(cpuhw);
2059 data.br_stack = &cpuhw->bhrb_stack;
2062 if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
2063 ppmu->get_mem_data_src)
2064 ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
2066 if (event->attr.sample_type & PERF_SAMPLE_WEIGHT &&
2067 ppmu->get_mem_weight)
2068 ppmu->get_mem_weight(&data.weight);
2070 if (perf_event_overflow(event, &data, regs))
2071 power_pmu_stop(event, 0);
2076 * Called from generic code to get the misc flags (i.e. processor mode)
2079 unsigned long perf_misc_flags(struct pt_regs *regs)
2081 u32 flags = perf_get_misc_flags(regs);
2085 return user_mode(regs) ? PERF_RECORD_MISC_USER :
2086 PERF_RECORD_MISC_KERNEL;
2090 * Called from generic code to get the instruction pointer
2093 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2095 bool use_siar = regs_use_siar(regs);
2097 if (use_siar && siar_valid(regs))
2098 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
2100 return 0; // no valid instruction pointer
2105 static bool pmc_overflow_power7(unsigned long val)
2108 * Events on POWER7 can roll back if a speculative event doesn't
2109 * eventually complete. Unfortunately in some rare cases they will
2110 * raise a performance monitor exception. We need to catch this to
2111 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2112 * cycles from overflow.
2114 * We only do this if the first pass fails to find any overflowing
2115 * PMCs because a user might set a period of less than 256 and we
2116 * don't want to mistakenly reset them.
2118 if ((0x80000000 - val) <= 256)
2124 static bool pmc_overflow(unsigned long val)
2133 * Performance monitor interrupt stuff
2135 static void perf_event_interrupt(struct pt_regs *regs)
2138 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2139 struct perf_event *event;
2140 unsigned long val[8];
2144 if (cpuhw->n_limited)
2145 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2148 perf_read_regs(regs);
2150 nmi = perf_intr_is_nmi(regs);
2156 /* Read all the PMCs since we'll need them a bunch of times */
2157 for (i = 0; i < ppmu->n_counter; ++i)
2158 val[i] = read_pmc(i + 1);
2160 /* Try to find what caused the IRQ */
2162 for (i = 0; i < ppmu->n_counter; ++i) {
2163 if (!pmc_overflow(val[i]))
2165 if (is_limited_pmc(i + 1))
2166 continue; /* these won't generate IRQs */
2168 * We've found one that's overflowed. For active
2169 * counters we need to log this. For inactive
2170 * counters, we need to reset it anyway
2174 for (j = 0; j < cpuhw->n_events; ++j) {
2175 event = cpuhw->event[j];
2176 if (event->hw.idx == (i + 1)) {
2178 record_and_restart(event, val[i], regs);
2183 /* reset non active counters that have overflowed */
2184 write_pmc(i + 1, 0);
2186 if (!found && pvr_version_is(PVR_POWER7)) {
2187 /* check active counters for special buggy p7 overflow */
2188 for (i = 0; i < cpuhw->n_events; ++i) {
2189 event = cpuhw->event[i];
2190 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2192 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2193 /* event has overflowed in a buggy way*/
2195 record_and_restart(event,
2196 val[event->hw.idx - 1],
2201 if (!found && !nmi && printk_ratelimit())
2202 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2205 * Reset MMCR0 to its normal value. This will set PMXE and
2206 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2207 * and thus allow interrupts to occur again.
2208 * XXX might want to use MSR.PM to keep the events frozen until
2209 * we get back out of this interrupt.
2211 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2219 static int power_pmu_prepare_cpu(unsigned int cpu)
2221 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2224 memset(cpuhw, 0, sizeof(*cpuhw));
2225 cpuhw->mmcr[0] = MMCR0_FC;
2230 int register_power_pmu(struct power_pmu *pmu)
2233 return -EBUSY; /* something's already registered */
2236 pr_info("%s performance monitor hardware support registered\n",
2239 power_pmu.attr_groups = ppmu->attr_groups;
2243 * Use FCHV to ignore kernel events if MSR.HV is set.
2245 if (mfmsr() & MSR_HV)
2246 freeze_events_kernel = MMCR0_FCHV;
2247 #endif /* CONFIG_PPC64 */
2249 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2250 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
2251 power_pmu_prepare_cpu, NULL);