2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/lmb.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
58 #define DBG(fmt...) udbg_printf(fmt)
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
66 #define DBG_LOW(fmt...)
74 * Note: pte --> Linux PTE
75 * HPTE --> PowerPC Hashed Page Table Entry
78 * htab_initialize is called with the MMU off (of course), but
79 * the kernel has been copied down to zero so it can directly
80 * reference global data. At this point it is very difficult
81 * to print debug info.
86 extern unsigned long dart_tablebase;
87 #endif /* CONFIG_U3_DART */
89 static unsigned long _SDR1;
90 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
92 struct hash_pte *htab_address;
93 unsigned long htab_size_bytes;
94 unsigned long htab_hash_mask;
95 int mmu_linear_psize = MMU_PAGE_4K;
96 int mmu_virtual_psize = MMU_PAGE_4K;
97 int mmu_vmalloc_psize = MMU_PAGE_4K;
98 #ifdef CONFIG_SPARSEMEM_VMEMMAP
99 int mmu_vmemmap_psize = MMU_PAGE_4K;
101 int mmu_io_psize = MMU_PAGE_4K;
102 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
103 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
104 u16 mmu_slb_size = 64;
105 #ifdef CONFIG_HUGETLB_PAGE
106 int mmu_huge_psize = MMU_PAGE_16M;
107 unsigned int HPAGE_SHIFT;
109 #ifdef CONFIG_PPC_64K_PAGES
110 int mmu_ci_restrictions;
112 #ifdef CONFIG_DEBUG_PAGEALLOC
113 static u8 *linear_map_hash_slots;
114 static unsigned long linear_map_hash_count;
115 static DEFINE_SPINLOCK(linear_map_hash_lock);
116 #endif /* CONFIG_DEBUG_PAGEALLOC */
118 /* There are definitions of page sizes arrays to be used when none
119 * is provided by the firmware.
122 /* Pre-POWER4 CPUs (4k pages only)
124 static struct mmu_psize_def mmu_psize_defaults_old[] = {
134 /* POWER4, GPUL, POWER5
136 * Support for 16Mb large pages
138 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
156 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
157 unsigned long pstart, unsigned long mode,
158 int psize, int ssize)
160 unsigned long vaddr, paddr;
161 unsigned int step, shift;
162 unsigned long tmp_mode;
165 shift = mmu_psize_defs[psize].shift;
168 for (vaddr = vstart, paddr = pstart; vaddr < vend;
169 vaddr += step, paddr += step) {
170 unsigned long hash, hpteg;
171 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
172 unsigned long va = hpt_va(vaddr, vsid, ssize);
176 /* Make non-kernel text non-executable */
177 if (!in_kernel_text(vaddr))
178 tmp_mode = mode | HPTE_R_N;
180 hash = hpt_hash(va, shift, ssize);
181 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
183 DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
185 BUG_ON(!ppc_md.hpte_insert);
186 ret = ppc_md.hpte_insert(hpteg, va, paddr,
187 tmp_mode, HPTE_V_BOLTED, psize, ssize);
191 #ifdef CONFIG_DEBUG_PAGEALLOC
192 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
193 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
194 #endif /* CONFIG_DEBUG_PAGEALLOC */
196 return ret < 0 ? ret : 0;
199 #ifdef CONFIG_MEMORY_HOTPLUG
200 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
201 int psize, int ssize)
204 unsigned int step, shift;
206 shift = mmu_psize_defs[psize].shift;
209 if (!ppc_md.hpte_removebolted) {
210 printk(KERN_WARNING "Platform doesn't implement "
211 "hpte_removebolted\n");
215 for (vaddr = vstart; vaddr < vend; vaddr += step)
216 ppc_md.hpte_removebolted(vaddr, psize, ssize);
220 #endif /* CONFIG_MEMORY_HOTPLUG */
222 static int __init htab_dt_scan_seg_sizes(unsigned long node,
223 const char *uname, int depth,
226 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
228 unsigned long size = 0;
230 /* We are scanning "cpu" nodes only */
231 if (type == NULL || strcmp(type, "cpu") != 0)
234 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
238 for (; size >= 4; size -= 4, ++prop) {
240 DBG("1T segment support detected\n");
241 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
245 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
249 static void __init htab_init_seg_sizes(void)
251 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
254 static int __init htab_dt_scan_page_sizes(unsigned long node,
255 const char *uname, int depth,
258 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
260 unsigned long size = 0;
262 /* We are scanning "cpu" nodes only */
263 if (type == NULL || strcmp(type, "cpu") != 0)
266 prop = (u32 *)of_get_flat_dt_prop(node,
267 "ibm,segment-page-sizes", &size);
269 DBG("Page sizes from device-tree:\n");
271 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
273 unsigned int shift = prop[0];
274 unsigned int slbenc = prop[1];
275 unsigned int lpnum = prop[2];
276 unsigned int lpenc = 0;
277 struct mmu_psize_def *def;
280 size -= 3; prop += 3;
281 while(size > 0 && lpnum) {
282 if (prop[0] == shift)
284 prop += 2; size -= 2;
299 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
307 def = &mmu_psize_defs[idx];
312 def->avpnm = (1 << (shift - 23)) - 1;
315 /* We don't know for sure what's up with tlbiel, so
316 * for now we only set it for 4K and 64K pages
318 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
323 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
324 "tlbiel=%d, penc=%d\n",
325 idx, shift, def->sllp, def->avpnm, def->tlbiel,
333 /* Scan for 16G memory blocks that have been set aside for huge pages
334 * and reserve those blocks for 16G huge pages.
336 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
337 const char *uname, int depth,
339 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
340 unsigned long *addr_prop;
341 u32 *page_count_prop;
342 unsigned int expected_pages;
343 long unsigned int phys_addr;
344 long unsigned int block_size;
346 /* We are scanning "memory" nodes only */
347 if (type == NULL || strcmp(type, "memory") != 0)
350 /* This property is the log base 2 of the number of virtual pages that
351 * will represent this memory block. */
352 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
353 if (page_count_prop == NULL)
355 expected_pages = (1 << page_count_prop[0]);
356 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
357 if (addr_prop == NULL)
359 phys_addr = addr_prop[0];
360 block_size = addr_prop[1];
361 if (block_size != (16 * GB))
363 printk(KERN_INFO "Huge page(16GB) memory: "
364 "addr = 0x%lX size = 0x%lX pages = %d\n",
365 phys_addr, block_size, expected_pages);
366 lmb_reserve(phys_addr, block_size * expected_pages);
367 add_gpage(phys_addr, block_size, expected_pages);
371 static void __init htab_init_page_sizes(void)
375 /* Default to 4K pages only */
376 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
377 sizeof(mmu_psize_defaults_old));
380 * Try to find the available page sizes in the device-tree
382 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
383 if (rc != 0) /* Found */
387 * Not in the device-tree, let's fallback on known size
388 * list for 16M capable GP & GR
390 if (cpu_has_feature(CPU_FTR_16M_PAGE))
391 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
392 sizeof(mmu_psize_defaults_gp));
394 #ifndef CONFIG_DEBUG_PAGEALLOC
396 * Pick a size for the linear mapping. Currently, we only support
397 * 16M, 1M and 4K which is the default
399 if (mmu_psize_defs[MMU_PAGE_16M].shift)
400 mmu_linear_psize = MMU_PAGE_16M;
401 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
402 mmu_linear_psize = MMU_PAGE_1M;
403 #endif /* CONFIG_DEBUG_PAGEALLOC */
405 #ifdef CONFIG_PPC_64K_PAGES
407 * Pick a size for the ordinary pages. Default is 4K, we support
408 * 64K for user mappings and vmalloc if supported by the processor.
409 * We only use 64k for ioremap if the processor
410 * (and firmware) support cache-inhibited large pages.
411 * If not, we use 4k and set mmu_ci_restrictions so that
412 * hash_page knows to switch processes that use cache-inhibited
413 * mappings to 4k pages.
415 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
416 mmu_virtual_psize = MMU_PAGE_64K;
417 mmu_vmalloc_psize = MMU_PAGE_64K;
418 if (mmu_linear_psize == MMU_PAGE_4K)
419 mmu_linear_psize = MMU_PAGE_64K;
420 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
422 * Don't use 64k pages for ioremap on pSeries, since
423 * that would stop us accessing the HEA ethernet.
425 if (!machine_is(pseries))
426 mmu_io_psize = MMU_PAGE_64K;
428 mmu_ci_restrictions = 1;
430 #endif /* CONFIG_PPC_64K_PAGES */
432 #ifdef CONFIG_SPARSEMEM_VMEMMAP
433 /* We try to use 16M pages for vmemmap if that is supported
434 * and we have at least 1G of RAM at boot
436 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
437 lmb_phys_mem_size() >= 0x40000000)
438 mmu_vmemmap_psize = MMU_PAGE_16M;
439 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
440 mmu_vmemmap_psize = MMU_PAGE_64K;
442 mmu_vmemmap_psize = MMU_PAGE_4K;
443 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
445 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
446 "virtual = %d, io = %d"
447 #ifdef CONFIG_SPARSEMEM_VMEMMAP
451 mmu_psize_defs[mmu_linear_psize].shift,
452 mmu_psize_defs[mmu_virtual_psize].shift,
453 mmu_psize_defs[mmu_io_psize].shift
454 #ifdef CONFIG_SPARSEMEM_VMEMMAP
455 ,mmu_psize_defs[mmu_vmemmap_psize].shift
459 #ifdef CONFIG_HUGETLB_PAGE
460 /* Reserve 16G huge page memory sections for huge pages */
461 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
463 /* Init large page size. Currently, we pick 16M or 1M depending
464 * on what is available
466 if (mmu_psize_defs[MMU_PAGE_16M].shift)
467 set_huge_psize(MMU_PAGE_16M);
468 /* With 4k/4level pagetables, we can't (for now) cope with a
469 * huge page size < PMD_SIZE */
470 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
471 set_huge_psize(MMU_PAGE_1M);
472 #endif /* CONFIG_HUGETLB_PAGE */
475 static int __init htab_dt_scan_pftsize(unsigned long node,
476 const char *uname, int depth,
479 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
482 /* We are scanning "cpu" nodes only */
483 if (type == NULL || strcmp(type, "cpu") != 0)
486 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
488 /* pft_size[0] is the NUMA CEC cookie */
489 ppc64_pft_size = prop[1];
495 static unsigned long __init htab_get_table_size(void)
497 unsigned long mem_size, rnd_mem_size, pteg_count;
499 /* If hash size isn't already provided by the platform, we try to
500 * retrieve it from the device-tree. If it's not there neither, we
501 * calculate it now based on the total RAM size
503 if (ppc64_pft_size == 0)
504 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
506 return 1UL << ppc64_pft_size;
508 /* round mem_size up to next power of 2 */
509 mem_size = lmb_phys_mem_size();
510 rnd_mem_size = 1UL << __ilog2(mem_size);
511 if (rnd_mem_size < mem_size)
515 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
517 return pteg_count << 7;
520 #ifdef CONFIG_MEMORY_HOTPLUG
521 void create_section_mapping(unsigned long start, unsigned long end)
523 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
524 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
525 mmu_linear_psize, mmu_kernel_ssize));
528 int remove_section_mapping(unsigned long start, unsigned long end)
530 return htab_remove_mapping(start, end, mmu_linear_psize,
533 #endif /* CONFIG_MEMORY_HOTPLUG */
535 static inline void make_bl(unsigned int *insn_addr, void *func)
537 unsigned long funcp = *((unsigned long *)func);
538 int offset = funcp - (unsigned long)insn_addr;
540 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
541 flush_icache_range((unsigned long)insn_addr, 4+
542 (unsigned long)insn_addr);
545 static void __init htab_finish_init(void)
547 extern unsigned int *htab_call_hpte_insert1;
548 extern unsigned int *htab_call_hpte_insert2;
549 extern unsigned int *htab_call_hpte_remove;
550 extern unsigned int *htab_call_hpte_updatepp;
552 #ifdef CONFIG_PPC_HAS_HASH_64K
553 extern unsigned int *ht64_call_hpte_insert1;
554 extern unsigned int *ht64_call_hpte_insert2;
555 extern unsigned int *ht64_call_hpte_remove;
556 extern unsigned int *ht64_call_hpte_updatepp;
558 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
559 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
560 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
561 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
562 #endif /* CONFIG_PPC_HAS_HASH_64K */
564 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
565 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
566 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
567 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
570 void __init htab_initialize(void)
573 unsigned long pteg_count;
574 unsigned long mode_rw;
575 unsigned long base = 0, size = 0, limit;
578 DBG(" -> htab_initialize()\n");
580 /* Initialize segment sizes */
581 htab_init_seg_sizes();
583 /* Initialize page sizes */
584 htab_init_page_sizes();
586 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
587 mmu_kernel_ssize = MMU_SEGSIZE_1T;
588 mmu_highuser_ssize = MMU_SEGSIZE_1T;
589 printk(KERN_INFO "Using 1TB segments\n");
593 * Calculate the required size of the htab. We want the number of
594 * PTEGs to equal one half the number of real pages.
596 htab_size_bytes = htab_get_table_size();
597 pteg_count = htab_size_bytes >> 7;
599 htab_hash_mask = pteg_count - 1;
601 if (firmware_has_feature(FW_FEATURE_LPAR)) {
602 /* Using a hypervisor which owns the htab */
606 /* Find storage for the HPT. Must be contiguous in
607 * the absolute address space. On cell we want it to be
608 * in the first 2 Gig so we can use it for IOMMU hacks.
610 if (machine_is(cell))
615 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
617 DBG("Hash table allocated at %lx, size: %lx\n", table,
620 htab_address = abs_to_virt(table);
622 /* htab absolute addr + encoded htabsize */
623 _SDR1 = table + __ilog2(pteg_count) - 11;
625 /* Initialize the HPT with no entries */
626 memset((void *)table, 0, htab_size_bytes);
629 mtspr(SPRN_SDR1, _SDR1);
632 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
634 #ifdef CONFIG_DEBUG_PAGEALLOC
635 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
636 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
638 memset(linear_map_hash_slots, 0, linear_map_hash_count);
639 #endif /* CONFIG_DEBUG_PAGEALLOC */
641 /* On U3 based machines, we need to reserve the DART area and
642 * _NOT_ map it to avoid cache paradoxes as it's remapped non
646 /* create bolted the linear mapping in the hash table */
647 for (i=0; i < lmb.memory.cnt; i++) {
648 base = (unsigned long)__va(lmb.memory.region[i].base);
649 size = lmb.memory.region[i].size;
651 DBG("creating mapping for region: %lx : %lx\n", base, size);
653 #ifdef CONFIG_U3_DART
654 /* Do not map the DART space. Fortunately, it will be aligned
655 * in such a way that it will not cross two lmb regions and
656 * will fit within a single 16Mb page.
657 * The DART space is assumed to be a full 16Mb region even if
658 * we only use 2Mb of that space. We will use more of it later
659 * for AGP GART. We have to use a full 16Mb large page.
661 DBG("DART base: %lx\n", dart_tablebase);
663 if (dart_tablebase != 0 && dart_tablebase >= base
664 && dart_tablebase < (base + size)) {
665 unsigned long dart_table_end = dart_tablebase + 16 * MB;
666 if (base != dart_tablebase)
667 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
671 if ((base + size) > dart_table_end)
672 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
674 __pa(dart_table_end),
680 #endif /* CONFIG_U3_DART */
681 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
682 mode_rw, mmu_linear_psize, mmu_kernel_ssize));
686 * If we have a memory_limit and we've allocated TCEs then we need to
687 * explicitly map the TCE area at the top of RAM. We also cope with the
688 * case that the TCEs start below memory_limit.
689 * tce_alloc_start/end are 16MB aligned so the mapping should work
690 * for either 4K or 16MB pages.
692 if (tce_alloc_start) {
693 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
694 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
696 if (base + size >= tce_alloc_start)
697 tce_alloc_start = base + size + 1;
699 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
700 __pa(tce_alloc_start), mode_rw,
701 mmu_linear_psize, mmu_kernel_ssize));
706 DBG(" <- htab_initialize()\n");
711 void htab_initialize_secondary(void)
713 if (!firmware_has_feature(FW_FEATURE_LPAR))
714 mtspr(SPRN_SDR1, _SDR1);
718 * Called by asm hashtable.S for doing lazy icache flush
720 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
724 if (!pfn_valid(pte_pfn(pte)))
727 page = pte_page(pte);
730 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
732 __flush_dcache_icache(page_address(page));
733 set_bit(PG_arch_1, &page->flags);
740 #ifdef CONFIG_PPC_MM_SLICES
741 unsigned int get_paca_psize(unsigned long addr)
743 unsigned long index, slices;
745 if (addr < SLICE_LOW_TOP) {
746 slices = get_paca()->context.low_slices_psize;
747 index = GET_LOW_SLICE_INDEX(addr);
749 slices = get_paca()->context.high_slices_psize;
750 index = GET_HIGH_SLICE_INDEX(addr);
752 return (slices >> (index * 4)) & 0xF;
756 unsigned int get_paca_psize(unsigned long addr)
758 return get_paca()->context.user_psize;
763 * Demote a segment to using 4k pages.
764 * For now this makes the whole process use 4k pages.
766 #ifdef CONFIG_PPC_64K_PAGES
767 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
769 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
771 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
772 #ifdef CONFIG_SPU_BASE
773 spu_flush_all_slbs(mm);
775 if (get_paca_psize(addr) != MMU_PAGE_4K) {
776 get_paca()->context = mm->context;
777 slb_flush_and_rebolt();
780 #endif /* CONFIG_PPC_64K_PAGES */
782 #ifdef CONFIG_PPC_SUBPAGE_PROT
784 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
785 * Userspace sets the subpage permissions using the subpage_prot system call.
787 * Result is 0: full permissions, _PAGE_RW: read-only,
788 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
790 static int subpage_protection(pgd_t *pgdir, unsigned long ea)
792 struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
796 if (ea >= spt->maxaddr)
798 if (ea < 0x100000000) {
799 /* addresses below 4GB use spt->low_prot */
800 sbpm = spt->low_prot;
802 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
806 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
809 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
811 /* extract 2-bit bitfield for this 4k subpage */
812 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
814 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
815 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
819 #else /* CONFIG_PPC_SUBPAGE_PROT */
820 static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
828 * 1 - normal page fault
829 * -1 - critical hash insertion error
830 * -2 - access not permitted by subpage protection mechanism
832 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
836 struct mm_struct *mm;
839 int rc, user_region = 0, local = 0;
842 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
845 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
846 DBG_LOW(" out of pgtable range !\n");
850 /* Get region & vsid */
851 switch (REGION_ID(ea)) {
856 DBG_LOW(" user region with no mm !\n");
859 psize = get_slice_psize(mm, ea);
860 ssize = user_segment_size(ea);
861 vsid = get_vsid(mm->context.id, ea, ssize);
863 case VMALLOC_REGION_ID:
865 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
866 if (ea < VMALLOC_END)
867 psize = mmu_vmalloc_psize;
869 psize = mmu_io_psize;
870 ssize = mmu_kernel_ssize;
874 * Send the problem up to do_page_fault
878 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
885 /* Check CPU locality */
886 tmp = cpumask_of_cpu(smp_processor_id());
887 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
890 #ifdef CONFIG_HUGETLB_PAGE
891 /* Handle hugepage regions */
892 if (HPAGE_SHIFT && psize == mmu_huge_psize) {
893 DBG_LOW(" -> huge page !\n");
894 return hash_huge_page(mm, access, ea, vsid, local, trap);
896 #endif /* CONFIG_HUGETLB_PAGE */
898 #ifndef CONFIG_PPC_64K_PAGES
899 /* If we use 4K pages and our psize is not 4K, then we are hitting
900 * a special driver mapping, we need to align the address before
903 if (psize != MMU_PAGE_4K)
904 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
905 #endif /* CONFIG_PPC_64K_PAGES */
907 /* Get PTE and page size from page tables */
908 ptep = find_linux_pte(pgdir, ea);
909 if (ptep == NULL || !pte_present(*ptep)) {
910 DBG_LOW(" no PTE !\n");
914 #ifndef CONFIG_PPC_64K_PAGES
915 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
917 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
918 pte_val(*(ptep + PTRS_PER_PTE)));
920 /* Pre-check access permissions (will be re-checked atomically
921 * in __hash_page_XX but this pre-check is a fast path
923 if (access & ~pte_val(*ptep)) {
924 DBG_LOW(" no access !\n");
928 /* Do actual hashing */
929 #ifdef CONFIG_PPC_64K_PAGES
930 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
931 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
932 demote_segment_4k(mm, ea);
936 /* If this PTE is non-cacheable and we have restrictions on
937 * using non cacheable large pages, then we switch to 4k
939 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
940 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
942 demote_segment_4k(mm, ea);
944 } else if (ea < VMALLOC_END) {
946 * some driver did a non-cacheable mapping
947 * in vmalloc space, so switch vmalloc
950 printk(KERN_ALERT "Reducing vmalloc segment "
951 "to 4kB pages because of "
952 "non-cacheable mapping\n");
953 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
954 #ifdef CONFIG_SPU_BASE
955 spu_flush_all_slbs(mm);
960 if (psize != get_paca_psize(ea)) {
961 get_paca()->context = mm->context;
962 slb_flush_and_rebolt();
964 } else if (get_paca()->vmalloc_sllp !=
965 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
966 get_paca()->vmalloc_sllp =
967 mmu_psize_defs[mmu_vmalloc_psize].sllp;
968 slb_vmalloc_update();
970 #endif /* CONFIG_PPC_64K_PAGES */
972 #ifdef CONFIG_PPC_HAS_HASH_64K
973 if (psize == MMU_PAGE_64K)
974 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
976 #endif /* CONFIG_PPC_HAS_HASH_64K */
978 int spp = subpage_protection(pgdir, ea);
982 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
986 #ifndef CONFIG_PPC_64K_PAGES
987 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
989 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
990 pte_val(*(ptep + PTRS_PER_PTE)));
992 DBG_LOW(" -> rc=%d\n", rc);
995 EXPORT_SYMBOL_GPL(hash_page);
997 void hash_preload(struct mm_struct *mm, unsigned long ea,
998 unsigned long access, unsigned long trap)
1004 unsigned long flags;
1008 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1010 #ifdef CONFIG_PPC_MM_SLICES
1011 /* We only prefault standard pages for now */
1012 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1016 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1017 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1019 /* Get Linux PTE if available */
1023 ptep = find_linux_pte(pgdir, ea);
1027 #ifdef CONFIG_PPC_64K_PAGES
1028 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1029 * a 64K kernel), then we don't preload, hash_page() will take
1030 * care of it once we actually try to access the page.
1031 * That way we don't have to duplicate all of the logic for segment
1032 * page size demotion here
1034 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1036 #endif /* CONFIG_PPC_64K_PAGES */
1039 ssize = user_segment_size(ea);
1040 vsid = get_vsid(mm->context.id, ea, ssize);
1042 /* Hash doesn't like irqs */
1043 local_irq_save(flags);
1045 /* Is that local to this CPU ? */
1046 mask = cpumask_of_cpu(smp_processor_id());
1047 if (cpus_equal(mm->cpu_vm_mask, mask))
1051 #ifdef CONFIG_PPC_HAS_HASH_64K
1052 if (mm->context.user_psize == MMU_PAGE_64K)
1053 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1055 #endif /* CONFIG_PPC_HAS_HASH_64K */
1056 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1057 subpage_protection(pgdir, ea));
1059 local_irq_restore(flags);
1062 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1063 * do not forget to update the assembly call site !
1065 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1068 unsigned long hash, index, shift, hidx, slot;
1070 DBG_LOW("flush_hash_page(va=%016x)\n", va);
1071 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1072 hash = hpt_hash(va, shift, ssize);
1073 hidx = __rpte_to_hidx(pte, index);
1074 if (hidx & _PTEIDX_SECONDARY)
1076 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1077 slot += hidx & _PTEIDX_GROUP_IX;
1078 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
1079 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1080 } pte_iterate_hashed_end();
1083 void flush_hash_range(unsigned long number, int local)
1085 if (ppc_md.flush_hash_range)
1086 ppc_md.flush_hash_range(number, local);
1089 struct ppc64_tlb_batch *batch =
1090 &__get_cpu_var(ppc64_tlb_batch);
1092 for (i = 0; i < number; i++)
1093 flush_hash_page(batch->vaddr[i], batch->pte[i],
1094 batch->psize, batch->ssize, local);
1099 * low_hash_fault is called when we the low level hash code failed
1100 * to instert a PTE due to an hypervisor error
1102 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1104 if (user_mode(regs)) {
1105 #ifdef CONFIG_PPC_SUBPAGE_PROT
1107 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1110 _exception(SIGBUS, regs, BUS_ADRERR, address);
1112 bad_page_fault(regs, address, SIGBUS);
1115 #ifdef CONFIG_DEBUG_PAGEALLOC
1116 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1118 unsigned long hash, hpteg;
1119 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1120 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1121 unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY |
1122 _PAGE_COHERENT | PP_RWXX | HPTE_R_N;
1125 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1126 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1128 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1129 mode, HPTE_V_BOLTED,
1130 mmu_linear_psize, mmu_kernel_ssize);
1132 spin_lock(&linear_map_hash_lock);
1133 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1134 linear_map_hash_slots[lmi] = ret | 0x80;
1135 spin_unlock(&linear_map_hash_lock);
1138 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1140 unsigned long hash, hidx, slot;
1141 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1142 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1144 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1145 spin_lock(&linear_map_hash_lock);
1146 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1147 hidx = linear_map_hash_slots[lmi] & 0x7f;
1148 linear_map_hash_slots[lmi] = 0;
1149 spin_unlock(&linear_map_hash_lock);
1150 if (hidx & _PTEIDX_SECONDARY)
1152 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1153 slot += hidx & _PTEIDX_GROUP_IX;
1154 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1157 void kernel_map_pages(struct page *page, int numpages, int enable)
1159 unsigned long flags, vaddr, lmi;
1162 local_irq_save(flags);
1163 for (i = 0; i < numpages; i++, page++) {
1164 vaddr = (unsigned long)page_address(page);
1165 lmi = __pa(vaddr) >> PAGE_SHIFT;
1166 if (lmi >= linear_map_hash_count)
1169 kernel_map_linear_page(vaddr, lmi);
1171 kernel_unmap_linear_page(vaddr, lmi);
1173 local_irq_restore(flags);
1175 #endif /* CONFIG_DEBUG_PAGEALLOC */