2 * native hashtable management.
4 * SMP scalability work:
5 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
18 #include <linux/threads.h>
19 #include <linux/smp.h>
21 #include <asm/machdep.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
25 #include <asm/tlbflush.h>
27 #include <asm/cputable.h>
29 #include <asm/kexec.h>
30 #include <asm/ppc-opcode.h>
32 #include <misc/cxl-base.h>
35 #define DBG_LOW(fmt...) udbg_printf(fmt)
37 #define DBG_LOW(fmt...)
41 #define HPTE_LOCK_BIT 3
43 #define HPTE_LOCK_BIT (56+3)
46 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
48 static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
55 * We need 14 to 65 bits of va for a tlibe of 4K page
56 * With vpn we ignore the lower VPN_SHIFT bits already.
57 * And top two bits are already ignored because we can
58 * only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT
61 va = vpn << VPN_SHIFT;
63 * clear top 16 bits of 64bit va, non SLS segment
64 * Older versions of the architecture (2.02 and earler) require the
65 * masking of the top 16 bits.
67 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
68 va &= ~(0xffffULL << 48);
72 /* clear out bits after (52) [0....52.....63] */
73 va &= ~((1ul << (64 - 52)) - 1);
75 sllp = get_sllp_encoding(apsize);
77 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
78 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
82 /* We need 14 to 14 + i bits of va */
83 penc = mmu_psize_defs[psize].penc[apsize];
84 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
89 * We don't need all the bits, but rest of the bits
90 * must be ignored by the processor.
91 * vpn cover upto 65 bits of va. (0...65) and we need
94 va |= (vpn & 0xfe); /* AVAL */
96 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
97 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
103 static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
109 /* VPN_SHIFT can be atmost 12 */
110 va = vpn << VPN_SHIFT;
112 * clear top 16 bits of 64 bit va, non SLS segment
113 * Older versions of the architecture (2.02 and earler) require the
114 * masking of the top 16 bits.
116 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
117 va &= ~(0xffffULL << 48);
121 /* clear out bits after(52) [0....52.....63] */
122 va &= ~((1ul << (64 - 52)) - 1);
124 sllp = get_sllp_encoding(apsize);
126 asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,0", %1)
127 : : "r" (va), "i" (CPU_FTR_ARCH_206)
131 /* We need 14 to 14 + i bits of va */
132 penc = mmu_psize_defs[psize].penc[apsize];
133 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
138 * We don't need all the bits, but rest of the bits
139 * must be ignored by the processor.
140 * vpn cover upto 65 bits of va. (0...65) and we need
145 asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,1", %1)
146 : : "r" (va), "i" (CPU_FTR_ARCH_206)
153 static inline void tlbie(unsigned long vpn, int psize, int apsize,
154 int ssize, int local)
156 unsigned int use_local;
157 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
159 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use();
162 use_local = mmu_psize_defs[psize].tlbiel;
163 if (lock_tlbie && !use_local)
164 raw_spin_lock(&native_tlbie_lock);
165 asm volatile("ptesync": : :"memory");
167 __tlbiel(vpn, psize, apsize, ssize);
168 asm volatile("ptesync": : :"memory");
170 __tlbie(vpn, psize, apsize, ssize);
171 asm volatile("eieio; tlbsync; ptesync": : :"memory");
173 if (lock_tlbie && !use_local)
174 raw_spin_unlock(&native_tlbie_lock);
177 static inline void native_lock_hpte(struct hash_pte *hptep)
179 unsigned long *word = (unsigned long *)&hptep->v;
182 if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
184 while(test_bit(HPTE_LOCK_BIT, word))
189 static inline void native_unlock_hpte(struct hash_pte *hptep)
191 unsigned long *word = (unsigned long *)&hptep->v;
193 clear_bit_unlock(HPTE_LOCK_BIT, word);
196 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
197 unsigned long pa, unsigned long rflags,
198 unsigned long vflags, int psize, int apsize, int ssize)
200 struct hash_pte *hptep = htab_address + hpte_group;
201 unsigned long hpte_v, hpte_r;
204 if (!(vflags & HPTE_V_BOLTED)) {
205 DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
206 " rflags=%lx, vflags=%lx, psize=%d)\n",
207 hpte_group, vpn, pa, rflags, vflags, psize);
210 for (i = 0; i < HPTES_PER_GROUP; i++) {
211 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) {
212 /* retry with lock held */
213 native_lock_hpte(hptep);
214 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID))
216 native_unlock_hpte(hptep);
222 if (i == HPTES_PER_GROUP)
225 hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
226 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
228 if (!(vflags & HPTE_V_BOLTED)) {
229 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
233 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
234 hpte_r = hpte_old_to_new_r(hpte_v, hpte_r);
235 hpte_v = hpte_old_to_new_v(hpte_v);
238 hptep->r = cpu_to_be64(hpte_r);
239 /* Guarantee the second dword is visible before the valid bit */
242 * Now set the first dword including the valid bit
243 * NOTE: this also unlocks the hpte
245 hptep->v = cpu_to_be64(hpte_v);
247 __asm__ __volatile__ ("ptesync" : : : "memory");
249 return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
252 static long native_hpte_remove(unsigned long hpte_group)
254 struct hash_pte *hptep;
257 unsigned long hpte_v;
259 DBG_LOW(" remove(group=%lx)\n", hpte_group);
261 /* pick a random entry to start at */
262 slot_offset = mftb() & 0x7;
264 for (i = 0; i < HPTES_PER_GROUP; i++) {
265 hptep = htab_address + hpte_group + slot_offset;
266 hpte_v = be64_to_cpu(hptep->v);
268 if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
269 /* retry with lock held */
270 native_lock_hpte(hptep);
271 hpte_v = be64_to_cpu(hptep->v);
272 if ((hpte_v & HPTE_V_VALID)
273 && !(hpte_v & HPTE_V_BOLTED))
275 native_unlock_hpte(hptep);
282 if (i == HPTES_PER_GROUP)
285 /* Invalidate the hpte. NOTE: this also unlocks it */
291 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
292 unsigned long vpn, int bpsize,
293 int apsize, int ssize, unsigned long flags)
295 struct hash_pte *hptep = htab_address + slot;
296 unsigned long hpte_v, want_v;
297 int ret = 0, local = 0;
299 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
301 DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
302 vpn, want_v & HPTE_V_AVPN, slot, newpp);
304 hpte_v = be64_to_cpu(hptep->v);
305 if (cpu_has_feature(CPU_FTR_ARCH_300))
306 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
308 * We need to invalidate the TLB always because hpte_remove doesn't do
309 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
310 * random entry from it. When we do that we don't invalidate the TLB
311 * (hpte_remove) because we assume the old translation is still
312 * technically "valid".
314 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
315 DBG_LOW(" -> miss\n");
318 native_lock_hpte(hptep);
319 /* recheck with locks held */
320 hpte_v = be64_to_cpu(hptep->v);
321 if (cpu_has_feature(CPU_FTR_ARCH_300))
322 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
323 if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) ||
324 !(hpte_v & HPTE_V_VALID))) {
327 DBG_LOW(" -> hit\n");
328 /* Update the HPTE */
329 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
330 ~(HPTE_R_PPP | HPTE_R_N)) |
331 (newpp & (HPTE_R_PPP | HPTE_R_N |
334 native_unlock_hpte(hptep);
337 if (flags & HPTE_LOCAL_UPDATE)
340 * Ensure it is out of the tlb too if it is not a nohpte fault
342 if (!(flags & HPTE_NOHPTE_UPDATE))
343 tlbie(vpn, bpsize, apsize, ssize, local);
348 static long native_hpte_find(unsigned long vpn, int psize, int ssize)
350 struct hash_pte *hptep;
354 unsigned long want_v, hpte_v;
356 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
357 want_v = hpte_encode_avpn(vpn, psize, ssize);
359 /* Bolted mappings are only ever in the primary group */
360 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
361 for (i = 0; i < HPTES_PER_GROUP; i++) {
362 hptep = htab_address + slot;
363 hpte_v = be64_to_cpu(hptep->v);
364 if (cpu_has_feature(CPU_FTR_ARCH_300))
365 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
367 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
377 * Update the page protection bits. Intended to be used to create
378 * guard pages for kernel data structures on pages which are bolted
379 * in the HPT. Assumes pages being operated on will not be stolen.
381 * No need to lock here because we should be the only user.
383 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
384 int psize, int ssize)
389 struct hash_pte *hptep;
391 vsid = get_kernel_vsid(ea, ssize);
392 vpn = hpt_vpn(ea, vsid, ssize);
394 slot = native_hpte_find(vpn, psize, ssize);
396 panic("could not find page to bolt\n");
397 hptep = htab_address + slot;
399 /* Update the HPTE */
400 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
401 ~(HPTE_R_PPP | HPTE_R_N)) |
402 (newpp & (HPTE_R_PPP | HPTE_R_N)));
404 * Ensure it is out of the tlb too. Bolted entries base and
405 * actual page size will be same.
407 tlbie(vpn, psize, psize, ssize, 0);
410 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
411 int bpsize, int apsize, int ssize, int local)
413 struct hash_pte *hptep = htab_address + slot;
414 unsigned long hpte_v;
415 unsigned long want_v;
418 local_irq_save(flags);
420 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
422 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
423 native_lock_hpte(hptep);
424 hpte_v = be64_to_cpu(hptep->v);
425 if (cpu_has_feature(CPU_FTR_ARCH_300))
426 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
429 * We need to invalidate the TLB always because hpte_remove doesn't do
430 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
431 * random entry from it. When we do that we don't invalidate the TLB
432 * (hpte_remove) because we assume the old translation is still
433 * technically "valid".
435 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
436 native_unlock_hpte(hptep);
438 /* Invalidate the hpte. NOTE: this also unlocks it */
441 /* Invalidate the TLB */
442 tlbie(vpn, bpsize, apsize, ssize, local);
444 local_irq_restore(flags);
447 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
448 static void native_hugepage_invalidate(unsigned long vsid,
450 unsigned char *hpte_slot_array,
451 int psize, int ssize, int local)
454 struct hash_pte *hptep;
455 int actual_psize = MMU_PAGE_16M;
456 unsigned int max_hpte_count, valid;
457 unsigned long flags, s_addr = addr;
458 unsigned long hpte_v, want_v, shift;
459 unsigned long hidx, vpn = 0, hash, slot;
461 shift = mmu_psize_defs[psize].shift;
462 max_hpte_count = 1U << (PMD_SHIFT - shift);
464 local_irq_save(flags);
465 for (i = 0; i < max_hpte_count; i++) {
466 valid = hpte_valid(hpte_slot_array, i);
469 hidx = hpte_hash_index(hpte_slot_array, i);
472 addr = s_addr + (i * (1ul << shift));
473 vpn = hpt_vpn(addr, vsid, ssize);
474 hash = hpt_hash(vpn, shift, ssize);
475 if (hidx & _PTEIDX_SECONDARY)
478 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
479 slot += hidx & _PTEIDX_GROUP_IX;
481 hptep = htab_address + slot;
482 want_v = hpte_encode_avpn(vpn, psize, ssize);
483 native_lock_hpte(hptep);
484 hpte_v = be64_to_cpu(hptep->v);
485 if (cpu_has_feature(CPU_FTR_ARCH_300))
486 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
488 /* Even if we miss, we need to invalidate the TLB */
489 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
490 native_unlock_hpte(hptep);
492 /* Invalidate the hpte. NOTE: this also unlocks it */
495 * We need to do tlb invalidate for all the address, tlbie
496 * instruction compares entry_VA in tlb with the VA specified
499 tlbie(vpn, psize, actual_psize, ssize, local);
501 local_irq_restore(flags);
504 static void native_hugepage_invalidate(unsigned long vsid,
506 unsigned char *hpte_slot_array,
507 int psize, int ssize, int local)
509 WARN(1, "%s called without THP support\n", __func__);
513 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
514 int *psize, int *apsize, int *ssize, unsigned long *vpn)
516 unsigned long avpn, pteg, vpi;
517 unsigned long hpte_v = be64_to_cpu(hpte->v);
518 unsigned long hpte_r = be64_to_cpu(hpte->r);
519 unsigned long vsid, seg_off;
520 int size, a_size, shift;
521 /* Look at the 8 bit LP value */
522 unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
524 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
525 hpte_v = hpte_new_to_old_v(hpte_v, hpte_r);
526 hpte_r = hpte_new_to_old_r(hpte_r);
528 if (!(hpte_v & HPTE_V_LARGE)) {
530 a_size = MMU_PAGE_4K;
532 size = hpte_page_sizes[lp] & 0xf;
533 a_size = hpte_page_sizes[lp] >> 4;
535 /* This works for all page sizes, and for 256M and 1T segments */
536 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
537 shift = mmu_psize_defs[size].shift;
539 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
540 pteg = slot / HPTES_PER_GROUP;
541 if (hpte_v & HPTE_V_SECONDARY)
545 case MMU_SEGSIZE_256M:
546 /* We only have 28 - 23 bits of seg_off in avpn */
547 seg_off = (avpn & 0x1f) << 23;
549 /* We can find more bits from the pteg value */
551 vpi = (vsid ^ pteg) & htab_hash_mask;
552 seg_off |= vpi << shift;
554 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
557 /* We only have 40 - 23 bits of seg_off in avpn */
558 seg_off = (avpn & 0x1ffff) << 23;
561 vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
562 seg_off |= vpi << shift;
564 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
574 * clear all mappings on kexec. All cpus are in real mode (or they will
575 * be when they isi), and we are the only one left. We rely on our kernel
576 * mapping being 0xC0's and the hardware ignoring those two real bits.
578 * This must be called with interrupts disabled.
580 * Taking the native_tlbie_lock is unsafe here due to the possibility of
581 * lockdep being on. On pre POWER5 hardware, not taking the lock could
582 * cause deadlock. POWER5 and newer not taking the lock is fine. This only
583 * gets called during boot before secondary CPUs have come up and during
584 * crashdump and all bets are off anyway.
586 * TODO: add batching support when enabled. remember, no dynamic memory here,
587 * although there is the control page available...
589 static void native_hpte_clear(void)
591 unsigned long vpn = 0;
592 unsigned long slot, slots;
593 struct hash_pte *hptep = htab_address;
594 unsigned long hpte_v;
595 unsigned long pteg_count;
596 int psize, apsize, ssize;
598 pteg_count = htab_hash_mask + 1;
600 slots = pteg_count * HPTES_PER_GROUP;
602 for (slot = 0; slot < slots; slot++, hptep++) {
604 * we could lock the pte here, but we are the only cpu
605 * running, right? and for crash dump, we probably
606 * don't want to wait for a maybe bad cpu.
608 hpte_v = be64_to_cpu(hptep->v);
611 * Call __tlbie() here rather than tlbie() since we can't take the
614 if (hpte_v & HPTE_V_VALID) {
615 hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
617 __tlbie(vpn, psize, apsize, ssize);
621 asm volatile("eieio; tlbsync; ptesync":::"memory");
625 * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
626 * the lock all the time
628 static void native_flush_hash_range(unsigned long number, int local)
631 unsigned long hash, index, hidx, shift, slot;
632 struct hash_pte *hptep;
633 unsigned long hpte_v;
634 unsigned long want_v;
637 struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);
638 unsigned long psize = batch->psize;
639 int ssize = batch->ssize;
641 unsigned int use_local;
643 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) &&
644 mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use();
646 local_irq_save(flags);
648 for (i = 0; i < number; i++) {
652 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
653 hash = hpt_hash(vpn, shift, ssize);
654 hidx = __rpte_to_hidx(pte, index);
655 if (hidx & _PTEIDX_SECONDARY)
657 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
658 slot += hidx & _PTEIDX_GROUP_IX;
659 hptep = htab_address + slot;
660 want_v = hpte_encode_avpn(vpn, psize, ssize);
661 native_lock_hpte(hptep);
662 hpte_v = be64_to_cpu(hptep->v);
663 if (cpu_has_feature(CPU_FTR_ARCH_300))
664 hpte_v = hpte_new_to_old_v(hpte_v,
665 be64_to_cpu(hptep->r));
666 if (!HPTE_V_COMPARE(hpte_v, want_v) ||
667 !(hpte_v & HPTE_V_VALID))
668 native_unlock_hpte(hptep);
671 } pte_iterate_hashed_end();
675 asm volatile("ptesync":::"memory");
676 for (i = 0; i < number; i++) {
680 pte_iterate_hashed_subpages(pte, psize,
682 __tlbiel(vpn, psize, psize, ssize);
683 } pte_iterate_hashed_end();
685 asm volatile("ptesync":::"memory");
687 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
690 raw_spin_lock(&native_tlbie_lock);
692 asm volatile("ptesync":::"memory");
693 for (i = 0; i < number; i++) {
697 pte_iterate_hashed_subpages(pte, psize,
699 __tlbie(vpn, psize, psize, ssize);
700 } pte_iterate_hashed_end();
702 asm volatile("eieio; tlbsync; ptesync":::"memory");
705 raw_spin_unlock(&native_tlbie_lock);
708 local_irq_restore(flags);
711 static int native_register_proc_table(unsigned long base, unsigned long page_size,
712 unsigned long table_size)
714 unsigned long patb1 = base << 25; /* VSID */
716 patb1 |= (page_size << 5); /* sllp */
719 partition_tb->patb1 = cpu_to_be64(patb1);
723 void __init hpte_init_native(void)
725 mmu_hash_ops.hpte_invalidate = native_hpte_invalidate;
726 mmu_hash_ops.hpte_updatepp = native_hpte_updatepp;
727 mmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;
728 mmu_hash_ops.hpte_insert = native_hpte_insert;
729 mmu_hash_ops.hpte_remove = native_hpte_remove;
730 mmu_hash_ops.hpte_clear_all = native_hpte_clear;
731 mmu_hash_ops.flush_hash_range = native_flush_hash_range;
732 mmu_hash_ops.hugepage_invalidate = native_hugepage_invalidate;
734 if (cpu_has_feature(CPU_FTR_ARCH_300))
735 register_process_table = native_register_proc_table;