arch/powerpc/lib/sstep.c

   1 /*
   2  * Single-step support.
   3  *
   4  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/kprobes.h>
  13 #include <linux/ptrace.h>
  14 #include <linux/prefetch.h>
  15 #include <asm/sstep.h>
  16 #include <asm/processor.h>
  17 #include <linux/uaccess.h>
  18 #include <asm/cpu_has_feature.h>
  19 #include <asm/cputable.h>
  20
  21 extern char system_call_common[];
  22
  23 #ifdef CONFIG_PPC64
  24 /* Bits in SRR1 that are copied from MSR */
  25 #define MSR_MASK        0xffffffff87c0ffffUL
  26 #else
  27 #define MSR_MASK        0x87c0ffff
  28 #endif
  29
  30 /* Bits in XER */
  31 #define XER_SO          0x80000000U
  32 #define XER_OV          0x40000000U
  33 #define XER_CA          0x20000000U
  34
  35 #ifdef CONFIG_PPC_FPU
  36 /*
  37  * Functions in ldstfp.S
  38  */
  39 extern void get_fpr(int rn, double *p);
  40 extern void put_fpr(int rn, const double *p);
  41 extern void get_vr(int rn, __vector128 *p);
  42 extern void put_vr(int rn, __vector128 *p);
  43 extern void load_vsrn(int vsr, const void *p);
  44 extern void store_vsrn(int vsr, void *p);
  45 extern void conv_sp_to_dp(const float *sp, double *dp);
  46 extern void conv_dp_to_sp(const double *dp, float *sp);
  47 #endif
  48
  49 #ifdef __powerpc64__
  50 /*
  51  * Functions in quad.S
  52  */
  53 extern int do_lq(unsigned long ea, unsigned long *regs);
  54 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  55 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  56 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  57                     unsigned int *crp);
  58 #endif
  59
  60 #ifdef __LITTLE_ENDIAN__
  61 #define IS_LE   1
  62 #define IS_BE   0
  63 #else
  64 #define IS_LE   0
  65 #define IS_BE   1
  66 #endif
  67
  68 /*
  69  * Emulate the truncation of 64 bit values in 32-bit mode.
  70  */
  71 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  72                                                         unsigned long val)
  73 {
  74 #ifdef __powerpc64__
  75         if ((msr & MSR_64BIT) == 0)
  76                 val &= 0xffffffffUL;
  77 #endif
  78         return val;
  79 }
  80
  81 /*
  82  * Determine whether a conditional branch instruction would branch.
  83  */
  84 static nokprobe_inline int branch_taken(unsigned int instr,
  85                                         const struct pt_regs *regs,
  86                                         struct instruction_op *op)
  87 {
  88         unsigned int bo = (instr >> 21) & 0x1f;
  89         unsigned int bi;
  90
  91         if ((bo & 4) == 0) {
  92                 /* decrement counter */
  93                 op->type |= DECCTR;
  94                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  95                         return 0;
  96         }
  97         if ((bo & 0x10) == 0) {
  98                 /* check bit from CR */
  99                 bi = (instr >> 16) & 0x1f;
 100                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 101                         return 0;
 102         }
 103         return 1;
 104 }
 105
 106 static nokprobe_inline long address_ok(struct pt_regs *regs,
 107                                        unsigned long ea, int nb)
 108 {
 109         if (!user_mode(regs))
 110                 return 1;
 111         if (__access_ok(ea, nb, USER_DS))
 112                 return 1;
 113         if (__access_ok(ea, 1, USER_DS))
 114                 /* Access overlaps the end of the user region */
 115                 regs->dar = USER_DS.seg;
 116         else
 117                 regs->dar = ea;
 118         return 0;
 119 }
 120
 121 /*
 122  * Calculate effective address for a D-form instruction
 123  */
 124 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 125                                               const struct pt_regs *regs)
 126 {
 127         int ra;
 128         unsigned long ea;
 129
 130         ra = (instr >> 16) & 0x1f;
 131         ea = (signed short) instr;              /* sign-extend */
 132         if (ra)
 133                 ea += regs->gpr[ra];
 134
 135         return ea;
 136 }
 137
 138 #ifdef __powerpc64__
 139 /*
 140  * Calculate effective address for a DS-form instruction
 141  */
 142 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 143                                                const struct pt_regs *regs)
 144 {
 145         int ra;
 146         unsigned long ea;
 147
 148         ra = (instr >> 16) & 0x1f;
 149         ea = (signed short) (instr & ~3);       /* sign-extend */
 150         if (ra)
 151                 ea += regs->gpr[ra];
 152
 153         return ea;
 154 }
 155
 156 /*
 157  * Calculate effective address for a DQ-form instruction
 158  */
 159 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 160                                                const struct pt_regs *regs)
 161 {
 162         int ra;
 163         unsigned long ea;
 164
 165         ra = (instr >> 16) & 0x1f;
 166         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 167         if (ra)
 168                 ea += regs->gpr[ra];
 169
 170         return ea;
 171 }
 172 #endif /* __powerpc64 */
 173
 174 /*
 175  * Calculate effective address for an X-form instruction
 176  */
 177 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 178                                               const struct pt_regs *regs)
 179 {
 180         int ra, rb;
 181         unsigned long ea;
 182
 183         ra = (instr >> 16) & 0x1f;
 184         rb = (instr >> 11) & 0x1f;
 185         ea = regs->gpr[rb];
 186         if (ra)
 187                 ea += regs->gpr[ra];
 188
 189         return ea;
 190 }
 191
 192 /*
 193  * Return the largest power of 2, not greater than sizeof(unsigned long),
 194  * such that x is a multiple of it.
 195  */
 196 static nokprobe_inline unsigned long max_align(unsigned long x)
 197 {
 198         x |= sizeof(unsigned long);
 199         return x & -x;          /* isolates rightmost bit */
 200 }
 201
 202 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 203 {
 204         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 205 }
 206
 207 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 208 {
 209         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 210                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 211 }
 212
 213 #ifdef __powerpc64__
 214 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 215 {
 216         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 217 }
 218 #endif
 219
 220 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
 221 {
 222         switch (nb) {
 223         case 2:
 224                 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
 225                 break;
 226         case 4:
 227                 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
 228                 break;
 229 #ifdef __powerpc64__
 230         case 8:
 231                 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
 232                 break;
 233         case 16: {
 234                 unsigned long *up = (unsigned long *)ptr;
 235                 unsigned long tmp;
 236                 tmp = byterev_8(up[0]);
 237                 up[0] = byterev_8(up[1]);
 238                 up[1] = tmp;
 239                 break;
 240         }
 241 #endif
 242         default:
 243                 WARN_ON_ONCE(1);
 244         }
 245 }
 246
 247 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 248                                             unsigned long ea, int nb,
 249                                             struct pt_regs *regs)
 250 {
 251         int err = 0;
 252         unsigned long x = 0;
 253
 254         switch (nb) {
 255         case 1:
 256                 err = __get_user(x, (unsigned char __user *) ea);
 257                 break;
 258         case 2:
 259                 err = __get_user(x, (unsigned short __user *) ea);
 260                 break;
 261         case 4:
 262                 err = __get_user(x, (unsigned int __user *) ea);
 263                 break;
 264 #ifdef __powerpc64__
 265         case 8:
 266                 err = __get_user(x, (unsigned long __user *) ea);
 267                 break;
 268 #endif
 269         }
 270         if (!err)
 271                 *dest = x;
 272         else
 273                 regs->dar = ea;
 274         return err;
 275 }
 276
 277 /*
 278  * Copy from userspace to a buffer, using the largest possible
 279  * aligned accesses, up to sizeof(long).
 280  */
 281 static int nokprobe_inline copy_mem_in(u8 *dest, unsigned long ea, int nb,
 282                                        struct pt_regs *regs)
 283 {
 284         int err = 0;
 285         int c;
 286
 287         for (; nb > 0; nb -= c) {
 288                 c = max_align(ea);
 289                 if (c > nb)
 290                         c = max_align(nb);
 291                 switch (c) {
 292                 case 1:
 293                         err = __get_user(*dest, (unsigned char __user *) ea);
 294                         break;
 295                 case 2:
 296                         err = __get_user(*(u16 *)dest,
 297                                          (unsigned short __user *) ea);
 298                         break;
 299                 case 4:
 300                         err = __get_user(*(u32 *)dest,
 301                                          (unsigned int __user *) ea);
 302                         break;
 303 #ifdef __powerpc64__
 304                 case 8:
 305                         err = __get_user(*(unsigned long *)dest,
 306                                          (unsigned long __user *) ea);
 307                         break;
 308 #endif
 309                 }
 310                 if (err) {
 311                         regs->dar = ea;
 312                         return err;
 313                 }
 314                 dest += c;
 315                 ea += c;
 316         }
 317         return 0;
 318 }
 319
 320 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 321                                               unsigned long ea, int nb,
 322                                               struct pt_regs *regs)
 323 {
 324         union {
 325                 unsigned long ul;
 326                 u8 b[sizeof(unsigned long)];
 327         } u;
 328         int i;
 329         int err;
 330
 331         u.ul = 0;
 332         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 333         err = copy_mem_in(&u.b[i], ea, nb, regs);
 334         if (!err)
 335                 *dest = u.ul;
 336         return err;
 337 }
 338
 339 /*
 340  * Read memory at address ea for nb bytes, return 0 for success
 341  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 342  * If nb < sizeof(long), the result is right-justified on BE systems.
 343  */
 344 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 345                               struct pt_regs *regs)
 346 {
 347         if (!address_ok(regs, ea, nb))
 348                 return -EFAULT;
 349         if ((ea & (nb - 1)) == 0)
 350                 return read_mem_aligned(dest, ea, nb, regs);
 351         return read_mem_unaligned(dest, ea, nb, regs);
 352 }
 353 NOKPROBE_SYMBOL(read_mem);
 354
 355 static nokprobe_inline int write_mem_aligned(unsigned long val,
 356                                              unsigned long ea, int nb,
 357                                              struct pt_regs *regs)
 358 {
 359         int err = 0;
 360
 361         switch (nb) {
 362         case 1:
 363                 err = __put_user(val, (unsigned char __user *) ea);
 364                 break;
 365         case 2:
 366                 err = __put_user(val, (unsigned short __user *) ea);
 367                 break;
 368         case 4:
 369                 err = __put_user(val, (unsigned int __user *) ea);
 370                 break;
 371 #ifdef __powerpc64__
 372         case 8:
 373                 err = __put_user(val, (unsigned long __user *) ea);
 374                 break;
 375 #endif
 376         }
 377         if (err)
 378                 regs->dar = ea;
 379         return err;
 380 }
 381
 382 /*
 383  * Copy from a buffer to userspace, using the largest possible
 384  * aligned accesses, up to sizeof(long).
 385  */
 386 static int nokprobe_inline copy_mem_out(u8 *dest, unsigned long ea, int nb,
 387                                         struct pt_regs *regs)
 388 {
 389         int err = 0;
 390         int c;
 391
 392         for (; nb > 0; nb -= c) {
 393                 c = max_align(ea);
 394                 if (c > nb)
 395                         c = max_align(nb);
 396                 switch (c) {
 397                 case 1:
 398                         err = __put_user(*dest, (unsigned char __user *) ea);
 399                         break;
 400                 case 2:
 401                         err = __put_user(*(u16 *)dest,
 402                                          (unsigned short __user *) ea);
 403                         break;
 404                 case 4:
 405                         err = __put_user(*(u32 *)dest,
 406                                          (unsigned int __user *) ea);
 407                         break;
 408 #ifdef __powerpc64__
 409                 case 8:
 410                         err = __put_user(*(unsigned long *)dest,
 411                                          (unsigned long __user *) ea);
 412                         break;
 413 #endif
 414                 }
 415                 if (err) {
 416                         regs->dar = ea;
 417                         return err;
 418                 }
 419                 dest += c;
 420                 ea += c;
 421         }
 422         return 0;
 423 }
 424
 425 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 426                                                unsigned long ea, int nb,
 427                                                struct pt_regs *regs)
 428 {
 429         union {
 430                 unsigned long ul;
 431                 u8 b[sizeof(unsigned long)];
 432         } u;
 433         int i;
 434
 435         u.ul = val;
 436         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 437         return copy_mem_out(&u.b[i], ea, nb, regs);
 438 }
 439
 440 /*
 441  * Write memory at address ea for nb bytes, return 0 for success
 442  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 443  */
 444 static int write_mem(unsigned long val, unsigned long ea, int nb,
 445                                struct pt_regs *regs)
 446 {
 447         if (!address_ok(regs, ea, nb))
 448                 return -EFAULT;
 449         if ((ea & (nb - 1)) == 0)
 450                 return write_mem_aligned(val, ea, nb, regs);
 451         return write_mem_unaligned(val, ea, nb, regs);
 452 }
 453 NOKPROBE_SYMBOL(write_mem);
 454
 455 #ifdef CONFIG_PPC_FPU
 456 /*
 457  * These access either the real FP register or the image in the
 458  * thread_struct, depending on regs->msr & MSR_FP.
 459  */
 460 static int do_fp_load(struct instruction_op *op, unsigned long ea,
 461                       struct pt_regs *regs, bool cross_endian)
 462 {
 463         int err, rn, nb;
 464         union {
 465                 int i;
 466                 unsigned int u;
 467                 float f;
 468                 double d[2];
 469                 unsigned long l[2];
 470                 u8 b[2 * sizeof(double)];
 471         } u;
 472
 473         nb = GETSIZE(op->type);
 474         if (!address_ok(regs, ea, nb))
 475                 return -EFAULT;
 476         rn = op->reg;
 477         err = copy_mem_in(u.b, ea, nb, regs);
 478         if (err)
 479                 return err;
 480         if (unlikely(cross_endian)) {
 481                 do_byte_reverse(u.b, min(nb, 8));
 482                 if (nb == 16)
 483                         do_byte_reverse(&u.b[8], 8);
 484         }
 485         preempt_disable();
 486         if (nb == 4) {
 487                 if (op->type & FPCONV)
 488                         conv_sp_to_dp(&u.f, &u.d[0]);
 489                 else if (op->type & SIGNEXT)
 490                         u.l[0] = u.i;
 491                 else
 492                         u.l[0] = u.u;
 493         }
 494         if (regs->msr & MSR_FP)
 495                 put_fpr(rn, &u.d[0]);
 496         else
 497                 current->thread.TS_FPR(rn) = u.l[0];
 498         if (nb == 16) {
 499                 /* lfdp */
 500                 rn |= 1;
 501                 if (regs->msr & MSR_FP)
 502                         put_fpr(rn, &u.d[1]);
 503                 else
 504                         current->thread.TS_FPR(rn) = u.l[1];
 505         }
 506         preempt_enable();
 507         return 0;
 508 }
 509 NOKPROBE_SYMBOL(do_fp_load);
 510
 511 static int do_fp_store(struct instruction_op *op, unsigned long ea,
 512                        struct pt_regs *regs, bool cross_endian)
 513 {
 514         int rn, nb;
 515         union {
 516                 unsigned int u;
 517                 float f;
 518                 double d[2];
 519                 unsigned long l[2];
 520                 u8 b[2 * sizeof(double)];
 521         } u;
 522
 523         nb = GETSIZE(op->type);
 524         if (!address_ok(regs, ea, nb))
 525                 return -EFAULT;
 526         rn = op->reg;
 527         preempt_disable();
 528         if (regs->msr & MSR_FP)
 529                 get_fpr(rn, &u.d[0]);
 530         else
 531                 u.l[0] = current->thread.TS_FPR(rn);
 532         if (nb == 4) {
 533                 if (op->type & FPCONV)
 534                         conv_dp_to_sp(&u.d[0], &u.f);
 535                 else
 536                         u.u = u.l[0];
 537         }
 538         if (nb == 16) {
 539                 rn |= 1;
 540                 if (regs->msr & MSR_FP)
 541                         get_fpr(rn, &u.d[1]);
 542                 else
 543                         u.l[1] = current->thread.TS_FPR(rn);
 544         }
 545         preempt_enable();
 546         if (unlikely(cross_endian)) {
 547                 do_byte_reverse(u.b, min(nb, 8));
 548                 if (nb == 16)
 549                         do_byte_reverse(&u.b[8], 8);
 550         }
 551         return copy_mem_out(u.b, ea, nb, regs);
 552 }
 553 NOKPROBE_SYMBOL(do_fp_store);
 554 #endif
 555
 556 #ifdef CONFIG_ALTIVEC
 557 /* For Altivec/VMX, no need to worry about alignment */
 558 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
 559                                        int size, struct pt_regs *regs,
 560                                        bool cross_endian)
 561 {
 562         int err;
 563         union {
 564                 __vector128 v;
 565                 u8 b[sizeof(__vector128)];
 566         } u = {};
 567
 568         if (!address_ok(regs, ea & ~0xfUL, 16))
 569                 return -EFAULT;
 570         /* align to multiple of size */
 571         ea &= ~(size - 1);
 572         err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
 573         if (err)
 574                 return err;
 575         if (unlikely(cross_endian))
 576                 do_byte_reverse(&u.b[ea & 0xf], size);
 577         preempt_disable();
 578         if (regs->msr & MSR_VEC)
 579                 put_vr(rn, &u.v);
 580         else
 581                 current->thread.vr_state.vr[rn] = u.v;
 582         preempt_enable();
 583         return 0;
 584 }
 585
 586 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
 587                                         int size, struct pt_regs *regs,
 588                                         bool cross_endian)
 589 {
 590         union {
 591                 __vector128 v;
 592                 u8 b[sizeof(__vector128)];
 593         } u;
 594
 595         if (!address_ok(regs, ea & ~0xfUL, 16))
 596                 return -EFAULT;
 597         /* align to multiple of size */
 598         ea &= ~(size - 1);
 599
 600         preempt_disable();
 601         if (regs->msr & MSR_VEC)
 602                 get_vr(rn, &u.v);
 603         else
 604                 u.v = current->thread.vr_state.vr[rn];
 605         preempt_enable();
 606         if (unlikely(cross_endian))
 607                 do_byte_reverse(&u.b[ea & 0xf], size);
 608         return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
 609 }
 610 #endif /* CONFIG_ALTIVEC */
 611
 612 #ifdef __powerpc64__
 613 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 614                                       int reg, bool cross_endian)
 615 {
 616         int err;
 617
 618         if (!address_ok(regs, ea, 16))
 619                 return -EFAULT;
 620         /* if aligned, should be atomic */
 621         if ((ea & 0xf) == 0) {
 622                 err = do_lq(ea, &regs->gpr[reg]);
 623         } else {
 624                 err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 625                 if (!err)
 626                         err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 627         }
 628         if (!err && unlikely(cross_endian))
 629                 do_byte_reverse(&regs->gpr[reg], 16);
 630         return err;
 631 }
 632
 633 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 634                                        int reg, bool cross_endian)
 635 {
 636         int err;
 637         unsigned long vals[2];
 638
 639         if (!address_ok(regs, ea, 16))
 640                 return -EFAULT;
 641         vals[0] = regs->gpr[reg];
 642         vals[1] = regs->gpr[reg + 1];
 643         if (unlikely(cross_endian))
 644                 do_byte_reverse(vals, 16);
 645
 646         /* if aligned, should be atomic */
 647         if ((ea & 0xf) == 0)
 648                 return do_stq(ea, vals[0], vals[1]);
 649
 650         err = write_mem(vals[IS_LE], ea, 8, regs);
 651         if (!err)
 652                 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
 653         return err;
 654 }
 655 #endif /* __powerpc64 */
 656
 657 #ifdef CONFIG_VSX
 658 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 659                       const void *mem, bool rev)
 660 {
 661         int size, read_size;
 662         int i, j;
 663         const unsigned int *wp;
 664         const unsigned short *hp;
 665         const unsigned char *bp;
 666
 667         size = GETSIZE(op->type);
 668         reg->d[0] = reg->d[1] = 0;
 669
 670         switch (op->element_size) {
 671         case 16:
 672                 /* whole vector; lxv[x] or lxvl[l] */
 673                 if (size == 0)
 674                         break;
 675                 memcpy(reg, mem, size);
 676                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 677                         rev = !rev;
 678                 if (rev)
 679                         do_byte_reverse(reg, 16);
 680                 break;
 681         case 8:
 682                 /* scalar loads, lxvd2x, lxvdsx */
 683                 read_size = (size >= 8) ? 8 : size;
 684                 i = IS_LE ? 8 : 8 - read_size;
 685                 memcpy(&reg->b[i], mem, read_size);
 686                 if (rev)
 687                         do_byte_reverse(&reg->b[i], 8);
 688                 if (size < 8) {
 689                         if (op->type & SIGNEXT) {
 690                                 /* size == 4 is the only case here */
 691                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 692                         } else if (op->vsx_flags & VSX_FPCONV) {
 693                                 preempt_disable();
 694                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 695                                               &reg->dp[IS_LE]);
 696                                 preempt_enable();
 697                         }
 698                 } else {
 699                         if (size == 16) {
 700                                 unsigned long v = *(unsigned long *)(mem + 8);
 701                                 reg->d[IS_BE] = !rev ? v : byterev_8(v);
 702                         } else if (op->vsx_flags & VSX_SPLAT)
 703                                 reg->d[IS_BE] = reg->d[IS_LE];
 704                 }
 705                 break;
 706         case 4:
 707                 /* lxvw4x, lxvwsx */
 708                 wp = mem;
 709                 for (j = 0; j < size / 4; ++j) {
 710                         i = IS_LE ? 3 - j : j;
 711                         reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
 712                 }
 713                 if (op->vsx_flags & VSX_SPLAT) {
 714                         u32 val = reg->w[IS_LE ? 3 : 0];
 715                         for (; j < 4; ++j) {
 716                                 i = IS_LE ? 3 - j : j;
 717                                 reg->w[i] = val;
 718                         }
 719                 }
 720                 break;
 721         case 2:
 722                 /* lxvh8x */
 723                 hp = mem;
 724                 for (j = 0; j < size / 2; ++j) {
 725                         i = IS_LE ? 7 - j : j;
 726                         reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
 727                 }
 728                 break;
 729         case 1:
 730                 /* lxvb16x */
 731                 bp = mem;
 732                 for (j = 0; j < size; ++j) {
 733                         i = IS_LE ? 15 - j : j;
 734                         reg->b[i] = *bp++;
 735                 }
 736                 break;
 737         }
 738 }
 739 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 740 NOKPROBE_SYMBOL(emulate_vsx_load);
 741
 742 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 743                        void *mem, bool rev)
 744 {
 745         int size, write_size;
 746         int i, j;
 747         union vsx_reg buf;
 748         unsigned int *wp;
 749         unsigned short *hp;
 750         unsigned char *bp;
 751
 752         size = GETSIZE(op->type);
 753
 754         switch (op->element_size) {
 755         case 16:
 756                 /* stxv, stxvx, stxvl, stxvll */
 757                 if (size == 0)
 758                         break;
 759                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 760                         rev = !rev;
 761                 if (rev) {
 762                         /* reverse 16 bytes */
 763                         buf.d[0] = byterev_8(reg->d[1]);
 764                         buf.d[1] = byterev_8(reg->d[0]);
 765                         reg = &buf;
 766                 }
 767                 memcpy(mem, reg, size);
 768                 break;
 769         case 8:
 770                 /* scalar stores, stxvd2x */
 771                 write_size = (size >= 8) ? 8 : size;
 772                 i = IS_LE ? 8 : 8 - write_size;
 773                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 774                         buf.d[0] = buf.d[1] = 0;
 775                         preempt_disable();
 776                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 777                         preempt_enable();
 778                         reg = &buf;
 779                 }
 780                 memcpy(mem, &reg->b[i], write_size);
 781                 if (size == 16)
 782                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 783                 if (unlikely(rev)) {
 784                         do_byte_reverse(mem, write_size);
 785                         if (size == 16)
 786                                 do_byte_reverse(mem + 8, 8);
 787                 }
 788                 break;
 789         case 4:
 790                 /* stxvw4x */
 791                 wp = mem;
 792                 for (j = 0; j < size / 4; ++j) {
 793                         i = IS_LE ? 3 - j : j;
 794                         *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
 795                 }
 796                 break;
 797         case 2:
 798                 /* stxvh8x */
 799                 hp = mem;
 800                 for (j = 0; j < size / 2; ++j) {
 801                         i = IS_LE ? 7 - j : j;
 802                         *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
 803                 }
 804                 break;
 805         case 1:
 806                 /* stvxb16x */
 807                 bp = mem;
 808                 for (j = 0; j < size; ++j) {
 809                         i = IS_LE ? 15 - j : j;
 810                         *bp++ = reg->b[i];
 811                 }
 812                 break;
 813         }
 814 }
 815 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 816 NOKPROBE_SYMBOL(emulate_vsx_store);
 817
 818 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
 819                                        unsigned long ea, struct pt_regs *regs,
 820                                        bool cross_endian)
 821 {
 822         int reg = op->reg;
 823         u8 mem[16];
 824         union vsx_reg buf;
 825         int size = GETSIZE(op->type);
 826
 827         if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
 828                 return -EFAULT;
 829
 830         emulate_vsx_load(op, &buf, mem, cross_endian);
 831         preempt_disable();
 832         if (reg < 32) {
 833                 /* FP regs + extensions */
 834                 if (regs->msr & MSR_FP) {
 835                         load_vsrn(reg, &buf);
 836                 } else {
 837                         current->thread.fp_state.fpr[reg][0] = buf.d[0];
 838                         current->thread.fp_state.fpr[reg][1] = buf.d[1];
 839                 }
 840         } else {
 841                 if (regs->msr & MSR_VEC)
 842                         load_vsrn(reg, &buf);
 843                 else
 844                         current->thread.vr_state.vr[reg - 32] = buf.v;
 845         }
 846         preempt_enable();
 847         return 0;
 848 }
 849
 850 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
 851                                         unsigned long ea, struct pt_regs *regs,
 852                                         bool cross_endian)
 853 {
 854         int reg = op->reg;
 855         u8 mem[16];
 856         union vsx_reg buf;
 857         int size = GETSIZE(op->type);
 858
 859         if (!address_ok(regs, ea, size))
 860                 return -EFAULT;
 861
 862         preempt_disable();
 863         if (reg < 32) {
 864                 /* FP regs + extensions */
 865                 if (regs->msr & MSR_FP) {
 866                         store_vsrn(reg, &buf);
 867                 } else {
 868                         buf.d[0] = current->thread.fp_state.fpr[reg][0];
 869                         buf.d[1] = current->thread.fp_state.fpr[reg][1];
 870                 }
 871         } else {
 872                 if (regs->msr & MSR_VEC)
 873                         store_vsrn(reg, &buf);
 874                 else
 875                         buf.v = current->thread.vr_state.vr[reg - 32];
 876         }
 877         preempt_enable();
 878         emulate_vsx_store(op, &buf, mem, cross_endian);
 879         return  copy_mem_out(mem, ea, size, regs);
 880 }
 881 #endif /* CONFIG_VSX */
 882
 883 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
 884 {
 885         int err;
 886         unsigned long i, size;
 887
 888 #ifdef __powerpc64__
 889         size = ppc64_caches.l1d.block_size;
 890         if (!(regs->msr & MSR_64BIT))
 891                 ea &= 0xffffffffUL;
 892 #else
 893         size = L1_CACHE_BYTES;
 894 #endif
 895         ea &= ~(size - 1);
 896         if (!address_ok(regs, ea, size))
 897                 return -EFAULT;
 898         for (i = 0; i < size; i += sizeof(long)) {
 899                 err = __put_user(0, (unsigned long __user *) (ea + i));
 900                 if (err) {
 901                         regs->dar = ea;
 902                         return err;
 903                 }
 904         }
 905         return 0;
 906 }
 907 NOKPROBE_SYMBOL(emulate_dcbz);
 908
 909 #define __put_user_asmx(x, addr, err, op, cr)           \
 910         __asm__ __volatile__(                           \
 911                 "1:     " op " %2,0,%3\n"               \
 912                 "       mfcr    %1\n"                   \
 913                 "2:\n"                                  \
 914                 ".section .fixup,\"ax\"\n"              \
 915                 "3:     li      %0,%4\n"                \
 916                 "       b       2b\n"                   \
 917                 ".previous\n"                           \
 918                 EX_TABLE(1b, 3b)                        \
 919                 : "=r" (err), "=r" (cr)                 \
 920                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
 921
 922 #define __get_user_asmx(x, addr, err, op)               \
 923         __asm__ __volatile__(                           \
 924                 "1:     "op" %1,0,%2\n"                 \
 925                 "2:\n"                                  \
 926                 ".section .fixup,\"ax\"\n"              \
 927                 "3:     li      %0,%3\n"                \
 928                 "       b       2b\n"                   \
 929                 ".previous\n"                           \
 930                 EX_TABLE(1b, 3b)                        \
 931                 : "=r" (err), "=r" (x)                  \
 932                 : "r" (addr), "i" (-EFAULT), "0" (err))
 933
 934 #define __cacheop_user_asmx(addr, err, op)              \
 935         __asm__ __volatile__(                           \
 936                 "1:     "op" 0,%1\n"                    \
 937                 "2:\n"                                  \
 938                 ".section .fixup,\"ax\"\n"              \
 939                 "3:     li      %0,%3\n"                \
 940                 "       b       2b\n"                   \
 941                 ".previous\n"                           \
 942                 EX_TABLE(1b, 3b)                        \
 943                 : "=r" (err)                            \
 944                 : "r" (addr), "i" (-EFAULT), "0" (err))
 945
 946 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
 947                                     struct instruction_op *op)
 948 {
 949         long val = op->val;
 950
 951         op->type |= SETCC;
 952         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
 953 #ifdef __powerpc64__
 954         if (!(regs->msr & MSR_64BIT))
 955                 val = (int) val;
 956 #endif
 957         if (val < 0)
 958                 op->ccval |= 0x80000000;
 959         else if (val > 0)
 960                 op->ccval |= 0x40000000;
 961         else
 962                 op->ccval |= 0x20000000;
 963 }
 964
 965 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
 966                                      struct instruction_op *op, int rd,
 967                                      unsigned long val1, unsigned long val2,
 968                                      unsigned long carry_in)
 969 {
 970         unsigned long val = val1 + val2;
 971
 972         if (carry_in)
 973                 ++val;
 974         op->type = COMPUTE + SETREG + SETXER;
 975         op->reg = rd;
 976         op->val = val;
 977 #ifdef __powerpc64__
 978         if (!(regs->msr & MSR_64BIT)) {
 979                 val = (unsigned int) val;
 980                 val1 = (unsigned int) val1;
 981         }
 982 #endif
 983         op->xerval = regs->xer;
 984         if (val < val1 || (carry_in && val == val1))
 985                 op->xerval |= XER_CA;
 986         else
 987                 op->xerval &= ~XER_CA;
 988 }
 989
 990 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
 991                                           struct instruction_op *op,
 992                                           long v1, long v2, int crfld)
 993 {
 994         unsigned int crval, shift;
 995
 996         op->type = COMPUTE + SETCC;
 997         crval = (regs->xer >> 31) & 1;          /* get SO bit */
 998         if (v1 < v2)
 999                 crval |= 8;
1000         else if (v1 > v2)
1001                 crval |= 4;
1002         else
1003                 crval |= 2;
1004         shift = (7 - crfld) * 4;
1005         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1006 }
1007
1008 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1009                                             struct instruction_op *op,
1010                                             unsigned long v1,
1011                                             unsigned long v2, int crfld)
1012 {
1013         unsigned int crval, shift;
1014
1015         op->type = COMPUTE + SETCC;
1016         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1017         if (v1 < v2)
1018                 crval |= 8;
1019         else if (v1 > v2)
1020                 crval |= 4;
1021         else
1022                 crval |= 2;
1023         shift = (7 - crfld) * 4;
1024         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1025 }
1026
1027 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1028                                     struct instruction_op *op,
1029                                     unsigned long v1, unsigned long v2)
1030 {
1031         unsigned long long out_val, mask;
1032         int i;
1033
1034         out_val = 0;
1035         for (i = 0; i < 8; i++) {
1036                 mask = 0xffUL << (i * 8);
1037                 if ((v1 & mask) == (v2 & mask))
1038                         out_val |= mask;
1039         }
1040         op->val = out_val;
1041 }
1042
1043 /*
1044  * The size parameter is used to adjust the equivalent popcnt instruction.
1045  * popcntb = 8, popcntw = 32, popcntd = 64
1046  */
1047 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1048                                       struct instruction_op *op,
1049                                       unsigned long v1, int size)
1050 {
1051         unsigned long long out = v1;
1052
1053         out -= (out >> 1) & 0x5555555555555555;
1054         out = (0x3333333333333333 & out) + (0x3333333333333333 & (out >> 2));
1055         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0f;
1056
1057         if (size == 8) {        /* popcntb */
1058                 op->val = out;
1059                 return;
1060         }
1061         out += out >> 8;
1062         out += out >> 16;
1063         if (size == 32) {       /* popcntw */
1064                 op->val = out & 0x0000003f0000003f;
1065                 return;
1066         }
1067
1068         out = (out + (out >> 32)) & 0x7f;
1069         op->val = out;  /* popcntd */
1070 }
1071
1072 #ifdef CONFIG_PPC64
1073 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1074                                       struct instruction_op *op,
1075                                       unsigned long v1, unsigned long v2)
1076 {
1077         unsigned char perm, idx;
1078         unsigned int i;
1079
1080         perm = 0;
1081         for (i = 0; i < 8; i++) {
1082                 idx = (v1 >> (i * 8)) & 0xff;
1083                 if (idx < 64)
1084                         if (v2 & PPC_BIT(idx))
1085                                 perm |= 1 << i;
1086         }
1087         op->val = perm;
1088 }
1089 #endif /* CONFIG_PPC64 */
1090 /*
1091  * The size parameter adjusts the equivalent prty instruction.
1092  * prtyw = 32, prtyd = 64
1093  */
1094 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1095                                     struct instruction_op *op,
1096                                     unsigned long v, int size)
1097 {
1098         unsigned long long res = v ^ (v >> 8);
1099
1100         res ^= res >> 16;
1101         if (size == 32) {               /* prtyw */
1102                 op->val = res & 0x0000000100000001;
1103                 return;
1104         }
1105
1106         res ^= res >> 32;
1107         op->val = res & 1;      /*prtyd */
1108 }
1109
1110 static nokprobe_inline int trap_compare(long v1, long v2)
1111 {
1112         int ret = 0;
1113
1114         if (v1 < v2)
1115                 ret |= 0x10;
1116         else if (v1 > v2)
1117                 ret |= 0x08;
1118         else
1119                 ret |= 0x04;
1120         if ((unsigned long)v1 < (unsigned long)v2)
1121                 ret |= 0x02;
1122         else if ((unsigned long)v1 > (unsigned long)v2)
1123                 ret |= 0x01;
1124         return ret;
1125 }
1126
1127 /*
1128  * Elements of 32-bit rotate and mask instructions.
1129  */
1130 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
1131                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1132 #ifdef __powerpc64__
1133 #define MASK64_L(mb)    (~0UL >> (mb))
1134 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
1135 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1136 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1137 #else
1138 #define DATA32(x)       (x)
1139 #endif
1140 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1141
1142 /*
1143  * Decode an instruction, and return information about it in *op
1144  * without changing *regs.
1145  * Integer arithmetic and logical instructions, branches, and barrier
1146  * instructions can be emulated just using the information in *op.
1147  *
1148  * Return value is 1 if the instruction can be emulated just by
1149  * updating *regs with the information in *op, -1 if we need the
1150  * GPRs but *regs doesn't contain the full register set, or 0
1151  * otherwise.
1152  */
1153 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1154                   unsigned int instr)
1155 {
1156         unsigned int opcode, ra, rb, rd, spr, u;
1157         unsigned long int imm;
1158         unsigned long int val, val2;
1159         unsigned int mb, me, sh;
1160         long ival;
1161
1162         op->type = COMPUTE;
1163
1164         opcode = instr >> 26;
1165         switch (opcode) {
1166         case 16:        /* bc */
1167                 op->type = BRANCH;
1168                 imm = (signed short)(instr & 0xfffc);
1169                 if ((instr & 2) == 0)
1170                         imm += regs->nip;
1171                 op->val = truncate_if_32bit(regs->msr, imm);
1172                 if (instr & 1)
1173                         op->type |= SETLK;
1174                 if (branch_taken(instr, regs, op))
1175                         op->type |= BRTAKEN;
1176                 return 1;
1177 #ifdef CONFIG_PPC64
1178         case 17:        /* sc */
1179                 if ((instr & 0xfe2) == 2)
1180                         op->type = SYSCALL;
1181                 else
1182                         op->type = UNKNOWN;
1183                 return 0;
1184 #endif
1185         case 18:        /* b */
1186                 op->type = BRANCH | BRTAKEN;
1187                 imm = instr & 0x03fffffc;
1188                 if (imm & 0x02000000)
1189                         imm -= 0x04000000;
1190                 if ((instr & 2) == 0)
1191                         imm += regs->nip;
1192                 op->val = truncate_if_32bit(regs->msr, imm);
1193                 if (instr & 1)
1194                         op->type |= SETLK;
1195                 return 1;
1196         case 19:
1197                 switch ((instr >> 1) & 0x3ff) {
1198                 case 0:         /* mcrf */
1199                         op->type = COMPUTE + SETCC;
1200                         rd = 7 - ((instr >> 23) & 0x7);
1201                         ra = 7 - ((instr >> 18) & 0x7);
1202                         rd *= 4;
1203                         ra *= 4;
1204                         val = (regs->ccr >> ra) & 0xf;
1205                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1206                         return 1;
1207
1208                 case 16:        /* bclr */
1209                 case 528:       /* bcctr */
1210                         op->type = BRANCH;
1211                         imm = (instr & 0x400)? regs->ctr: regs->link;
1212                         op->val = truncate_if_32bit(regs->msr, imm);
1213                         if (instr & 1)
1214                                 op->type |= SETLK;
1215                         if (branch_taken(instr, regs, op))
1216                                 op->type |= BRTAKEN;
1217                         return 1;
1218
1219                 case 18:        /* rfid, scary */
1220                         if (regs->msr & MSR_PR)
1221                                 goto priv;
1222                         op->type = RFI;
1223                         return 0;
1224
1225                 case 150:       /* isync */
1226                         op->type = BARRIER | BARRIER_ISYNC;
1227                         return 1;
1228
1229                 case 33:        /* crnor */
1230                 case 129:       /* crandc */
1231                 case 193:       /* crxor */
1232                 case 225:       /* crnand */
1233                 case 257:       /* crand */
1234                 case 289:       /* creqv */
1235                 case 417:       /* crorc */
1236                 case 449:       /* cror */
1237                         op->type = COMPUTE + SETCC;
1238                         ra = (instr >> 16) & 0x1f;
1239                         rb = (instr >> 11) & 0x1f;
1240                         rd = (instr >> 21) & 0x1f;
1241                         ra = (regs->ccr >> (31 - ra)) & 1;
1242                         rb = (regs->ccr >> (31 - rb)) & 1;
1243                         val = (instr >> (6 + ra * 2 + rb)) & 1;
1244                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1245                                 (val << (31 - rd));
1246                         return 1;
1247                 }
1248                 break;
1249         case 31:
1250                 switch ((instr >> 1) & 0x3ff) {
1251                 case 598:       /* sync */
1252                         op->type = BARRIER + BARRIER_SYNC;
1253 #ifdef __powerpc64__
1254                         switch ((instr >> 21) & 3) {
1255                         case 1:         /* lwsync */
1256                                 op->type = BARRIER + BARRIER_LWSYNC;
1257                                 break;
1258                         case 2:         /* ptesync */
1259                                 op->type = BARRIER + BARRIER_PTESYNC;
1260                                 break;
1261                         }
1262 #endif
1263                         return 1;
1264
1265                 case 854:       /* eieio */
1266                         op->type = BARRIER + BARRIER_EIEIO;
1267                         return 1;
1268                 }
1269                 break;
1270         }
1271
1272         /* Following cases refer to regs->gpr[], so we need all regs */
1273         if (!FULL_REGS(regs))
1274                 return -1;
1275
1276         rd = (instr >> 21) & 0x1f;
1277         ra = (instr >> 16) & 0x1f;
1278         rb = (instr >> 11) & 0x1f;
1279
1280         switch (opcode) {
1281 #ifdef __powerpc64__
1282         case 2:         /* tdi */
1283                 if (rd & trap_compare(regs->gpr[ra], (short) instr))
1284                         goto trap;
1285                 return 1;
1286 #endif
1287         case 3:         /* twi */
1288                 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1289                         goto trap;
1290                 return 1;
1291
1292         case 7:         /* mulli */
1293                 op->val = regs->gpr[ra] * (short) instr;
1294                 goto compute_done;
1295
1296         case 8:         /* subfic */
1297                 imm = (short) instr;
1298                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1299                 return 1;
1300
1301         case 10:        /* cmpli */
1302                 imm = (unsigned short) instr;
1303                 val = regs->gpr[ra];
1304 #ifdef __powerpc64__
1305                 if ((rd & 1) == 0)
1306                         val = (unsigned int) val;
1307 #endif
1308                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1309                 return 1;
1310
1311         case 11:        /* cmpi */
1312                 imm = (short) instr;
1313                 val = regs->gpr[ra];
1314 #ifdef __powerpc64__
1315                 if ((rd & 1) == 0)
1316                         val = (int) val;
1317 #endif
1318                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1319                 return 1;
1320
1321         case 12:        /* addic */
1322                 imm = (short) instr;
1323                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1324                 return 1;
1325
1326         case 13:        /* addic. */
1327                 imm = (short) instr;
1328                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1329                 set_cr0(regs, op);
1330                 return 1;
1331
1332         case 14:        /* addi */
1333                 imm = (short) instr;
1334                 if (ra)
1335                         imm += regs->gpr[ra];
1336                 op->val = imm;
1337                 goto compute_done;
1338
1339         case 15:        /* addis */
1340                 imm = ((short) instr) << 16;
1341                 if (ra)
1342                         imm += regs->gpr[ra];
1343                 op->val = imm;
1344                 goto compute_done;
1345
1346         case 19:
1347                 if (((instr >> 1) & 0x1f) == 2) {
1348                         /* addpcis */
1349                         imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
1350                         imm |= (instr >> 15) & 0x3e;    /* d1 field */
1351                         op->val = regs->nip + (imm << 16) + 4;
1352                         goto compute_done;
1353                 }
1354                 op->type = UNKNOWN;
1355                 return 0;
1356
1357         case 20:        /* rlwimi */
1358                 mb = (instr >> 6) & 0x1f;
1359                 me = (instr >> 1) & 0x1f;
1360                 val = DATA32(regs->gpr[rd]);
1361                 imm = MASK32(mb, me);
1362                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1363                 goto logical_done;
1364
1365         case 21:        /* rlwinm */
1366                 mb = (instr >> 6) & 0x1f;
1367                 me = (instr >> 1) & 0x1f;
1368                 val = DATA32(regs->gpr[rd]);
1369                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1370                 goto logical_done;
1371
1372         case 23:        /* rlwnm */
1373                 mb = (instr >> 6) & 0x1f;
1374                 me = (instr >> 1) & 0x1f;
1375                 rb = regs->gpr[rb] & 0x1f;
1376                 val = DATA32(regs->gpr[rd]);
1377                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1378                 goto logical_done;
1379
1380         case 24:        /* ori */
1381                 op->val = regs->gpr[rd] | (unsigned short) instr;
1382                 goto logical_done_nocc;
1383
1384         case 25:        /* oris */
1385                 imm = (unsigned short) instr;
1386                 op->val = regs->gpr[rd] | (imm << 16);
1387                 goto logical_done_nocc;
1388
1389         case 26:        /* xori */
1390                 op->val = regs->gpr[rd] ^ (unsigned short) instr;
1391                 goto logical_done_nocc;
1392
1393         case 27:        /* xoris */
1394                 imm = (unsigned short) instr;
1395                 op->val = regs->gpr[rd] ^ (imm << 16);
1396                 goto logical_done_nocc;
1397
1398         case 28:        /* andi. */
1399                 op->val = regs->gpr[rd] & (unsigned short) instr;
1400                 set_cr0(regs, op);
1401                 goto logical_done_nocc;
1402
1403         case 29:        /* andis. */
1404                 imm = (unsigned short) instr;
1405                 op->val = regs->gpr[rd] & (imm << 16);
1406                 set_cr0(regs, op);
1407                 goto logical_done_nocc;
1408
1409 #ifdef __powerpc64__
1410         case 30:        /* rld* */
1411                 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1412                 val = regs->gpr[rd];
1413                 if ((instr & 0x10) == 0) {
1414                         sh = rb | ((instr & 2) << 4);
1415                         val = ROTATE(val, sh);
1416                         switch ((instr >> 2) & 3) {
1417                         case 0:         /* rldicl */
1418                                 val &= MASK64_L(mb);
1419                                 break;
1420                         case 1:         /* rldicr */
1421                                 val &= MASK64_R(mb);
1422                                 break;
1423                         case 2:         /* rldic */
1424                                 val &= MASK64(mb, 63 - sh);
1425                                 break;
1426                         case 3:         /* rldimi */
1427                                 imm = MASK64(mb, 63 - sh);
1428                                 val = (regs->gpr[ra] & ~imm) |
1429                                         (val & imm);
1430                         }
1431                         op->val = val;
1432                         goto logical_done;
1433                 } else {
1434                         sh = regs->gpr[rb] & 0x3f;
1435                         val = ROTATE(val, sh);
1436                         switch ((instr >> 1) & 7) {
1437                         case 0:         /* rldcl */
1438                                 op->val = val & MASK64_L(mb);
1439                                 goto logical_done;
1440                         case 1:         /* rldcr */
1441                                 op->val = val & MASK64_R(mb);
1442                                 goto logical_done;
1443                         }
1444                 }
1445 #endif
1446                 op->type = UNKNOWN;     /* illegal instruction */
1447                 return 0;
1448
1449         case 31:
1450                 /* isel occupies 32 minor opcodes */
1451                 if (((instr >> 1) & 0x1f) == 15) {
1452                         mb = (instr >> 6) & 0x1f; /* bc field */
1453                         val = (regs->ccr >> (31 - mb)) & 1;
1454                         val2 = (ra) ? regs->gpr[ra] : 0;
1455
1456                         op->val = (val) ? val2 : regs->gpr[rb];
1457                         goto compute_done;
1458                 }
1459
1460                 switch ((instr >> 1) & 0x3ff) {
1461                 case 4:         /* tw */
1462                         if (rd == 0x1f ||
1463                             (rd & trap_compare((int)regs->gpr[ra],
1464                                                (int)regs->gpr[rb])))
1465                                 goto trap;
1466                         return 1;
1467 #ifdef __powerpc64__
1468                 case 68:        /* td */
1469                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1470                                 goto trap;
1471                         return 1;
1472 #endif
1473                 case 83:        /* mfmsr */
1474                         if (regs->msr & MSR_PR)
1475                                 goto priv;
1476                         op->type = MFMSR;
1477                         op->reg = rd;
1478                         return 0;
1479                 case 146:       /* mtmsr */
1480                         if (regs->msr & MSR_PR)
1481                                 goto priv;
1482                         op->type = MTMSR;
1483                         op->reg = rd;
1484                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1485                         return 0;
1486 #ifdef CONFIG_PPC64
1487                 case 178:       /* mtmsrd */
1488                         if (regs->msr & MSR_PR)
1489                                 goto priv;
1490                         op->type = MTMSR;
1491                         op->reg = rd;
1492                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1493                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1494                         imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1495                         op->val = imm;
1496                         return 0;
1497 #endif
1498
1499                 case 19:        /* mfcr */
1500                         imm = 0xffffffffUL;
1501                         if ((instr >> 20) & 1) {
1502                                 imm = 0xf0000000UL;
1503                                 for (sh = 0; sh < 8; ++sh) {
1504                                         if (instr & (0x80000 >> sh))
1505                                                 break;
1506                                         imm >>= 4;
1507                                 }
1508                         }
1509                         op->val = regs->ccr & imm;
1510                         goto compute_done;
1511
1512                 case 144:       /* mtcrf */
1513                         op->type = COMPUTE + SETCC;
1514                         imm = 0xf0000000UL;
1515                         val = regs->gpr[rd];
1516                         op->ccval = regs->ccr;
1517                         for (sh = 0; sh < 8; ++sh) {
1518                                 if (instr & (0x80000 >> sh))
1519                                         op->ccval = (op->ccval & ~imm) |
1520                                                 (val & imm);
1521                                 imm >>= 4;
1522                         }
1523                         return 1;
1524
1525                 case 339:       /* mfspr */
1526                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1527                         op->type = MFSPR;
1528                         op->reg = rd;
1529                         op->spr = spr;
1530                         if (spr == SPRN_XER || spr == SPRN_LR ||
1531                             spr == SPRN_CTR)
1532                                 return 1;
1533                         return 0;
1534
1535                 case 467:       /* mtspr */
1536                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1537                         op->type = MTSPR;
1538                         op->val = regs->gpr[rd];
1539                         op->spr = spr;
1540                         if (spr == SPRN_XER || spr == SPRN_LR ||
1541                             spr == SPRN_CTR)
1542                                 return 1;
1543                         return 0;
1544
1545 /*
1546  * Compare instructions
1547  */
1548                 case 0: /* cmp */
1549                         val = regs->gpr[ra];
1550                         val2 = regs->gpr[rb];
1551 #ifdef __powerpc64__
1552                         if ((rd & 1) == 0) {
1553                                 /* word (32-bit) compare */
1554                                 val = (int) val;
1555                                 val2 = (int) val2;
1556                         }
1557 #endif
1558                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1559                         return 1;
1560
1561                 case 32:        /* cmpl */
1562                         val = regs->gpr[ra];
1563                         val2 = regs->gpr[rb];
1564 #ifdef __powerpc64__
1565                         if ((rd & 1) == 0) {
1566                                 /* word (32-bit) compare */
1567                                 val = (unsigned int) val;
1568                                 val2 = (unsigned int) val2;
1569                         }
1570 #endif
1571                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1572                         return 1;
1573
1574                 case 508: /* cmpb */
1575                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1576                         goto logical_done_nocc;
1577
1578 /*
1579  * Arithmetic instructions
1580  */
1581                 case 8: /* subfc */
1582                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1583                                        regs->gpr[rb], 1);
1584                         goto arith_done;
1585 #ifdef __powerpc64__
1586                 case 9: /* mulhdu */
1587                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1588                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1589                         goto arith_done;
1590 #endif
1591                 case 10:        /* addc */
1592                         add_with_carry(regs, op, rd, regs->gpr[ra],
1593                                        regs->gpr[rb], 0);
1594                         goto arith_done;
1595
1596                 case 11:        /* mulhwu */
1597                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1598                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1599                         goto arith_done;
1600
1601                 case 40:        /* subf */
1602                         op->val = regs->gpr[rb] - regs->gpr[ra];
1603                         goto arith_done;
1604 #ifdef __powerpc64__
1605                 case 73:        /* mulhd */
1606                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1607                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1608                         goto arith_done;
1609 #endif
1610                 case 75:        /* mulhw */
1611                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1612                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1613                         goto arith_done;
1614
1615                 case 104:       /* neg */
1616                         op->val = -regs->gpr[ra];
1617                         goto arith_done;
1618
1619                 case 136:       /* subfe */
1620                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1621                                        regs->gpr[rb], regs->xer & XER_CA);
1622                         goto arith_done;
1623
1624                 case 138:       /* adde */
1625                         add_with_carry(regs, op, rd, regs->gpr[ra],
1626                                        regs->gpr[rb], regs->xer & XER_CA);
1627                         goto arith_done;
1628
1629                 case 200:       /* subfze */
1630                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1631                                        regs->xer & XER_CA);
1632                         goto arith_done;
1633
1634                 case 202:       /* addze */
1635                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1636                                        regs->xer & XER_CA);
1637                         goto arith_done;
1638
1639                 case 232:       /* subfme */
1640                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1641                                        regs->xer & XER_CA);
1642                         goto arith_done;
1643 #ifdef __powerpc64__
1644                 case 233:       /* mulld */
1645                         op->val = regs->gpr[ra] * regs->gpr[rb];
1646                         goto arith_done;
1647 #endif
1648                 case 234:       /* addme */
1649                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1650                                        regs->xer & XER_CA);
1651                         goto arith_done;
1652
1653                 case 235:       /* mullw */
1654                         op->val = (long)(int) regs->gpr[ra] *
1655                                 (int) regs->gpr[rb];
1656
1657                         goto arith_done;
1658
1659                 case 266:       /* add */
1660                         op->val = regs->gpr[ra] + regs->gpr[rb];
1661                         goto arith_done;
1662 #ifdef __powerpc64__
1663                 case 457:       /* divdu */
1664                         op->val = regs->gpr[ra] / regs->gpr[rb];
1665                         goto arith_done;
1666 #endif
1667                 case 459:       /* divwu */
1668                         op->val = (unsigned int) regs->gpr[ra] /
1669                                 (unsigned int) regs->gpr[rb];
1670                         goto arith_done;
1671 #ifdef __powerpc64__
1672                 case 489:       /* divd */
1673                         op->val = (long int) regs->gpr[ra] /
1674                                 (long int) regs->gpr[rb];
1675                         goto arith_done;
1676 #endif
1677                 case 491:       /* divw */
1678                         op->val = (int) regs->gpr[ra] /
1679                                 (int) regs->gpr[rb];
1680                         goto arith_done;
1681
1682
1683 /*
1684  * Logical instructions
1685  */
1686                 case 26:        /* cntlzw */
1687                         val = (unsigned int) regs->gpr[rd];
1688                         op->val = ( val ? __builtin_clz(val) : 32 );
1689                         goto logical_done;
1690 #ifdef __powerpc64__
1691                 case 58:        /* cntlzd */
1692                         val = regs->gpr[rd];
1693                         op->val = ( val ? __builtin_clzl(val) : 64 );
1694                         goto logical_done;
1695 #endif
1696                 case 28:        /* and */
1697                         op->val = regs->gpr[rd] & regs->gpr[rb];
1698                         goto logical_done;
1699
1700                 case 60:        /* andc */
1701                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1702                         goto logical_done;
1703
1704                 case 122:       /* popcntb */
1705                         do_popcnt(regs, op, regs->gpr[rd], 8);
1706                         goto logical_done_nocc;
1707
1708                 case 124:       /* nor */
1709                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1710                         goto logical_done;
1711
1712                 case 154:       /* prtyw */
1713                         do_prty(regs, op, regs->gpr[rd], 32);
1714                         goto logical_done_nocc;
1715
1716                 case 186:       /* prtyd */
1717                         do_prty(regs, op, regs->gpr[rd], 64);
1718                         goto logical_done_nocc;
1719 #ifdef CONFIG_PPC64
1720                 case 252:       /* bpermd */
1721                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1722                         goto logical_done_nocc;
1723 #endif
1724                 case 284:       /* xor */
1725                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1726                         goto logical_done;
1727
1728                 case 316:       /* xor */
1729                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
1730                         goto logical_done;
1731
1732                 case 378:       /* popcntw */
1733                         do_popcnt(regs, op, regs->gpr[rd], 32);
1734                         goto logical_done_nocc;
1735
1736                 case 412:       /* orc */
1737                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
1738                         goto logical_done;
1739
1740                 case 444:       /* or */
1741                         op->val = regs->gpr[rd] | regs->gpr[rb];
1742                         goto logical_done;
1743
1744                 case 476:       /* nand */
1745                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1746                         goto logical_done;
1747 #ifdef CONFIG_PPC64
1748                 case 506:       /* popcntd */
1749                         do_popcnt(regs, op, regs->gpr[rd], 64);
1750                         goto logical_done_nocc;
1751 #endif
1752                 case 922:       /* extsh */
1753                         op->val = (signed short) regs->gpr[rd];
1754                         goto logical_done;
1755
1756                 case 954:       /* extsb */
1757                         op->val = (signed char) regs->gpr[rd];
1758                         goto logical_done;
1759 #ifdef __powerpc64__
1760                 case 986:       /* extsw */
1761                         op->val = (signed int) regs->gpr[rd];
1762                         goto logical_done;
1763 #endif
1764
1765 /*
1766  * Shift instructions
1767  */
1768                 case 24:        /* slw */
1769                         sh = regs->gpr[rb] & 0x3f;
1770                         if (sh < 32)
1771                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1772                         else
1773                                 op->val = 0;
1774                         goto logical_done;
1775
1776                 case 536:       /* srw */
1777                         sh = regs->gpr[rb] & 0x3f;
1778                         if (sh < 32)
1779                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1780                         else
1781                                 op->val = 0;
1782                         goto logical_done;
1783
1784                 case 792:       /* sraw */
1785                         op->type = COMPUTE + SETREG + SETXER;
1786                         sh = regs->gpr[rb] & 0x3f;
1787                         ival = (signed int) regs->gpr[rd];
1788                         op->val = ival >> (sh < 32 ? sh : 31);
1789                         op->xerval = regs->xer;
1790                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1791                                 op->xerval |= XER_CA;
1792                         else
1793                                 op->xerval &= ~XER_CA;
1794                         goto logical_done;
1795
1796                 case 824:       /* srawi */
1797                         op->type = COMPUTE + SETREG + SETXER;
1798                         sh = rb;
1799                         ival = (signed int) regs->gpr[rd];
1800                         op->val = ival >> sh;
1801                         op->xerval = regs->xer;
1802                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1803                                 op->xerval |= XER_CA;
1804                         else
1805                                 op->xerval &= ~XER_CA;
1806                         goto logical_done;
1807
1808 #ifdef __powerpc64__
1809                 case 27:        /* sld */
1810                         sh = regs->gpr[rb] & 0x7f;
1811                         if (sh < 64)
1812                                 op->val = regs->gpr[rd] << sh;
1813                         else
1814                                 op->val = 0;
1815                         goto logical_done;
1816
1817                 case 539:       /* srd */
1818                         sh = regs->gpr[rb] & 0x7f;
1819                         if (sh < 64)
1820                                 op->val = regs->gpr[rd] >> sh;
1821                         else
1822                                 op->val = 0;
1823                         goto logical_done;
1824
1825                 case 794:       /* srad */
1826                         op->type = COMPUTE + SETREG + SETXER;
1827                         sh = regs->gpr[rb] & 0x7f;
1828                         ival = (signed long int) regs->gpr[rd];
1829                         op->val = ival >> (sh < 64 ? sh : 63);
1830                         op->xerval = regs->xer;
1831                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
1832                                 op->xerval |= XER_CA;
1833                         else
1834                                 op->xerval &= ~XER_CA;
1835                         goto logical_done;
1836
1837                 case 826:       /* sradi with sh_5 = 0 */
1838                 case 827:       /* sradi with sh_5 = 1 */
1839                         op->type = COMPUTE + SETREG + SETXER;
1840                         sh = rb | ((instr & 2) << 4);
1841                         ival = (signed long int) regs->gpr[rd];
1842                         op->val = ival >> sh;
1843                         op->xerval = regs->xer;
1844                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1845                                 op->xerval |= XER_CA;
1846                         else
1847                                 op->xerval &= ~XER_CA;
1848                         goto logical_done;
1849 #endif /* __powerpc64__ */
1850
1851 /*
1852  * Cache instructions
1853  */
1854                 case 54:        /* dcbst */
1855                         op->type = MKOP(CACHEOP, DCBST, 0);
1856                         op->ea = xform_ea(instr, regs);
1857                         return 0;
1858
1859                 case 86:        /* dcbf */
1860                         op->type = MKOP(CACHEOP, DCBF, 0);
1861                         op->ea = xform_ea(instr, regs);
1862                         return 0;
1863
1864                 case 246:       /* dcbtst */
1865                         op->type = MKOP(CACHEOP, DCBTST, 0);
1866                         op->ea = xform_ea(instr, regs);
1867                         op->reg = rd;
1868                         return 0;
1869
1870                 case 278:       /* dcbt */
1871                         op->type = MKOP(CACHEOP, DCBTST, 0);
1872                         op->ea = xform_ea(instr, regs);
1873                         op->reg = rd;
1874                         return 0;
1875
1876                 case 982:       /* icbi */
1877                         op->type = MKOP(CACHEOP, ICBI, 0);
1878                         op->ea = xform_ea(instr, regs);
1879                         return 0;
1880
1881                 case 1014:      /* dcbz */
1882                         op->type = MKOP(CACHEOP, DCBZ, 0);
1883                         op->ea = xform_ea(instr, regs);
1884                         return 0;
1885                 }
1886                 break;
1887         }
1888
1889 /*
1890  * Loads and stores.
1891  */
1892         op->type = UNKNOWN;
1893         op->update_reg = ra;
1894         op->reg = rd;
1895         op->val = regs->gpr[rd];
1896         u = (instr >> 20) & UPDATE;
1897         op->vsx_flags = 0;
1898
1899         switch (opcode) {
1900         case 31:
1901                 u = instr & UPDATE;
1902                 op->ea = xform_ea(instr, regs);
1903                 switch ((instr >> 1) & 0x3ff) {
1904                 case 20:        /* lwarx */
1905                         op->type = MKOP(LARX, 0, 4);
1906                         break;
1907
1908                 case 150:       /* stwcx. */
1909                         op->type = MKOP(STCX, 0, 4);
1910                         break;
1911
1912 #ifdef __powerpc64__
1913                 case 84:        /* ldarx */
1914                         op->type = MKOP(LARX, 0, 8);
1915                         break;
1916
1917                 case 214:       /* stdcx. */
1918                         op->type = MKOP(STCX, 0, 8);
1919                         break;
1920
1921                 case 52:        /* lbarx */
1922                         op->type = MKOP(LARX, 0, 1);
1923                         break;
1924
1925                 case 694:       /* stbcx. */
1926                         op->type = MKOP(STCX, 0, 1);
1927                         break;
1928
1929                 case 116:       /* lharx */
1930                         op->type = MKOP(LARX, 0, 2);
1931                         break;
1932
1933                 case 726:       /* sthcx. */
1934                         op->type = MKOP(STCX, 0, 2);
1935                         break;
1936
1937                 case 276:       /* lqarx */
1938                         if (!((rd & 1) || rd == ra || rd == rb))
1939                                 op->type = MKOP(LARX, 0, 16);
1940                         break;
1941
1942                 case 182:       /* stqcx. */
1943                         if (!(rd & 1))
1944                                 op->type = MKOP(STCX, 0, 16);
1945                         break;
1946 #endif
1947
1948                 case 23:        /* lwzx */
1949                 case 55:        /* lwzux */
1950                         op->type = MKOP(LOAD, u, 4);
1951                         break;
1952
1953                 case 87:        /* lbzx */
1954                 case 119:       /* lbzux */
1955                         op->type = MKOP(LOAD, u, 1);
1956                         break;
1957
1958 #ifdef CONFIG_ALTIVEC
1959                 /*
1960                  * Note: for the load/store vector element instructions,
1961                  * bits of the EA say which field of the VMX register to use.
1962                  */
1963                 case 7:         /* lvebx */
1964                         op->type = MKOP(LOAD_VMX, 0, 1);
1965                         op->element_size = 1;
1966                         break;
1967
1968                 case 39:        /* lvehx */
1969                         op->type = MKOP(LOAD_VMX, 0, 2);
1970                         op->element_size = 2;
1971                         break;
1972
1973                 case 71:        /* lvewx */
1974                         op->type = MKOP(LOAD_VMX, 0, 4);
1975                         op->element_size = 4;
1976                         break;
1977
1978                 case 103:       /* lvx */
1979                 case 359:       /* lvxl */
1980                         op->type = MKOP(LOAD_VMX, 0, 16);
1981                         op->element_size = 16;
1982                         break;
1983
1984                 case 135:       /* stvebx */
1985                         op->type = MKOP(STORE_VMX, 0, 1);
1986                         op->element_size = 1;
1987                         break;
1988
1989                 case 167:       /* stvehx */
1990                         op->type = MKOP(STORE_VMX, 0, 2);
1991                         op->element_size = 2;
1992                         break;
1993
1994                 case 199:       /* stvewx */
1995                         op->type = MKOP(STORE_VMX, 0, 4);
1996                         op->element_size = 4;
1997                         break;
1998
1999                 case 231:       /* stvx */
2000                 case 487:       /* stvxl */
2001                         op->type = MKOP(STORE_VMX, 0, 16);
2002                         break;
2003 #endif /* CONFIG_ALTIVEC */
2004
2005 #ifdef __powerpc64__
2006                 case 21:        /* ldx */
2007                 case 53:        /* ldux */
2008                         op->type = MKOP(LOAD, u, 8);
2009                         break;
2010
2011                 case 149:       /* stdx */
2012                 case 181:       /* stdux */
2013                         op->type = MKOP(STORE, u, 8);
2014                         break;
2015 #endif
2016
2017                 case 151:       /* stwx */
2018                 case 183:       /* stwux */
2019                         op->type = MKOP(STORE, u, 4);
2020                         break;
2021
2022                 case 215:       /* stbx */
2023                 case 247:       /* stbux */
2024                         op->type = MKOP(STORE, u, 1);
2025                         break;
2026
2027                 case 279:       /* lhzx */
2028                 case 311:       /* lhzux */
2029                         op->type = MKOP(LOAD, u, 2);
2030                         break;
2031
2032 #ifdef __powerpc64__
2033                 case 341:       /* lwax */
2034                 case 373:       /* lwaux */
2035                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
2036                         break;
2037 #endif
2038
2039                 case 343:       /* lhax */
2040                 case 375:       /* lhaux */
2041                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
2042                         break;
2043
2044                 case 407:       /* sthx */
2045                 case 439:       /* sthux */
2046                         op->type = MKOP(STORE, u, 2);
2047                         break;
2048
2049 #ifdef __powerpc64__
2050                 case 532:       /* ldbrx */
2051                         op->type = MKOP(LOAD, BYTEREV, 8);
2052                         break;
2053
2054 #endif
2055                 case 533:       /* lswx */
2056                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2057                         break;
2058
2059                 case 534:       /* lwbrx */
2060                         op->type = MKOP(LOAD, BYTEREV, 4);
2061                         break;
2062
2063                 case 597:       /* lswi */
2064                         if (rb == 0)
2065                                 rb = 32;        /* # bytes to load */
2066                         op->type = MKOP(LOAD_MULTI, 0, rb);
2067                         op->ea = ra ? regs->gpr[ra] : 0;
2068                         break;
2069
2070 #ifdef CONFIG_PPC_FPU
2071                 case 535:       /* lfsx */
2072                 case 567:       /* lfsux */
2073                         op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2074                         break;
2075
2076                 case 599:       /* lfdx */
2077                 case 631:       /* lfdux */
2078                         op->type = MKOP(LOAD_FP, u, 8);
2079                         break;
2080
2081                 case 663:       /* stfsx */
2082                 case 695:       /* stfsux */
2083                         op->type = MKOP(STORE_FP, u | FPCONV, 4);
2084                         break;
2085
2086                 case 727:       /* stfdx */
2087                 case 759:       /* stfdux */
2088                         op->type = MKOP(STORE_FP, u, 8);
2089                         break;
2090
2091 #ifdef __powerpc64__
2092                 case 791:       /* lfdpx */
2093                         op->type = MKOP(LOAD_FP, 0, 16);
2094                         break;
2095
2096                 case 855:       /* lfiwax */
2097                         op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2098                         break;
2099
2100                 case 887:       /* lfiwzx */
2101                         op->type = MKOP(LOAD_FP, 0, 4);
2102                         break;
2103
2104                 case 919:       /* stfdpx */
2105                         op->type = MKOP(STORE_FP, 0, 16);
2106                         break;
2107
2108                 case 983:       /* stfiwx */
2109                         op->type = MKOP(STORE_FP, 0, 4);
2110                         break;
2111 #endif /* __powerpc64 */
2112 #endif /* CONFIG_PPC_FPU */
2113
2114 #ifdef __powerpc64__
2115                 case 660:       /* stdbrx */
2116                         op->type = MKOP(STORE, BYTEREV, 8);
2117                         op->val = byterev_8(regs->gpr[rd]);
2118                         break;
2119
2120 #endif
2121                 case 661:       /* stswx */
2122                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2123                         break;
2124
2125                 case 662:       /* stwbrx */
2126                         op->type = MKOP(STORE, BYTEREV, 4);
2127                         op->val = byterev_4(regs->gpr[rd]);
2128                         break;
2129
2130                 case 725:       /* stswi */
2131                         if (rb == 0)
2132                                 rb = 32;        /* # bytes to store */
2133                         op->type = MKOP(STORE_MULTI, 0, rb);
2134                         op->ea = ra ? regs->gpr[ra] : 0;
2135                         break;
2136
2137                 case 790:       /* lhbrx */
2138                         op->type = MKOP(LOAD, BYTEREV, 2);
2139                         break;
2140
2141                 case 918:       /* sthbrx */
2142                         op->type = MKOP(STORE, BYTEREV, 2);
2143                         op->val = byterev_2(regs->gpr[rd]);
2144                         break;
2145
2146 #ifdef CONFIG_VSX
2147                 case 12:        /* lxsiwzx */
2148                         op->reg = rd | ((instr & 1) << 5);
2149                         op->type = MKOP(LOAD_VSX, 0, 4);
2150                         op->element_size = 8;
2151                         break;
2152
2153                 case 76:        /* lxsiwax */
2154                         op->reg = rd | ((instr & 1) << 5);
2155                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2156                         op->element_size = 8;
2157                         break;
2158
2159                 case 140:       /* stxsiwx */
2160                         op->reg = rd | ((instr & 1) << 5);
2161                         op->type = MKOP(STORE_VSX, 0, 4);
2162                         op->element_size = 8;
2163                         break;
2164
2165                 case 268:       /* lxvx */
2166                         op->reg = rd | ((instr & 1) << 5);
2167                         op->type = MKOP(LOAD_VSX, 0, 16);
2168                         op->element_size = 16;
2169                         op->vsx_flags = VSX_CHECK_VEC;
2170                         break;
2171
2172                 case 269:       /* lxvl */
2173                 case 301: {     /* lxvll */
2174                         int nb;
2175                         op->reg = rd | ((instr & 1) << 5);
2176                         op->ea = ra ? regs->gpr[ra] : 0;
2177                         nb = regs->gpr[rb] & 0xff;
2178                         if (nb > 16)
2179                                 nb = 16;
2180                         op->type = MKOP(LOAD_VSX, 0, nb);
2181                         op->element_size = 16;
2182                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2183                                 VSX_CHECK_VEC;
2184                         break;
2185                 }
2186                 case 332:       /* lxvdsx */
2187                         op->reg = rd | ((instr & 1) << 5);
2188                         op->type = MKOP(LOAD_VSX, 0, 8);
2189                         op->element_size = 8;
2190                         op->vsx_flags = VSX_SPLAT;
2191                         break;
2192
2193                 case 364:       /* lxvwsx */
2194                         op->reg = rd | ((instr & 1) << 5);
2195                         op->type = MKOP(LOAD_VSX, 0, 4);
2196                         op->element_size = 4;
2197                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2198                         break;
2199
2200                 case 396:       /* stxvx */
2201                         op->reg = rd | ((instr & 1) << 5);
2202                         op->type = MKOP(STORE_VSX, 0, 16);
2203                         op->element_size = 16;
2204                         op->vsx_flags = VSX_CHECK_VEC;
2205                         break;
2206
2207                 case 397:       /* stxvl */
2208                 case 429: {     /* stxvll */
2209                         int nb;
2210                         op->reg = rd | ((instr & 1) << 5);
2211                         op->ea = ra ? regs->gpr[ra] : 0;
2212                         nb = regs->gpr[rb] & 0xff;
2213                         if (nb > 16)
2214                                 nb = 16;
2215                         op->type = MKOP(STORE_VSX, 0, nb);
2216                         op->element_size = 16;
2217                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2218                                 VSX_CHECK_VEC;
2219                         break;
2220                 }
2221                 case 524:       /* lxsspx */
2222                         op->reg = rd | ((instr & 1) << 5);
2223                         op->type = MKOP(LOAD_VSX, 0, 4);
2224                         op->element_size = 8;
2225                         op->vsx_flags = VSX_FPCONV;
2226                         break;
2227
2228                 case 588:       /* lxsdx */
2229                         op->reg = rd | ((instr & 1) << 5);
2230                         op->type = MKOP(LOAD_VSX, 0, 8);
2231                         op->element_size = 8;
2232                         break;
2233
2234                 case 652:       /* stxsspx */
2235                         op->reg = rd | ((instr & 1) << 5);
2236                         op->type = MKOP(STORE_VSX, 0, 4);
2237                         op->element_size = 8;
2238                         op->vsx_flags = VSX_FPCONV;
2239                         break;
2240
2241                 case 716:       /* stxsdx */
2242                         op->reg = rd | ((instr & 1) << 5);
2243                         op->type = MKOP(STORE_VSX, 0, 8);
2244                         op->element_size = 8;
2245                         break;
2246
2247                 case 780:       /* lxvw4x */
2248                         op->reg = rd | ((instr & 1) << 5);
2249                         op->type = MKOP(LOAD_VSX, 0, 16);
2250                         op->element_size = 4;
2251                         break;
2252
2253                 case 781:       /* lxsibzx */
2254                         op->reg = rd | ((instr & 1) << 5);
2255                         op->type = MKOP(LOAD_VSX, 0, 1);
2256                         op->element_size = 8;
2257                         op->vsx_flags = VSX_CHECK_VEC;
2258                         break;
2259
2260                 case 812:       /* lxvh8x */
2261                         op->reg = rd | ((instr & 1) << 5);
2262                         op->type = MKOP(LOAD_VSX, 0, 16);
2263                         op->element_size = 2;
2264                         op->vsx_flags = VSX_CHECK_VEC;
2265                         break;
2266
2267                 case 813:       /* lxsihzx */
2268                         op->reg = rd | ((instr & 1) << 5);
2269                         op->type = MKOP(LOAD_VSX, 0, 2);
2270                         op->element_size = 8;
2271                         op->vsx_flags = VSX_CHECK_VEC;
2272                         break;
2273
2274                 case 844:       /* lxvd2x */
2275                         op->reg = rd | ((instr & 1) << 5);
2276                         op->type = MKOP(LOAD_VSX, 0, 16);
2277                         op->element_size = 8;
2278                         break;
2279
2280                 case 876:       /* lxvb16x */
2281                         op->reg = rd | ((instr & 1) << 5);
2282                         op->type = MKOP(LOAD_VSX, 0, 16);
2283                         op->element_size = 1;
2284                         op->vsx_flags = VSX_CHECK_VEC;
2285                         break;
2286
2287                 case 908:       /* stxvw4x */
2288                         op->reg = rd | ((instr & 1) << 5);
2289                         op->type = MKOP(STORE_VSX, 0, 16);
2290                         op->element_size = 4;
2291                         break;
2292
2293                 case 909:       /* stxsibx */
2294                         op->reg = rd | ((instr & 1) << 5);
2295                         op->type = MKOP(STORE_VSX, 0, 1);
2296                         op->element_size = 8;
2297                         op->vsx_flags = VSX_CHECK_VEC;
2298                         break;
2299
2300                 case 940:       /* stxvh8x */
2301                         op->reg = rd | ((instr & 1) << 5);
2302                         op->type = MKOP(STORE_VSX, 0, 16);
2303                         op->element_size = 2;
2304                         op->vsx_flags = VSX_CHECK_VEC;
2305                         break;
2306
2307                 case 941:       /* stxsihx */
2308                         op->reg = rd | ((instr & 1) << 5);
2309                         op->type = MKOP(STORE_VSX, 0, 2);
2310                         op->element_size = 8;
2311                         op->vsx_flags = VSX_CHECK_VEC;
2312                         break;
2313
2314                 case 972:       /* stxvd2x */
2315                         op->reg = rd | ((instr & 1) << 5);
2316                         op->type = MKOP(STORE_VSX, 0, 16);
2317                         op->element_size = 8;
2318                         break;
2319
2320                 case 1004:      /* stxvb16x */
2321                         op->reg = rd | ((instr & 1) << 5);
2322                         op->type = MKOP(STORE_VSX, 0, 16);
2323                         op->element_size = 1;
2324                         op->vsx_flags = VSX_CHECK_VEC;
2325                         break;
2326
2327 #endif /* CONFIG_VSX */
2328                 }
2329                 break;
2330
2331         case 32:        /* lwz */
2332         case 33:        /* lwzu */
2333                 op->type = MKOP(LOAD, u, 4);
2334                 op->ea = dform_ea(instr, regs);
2335                 break;
2336
2337         case 34:        /* lbz */
2338         case 35:        /* lbzu */
2339                 op->type = MKOP(LOAD, u, 1);
2340                 op->ea = dform_ea(instr, regs);
2341                 break;
2342
2343         case 36:        /* stw */
2344         case 37:        /* stwu */
2345                 op->type = MKOP(STORE, u, 4);
2346                 op->ea = dform_ea(instr, regs);
2347                 break;
2348
2349         case 38:        /* stb */
2350         case 39:        /* stbu */
2351                 op->type = MKOP(STORE, u, 1);
2352                 op->ea = dform_ea(instr, regs);
2353                 break;
2354
2355         case 40:        /* lhz */
2356         case 41:        /* lhzu */
2357                 op->type = MKOP(LOAD, u, 2);
2358                 op->ea = dform_ea(instr, regs);
2359                 break;
2360
2361         case 42:        /* lha */
2362         case 43:        /* lhau */
2363                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2364                 op->ea = dform_ea(instr, regs);
2365                 break;
2366
2367         case 44:        /* sth */
2368         case 45:        /* sthu */
2369                 op->type = MKOP(STORE, u, 2);
2370                 op->ea = dform_ea(instr, regs);
2371                 break;
2372
2373         case 46:        /* lmw */
2374                 if (ra >= rd)
2375                         break;          /* invalid form, ra in range to load */
2376                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2377                 op->ea = dform_ea(instr, regs);
2378                 break;
2379
2380         case 47:        /* stmw */
2381                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2382                 op->ea = dform_ea(instr, regs);
2383                 break;
2384
2385 #ifdef CONFIG_PPC_FPU
2386         case 48:        /* lfs */
2387         case 49:        /* lfsu */
2388                 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2389                 op->ea = dform_ea(instr, regs);
2390                 break;
2391
2392         case 50:        /* lfd */
2393         case 51:        /* lfdu */
2394                 op->type = MKOP(LOAD_FP, u, 8);
2395                 op->ea = dform_ea(instr, regs);
2396                 break;
2397
2398         case 52:        /* stfs */
2399         case 53:        /* stfsu */
2400                 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2401                 op->ea = dform_ea(instr, regs);
2402                 break;
2403
2404         case 54:        /* stfd */
2405         case 55:        /* stfdu */
2406                 op->type = MKOP(STORE_FP, u, 8);
2407                 op->ea = dform_ea(instr, regs);
2408                 break;
2409 #endif
2410
2411 #ifdef __powerpc64__
2412         case 56:        /* lq */
2413                 if (!((rd & 1) || (rd == ra)))
2414                         op->type = MKOP(LOAD, 0, 16);
2415                 op->ea = dqform_ea(instr, regs);
2416                 break;
2417 #endif
2418
2419 #ifdef CONFIG_VSX
2420         case 57:        /* lfdp, lxsd, lxssp */
2421                 op->ea = dsform_ea(instr, regs);
2422                 switch (instr & 3) {
2423                 case 0:         /* lfdp */
2424                         if (rd & 1)
2425                                 break;          /* reg must be even */
2426                         op->type = MKOP(LOAD_FP, 0, 16);
2427                         break;
2428                 case 2:         /* lxsd */
2429                         op->reg = rd + 32;
2430                         op->type = MKOP(LOAD_VSX, 0, 8);
2431                         op->element_size = 8;
2432                         op->vsx_flags = VSX_CHECK_VEC;
2433                         break;
2434                 case 3:         /* lxssp */
2435                         op->reg = rd + 32;
2436                         op->type = MKOP(LOAD_VSX, 0, 4);
2437                         op->element_size = 8;
2438                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2439                         break;
2440                 }
2441                 break;
2442 #endif /* CONFIG_VSX */
2443
2444 #ifdef __powerpc64__
2445         case 58:        /* ld[u], lwa */
2446                 op->ea = dsform_ea(instr, regs);
2447                 switch (instr & 3) {
2448                 case 0:         /* ld */
2449                         op->type = MKOP(LOAD, 0, 8);
2450                         break;
2451                 case 1:         /* ldu */
2452                         op->type = MKOP(LOAD, UPDATE, 8);
2453                         break;
2454                 case 2:         /* lwa */
2455                         op->type = MKOP(LOAD, SIGNEXT, 4);
2456                         break;
2457                 }
2458                 break;
2459 #endif
2460
2461 #ifdef CONFIG_VSX
2462         case 61:        /* stfdp, lxv, stxsd, stxssp, stxv */
2463                 switch (instr & 7) {
2464                 case 0:         /* stfdp with LSB of DS field = 0 */
2465                 case 4:         /* stfdp with LSB of DS field = 1 */
2466                         op->ea = dsform_ea(instr, regs);
2467                         op->type = MKOP(STORE_FP, 0, 16);
2468                         break;
2469
2470                 case 1:         /* lxv */
2471                         op->ea = dqform_ea(instr, regs);
2472                         if (instr & 8)
2473                                 op->reg = rd + 32;
2474                         op->type = MKOP(LOAD_VSX, 0, 16);
2475                         op->element_size = 16;
2476                         op->vsx_flags = VSX_CHECK_VEC;
2477                         break;
2478
2479                 case 2:         /* stxsd with LSB of DS field = 0 */
2480                 case 6:         /* stxsd with LSB of DS field = 1 */
2481                         op->ea = dsform_ea(instr, regs);
2482                         op->reg = rd + 32;
2483                         op->type = MKOP(STORE_VSX, 0, 8);
2484                         op->element_size = 8;
2485                         op->vsx_flags = VSX_CHECK_VEC;
2486                         break;
2487
2488                 case 3:         /* stxssp with LSB of DS field = 0 */
2489                 case 7:         /* stxssp with LSB of DS field = 1 */
2490                         op->ea = dsform_ea(instr, regs);
2491                         op->reg = rd + 32;
2492                         op->type = MKOP(STORE_VSX, 0, 4);
2493                         op->element_size = 8;
2494                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2495                         break;
2496
2497                 case 5:         /* stxv */
2498                         op->ea = dqform_ea(instr, regs);
2499                         if (instr & 8)
2500                                 op->reg = rd + 32;
2501                         op->type = MKOP(STORE_VSX, 0, 16);
2502                         op->element_size = 16;
2503                         op->vsx_flags = VSX_CHECK_VEC;
2504                         break;
2505                 }
2506                 break;
2507 #endif /* CONFIG_VSX */
2508
2509 #ifdef __powerpc64__
2510         case 62:        /* std[u] */
2511                 op->ea = dsform_ea(instr, regs);
2512                 switch (instr & 3) {
2513                 case 0:         /* std */
2514                         op->type = MKOP(STORE, 0, 8);
2515                         break;
2516                 case 1:         /* stdu */
2517                         op->type = MKOP(STORE, UPDATE, 8);
2518                         break;
2519                 case 2:         /* stq */
2520                         if (!(rd & 1))
2521                                 op->type = MKOP(STORE, 0, 16);
2522                         break;
2523                 }
2524                 break;
2525 #endif /* __powerpc64__ */
2526
2527         }
2528         return 0;
2529
2530  logical_done:
2531         if (instr & 1)
2532                 set_cr0(regs, op);
2533  logical_done_nocc:
2534         op->reg = ra;
2535         op->type |= SETREG;
2536         return 1;
2537
2538  arith_done:
2539         if (instr & 1)
2540                 set_cr0(regs, op);
2541  compute_done:
2542         op->reg = rd;
2543         op->type |= SETREG;
2544         return 1;
2545
2546  priv:
2547         op->type = INTERRUPT | 0x700;
2548         op->val = SRR1_PROGPRIV;
2549         return 0;
2550
2551  trap:
2552         op->type = INTERRUPT | 0x700;
2553         op->val = SRR1_PROGTRAP;
2554         return 0;
2555 }
2556 EXPORT_SYMBOL_GPL(analyse_instr);
2557 NOKPROBE_SYMBOL(analyse_instr);
2558
2559 /*
2560  * For PPC32 we always use stwu with r1 to change the stack pointer.
2561  * So this emulated store may corrupt the exception frame, now we
2562  * have to provide the exception frame trampoline, which is pushed
2563  * below the kprobed function stack. So we only update gpr[1] but
2564  * don't emulate the real store operation. We will do real store
2565  * operation safely in exception return code by checking this flag.
2566  */
2567 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2568 {
2569 #ifdef CONFIG_PPC32
2570         /*
2571          * Check if we will touch kernel stack overflow
2572          */
2573         if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2574                 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2575                 return -EINVAL;
2576         }
2577 #endif /* CONFIG_PPC32 */
2578         /*
2579          * Check if we already set since that means we'll
2580          * lose the previous value.
2581          */
2582         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2583         set_thread_flag(TIF_EMULATE_STACK_STORE);
2584         return 0;
2585 }
2586
2587 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2588 {
2589         switch (size) {
2590         case 2:
2591                 *valp = (signed short) *valp;
2592                 break;
2593         case 4:
2594                 *valp = (signed int) *valp;
2595                 break;
2596         }
2597 }
2598
2599 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2600 {
2601         switch (size) {
2602         case 2:
2603                 *valp = byterev_2(*valp);
2604                 break;
2605         case 4:
2606                 *valp = byterev_4(*valp);
2607                 break;
2608 #ifdef __powerpc64__
2609         case 8:
2610                 *valp = byterev_8(*valp);
2611                 break;
2612 #endif
2613         }
2614 }
2615
2616 /*
2617  * Emulate an instruction that can be executed just by updating
2618  * fields in *regs.
2619  */
2620 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2621 {
2622         unsigned long next_pc;
2623
2624         next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
2625         switch (op->type & INSTR_TYPE_MASK) {
2626         case COMPUTE:
2627                 if (op->type & SETREG)
2628                         regs->gpr[op->reg] = op->val;
2629                 if (op->type & SETCC)
2630                         regs->ccr = op->ccval;
2631                 if (op->type & SETXER)
2632                         regs->xer = op->xerval;
2633                 break;
2634
2635         case BRANCH:
2636                 if (op->type & SETLK)
2637                         regs->link = next_pc;
2638                 if (op->type & BRTAKEN)
2639                         next_pc = op->val;
2640                 if (op->type & DECCTR)
2641                         --regs->ctr;
2642                 break;
2643
2644         case BARRIER:
2645                 switch (op->type & BARRIER_MASK) {
2646                 case BARRIER_SYNC:
2647                         mb();
2648                         break;
2649                 case BARRIER_ISYNC:
2650                         isync();
2651                         break;
2652                 case BARRIER_EIEIO:
2653                         eieio();
2654                         break;
2655                 case BARRIER_LWSYNC:
2656                         asm volatile("lwsync" : : : "memory");
2657                         break;
2658                 case BARRIER_PTESYNC:
2659                         asm volatile("ptesync" : : : "memory");
2660                         break;
2661                 }
2662                 break;
2663
2664         case MFSPR:
2665                 switch (op->spr) {
2666                 case SPRN_XER:
2667                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2668                         break;
2669                 case SPRN_LR:
2670                         regs->gpr[op->reg] = regs->link;
2671                         break;
2672                 case SPRN_CTR:
2673                         regs->gpr[op->reg] = regs->ctr;
2674                         break;
2675                 default:
2676                         WARN_ON_ONCE(1);
2677                 }
2678                 break;
2679
2680         case MTSPR:
2681                 switch (op->spr) {
2682                 case SPRN_XER:
2683                         regs->xer = op->val & 0xffffffffUL;
2684                         break;
2685                 case SPRN_LR:
2686                         regs->link = op->val;
2687                         break;
2688                 case SPRN_CTR:
2689                         regs->ctr = op->val;
2690                         break;
2691                 default:
2692                         WARN_ON_ONCE(1);
2693                 }
2694                 break;
2695
2696         default:
2697                 WARN_ON_ONCE(1);
2698         }
2699         regs->nip = next_pc;
2700 }
2701
2702 /*
2703  * Emulate a previously-analysed load or store instruction.
2704  * Return values are:
2705  * 0 = instruction emulated successfully
2706  * -EFAULT = address out of range or access faulted (regs->dar
2707  *           contains the faulting address)
2708  * -EACCES = misaligned access, instruction requires alignment
2709  * -EINVAL = unknown operation in *op
2710  */
2711 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
2712 {
2713         int err, size, type;
2714         int i, rd, nb;
2715         unsigned int cr;
2716         unsigned long val;
2717         unsigned long ea;
2718         bool cross_endian;
2719
2720         err = 0;
2721         size = GETSIZE(op->type);
2722         type = op->type & INSTR_TYPE_MASK;
2723         cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
2724         ea = truncate_if_32bit(regs->msr, op->ea);
2725
2726         switch (type) {
2727         case LARX:
2728                 if (ea & (size - 1))
2729                         return -EACCES;         /* can't handle misaligned */
2730                 if (!address_ok(regs, ea, size))
2731                         return -EFAULT;
2732                 err = 0;
2733                 val = 0;
2734                 switch (size) {
2735 #ifdef __powerpc64__
2736                 case 1:
2737                         __get_user_asmx(val, ea, err, "lbarx");
2738                         break;
2739                 case 2:
2740                         __get_user_asmx(val, ea, err, "lharx");
2741                         break;
2742 #endif
2743                 case 4:
2744                         __get_user_asmx(val, ea, err, "lwarx");
2745                         break;
2746 #ifdef __powerpc64__
2747                 case 8:
2748                         __get_user_asmx(val, ea, err, "ldarx");
2749                         break;
2750                 case 16:
2751                         err = do_lqarx(ea, &regs->gpr[op->reg]);
2752                         break;
2753 #endif
2754                 default:
2755                         return -EINVAL;
2756                 }
2757                 if (err) {
2758                         regs->dar = ea;
2759                         break;
2760                 }
2761                 if (size < 16)
2762                         regs->gpr[op->reg] = val;
2763                 break;
2764
2765         case STCX:
2766                 if (ea & (size - 1))
2767                         return -EACCES;         /* can't handle misaligned */
2768                 if (!address_ok(regs, ea, size))
2769                         return -EFAULT;
2770                 err = 0;
2771                 switch (size) {
2772 #ifdef __powerpc64__
2773                 case 1:
2774                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2775                         break;
2776                 case 2:
2777                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2778                         break;
2779 #endif
2780                 case 4:
2781                         __put_user_asmx(op->val, ea, err, "stwcx.", cr);
2782                         break;
2783 #ifdef __powerpc64__
2784                 case 8:
2785                         __put_user_asmx(op->val, ea, err, "stdcx.", cr);
2786                         break;
2787                 case 16:
2788                         err = do_stqcx(ea, regs->gpr[op->reg],
2789                                        regs->gpr[op->reg + 1], &cr);
2790                         break;
2791 #endif
2792                 default:
2793                         return -EINVAL;
2794                 }
2795                 if (!err)
2796                         regs->ccr = (regs->ccr & 0x0fffffff) |
2797                                 (cr & 0xe0000000) |
2798                                 ((regs->xer >> 3) & 0x10000000);
2799                 else
2800                         regs->dar = ea;
2801                 break;
2802
2803         case LOAD:
2804 #ifdef __powerpc64__
2805                 if (size == 16) {
2806                         err = emulate_lq(regs, ea, op->reg, cross_endian);
2807                         break;
2808                 }
2809 #endif
2810                 err = read_mem(&regs->gpr[op->reg], ea, size, regs);
2811                 if (!err) {
2812                         if (op->type & SIGNEXT)
2813                                 do_signext(&regs->gpr[op->reg], size);
2814                         if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
2815                                 do_byterev(&regs->gpr[op->reg], size);
2816                 }
2817                 break;
2818
2819 #ifdef CONFIG_PPC_FPU
2820         case LOAD_FP:
2821                 /*
2822                  * If the instruction is in userspace, we can emulate it even
2823                  * if the VMX state is not live, because we have the state
2824                  * stored in the thread_struct.  If the instruction is in
2825                  * the kernel, we must not touch the state in the thread_struct.
2826                  */
2827                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2828                         return 0;
2829                 err = do_fp_load(op, ea, regs, cross_endian);
2830                 break;
2831 #endif
2832 #ifdef CONFIG_ALTIVEC
2833         case LOAD_VMX:
2834                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2835                         return 0;
2836                 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
2837                 break;
2838 #endif
2839 #ifdef CONFIG_VSX
2840         case LOAD_VSX: {
2841                 unsigned long msrbit = MSR_VSX;
2842
2843                 /*
2844                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2845                  * when the target of the instruction is a vector register.
2846                  */
2847                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2848                         msrbit = MSR_VEC;
2849                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2850                         return 0;
2851                 err = do_vsx_load(op, ea, regs, cross_endian);
2852                 break;
2853         }
2854 #endif
2855         case LOAD_MULTI:
2856                 if (!address_ok(regs, ea, size))
2857                         return -EFAULT;
2858                 rd = op->reg;
2859                 for (i = 0; i < size; i += 4) {
2860                         unsigned int v32 = 0;
2861
2862                         nb = size - i;
2863                         if (nb > 4)
2864                                 nb = 4;
2865                         err = copy_mem_in((u8 *) &v32, ea, nb, regs);
2866                         if (err)
2867                                 break;
2868                         if (unlikely(cross_endian))
2869                                 v32 = byterev_4(v32);
2870                         regs->gpr[rd] = v32;
2871                         ea += 4;
2872                         /* reg number wraps from 31 to 0 for lsw[ix] */
2873                         rd = (rd + 1) & 0x1f;
2874                 }
2875                 break;
2876
2877         case STORE:
2878 #ifdef __powerpc64__
2879                 if (size == 16) {
2880                         err = emulate_stq(regs, ea, op->reg, cross_endian);
2881                         break;
2882                 }
2883 #endif
2884                 if ((op->type & UPDATE) && size == sizeof(long) &&
2885                     op->reg == 1 && op->update_reg == 1 &&
2886                     !(regs->msr & MSR_PR) &&
2887                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
2888                         err = handle_stack_update(ea, regs);
2889                         break;
2890                 }
2891                 if (unlikely(cross_endian))
2892                         do_byterev(&op->val, size);
2893                 err = write_mem(op->val, ea, size, regs);
2894                 break;
2895
2896 #ifdef CONFIG_PPC_FPU
2897         case STORE_FP:
2898                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2899                         return 0;
2900                 err = do_fp_store(op, ea, regs, cross_endian);
2901                 break;
2902 #endif
2903 #ifdef CONFIG_ALTIVEC
2904         case STORE_VMX:
2905                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2906                         return 0;
2907                 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
2908                 break;
2909 #endif
2910 #ifdef CONFIG_VSX
2911         case STORE_VSX: {
2912                 unsigned long msrbit = MSR_VSX;
2913
2914                 /*
2915                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2916                  * when the target of the instruction is a vector register.
2917                  */
2918                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2919                         msrbit = MSR_VEC;
2920                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2921                         return 0;
2922                 err = do_vsx_store(op, ea, regs, cross_endian);
2923                 break;
2924         }
2925 #endif
2926         case STORE_MULTI:
2927                 if (!address_ok(regs, ea, size))
2928                         return -EFAULT;
2929                 rd = op->reg;
2930                 for (i = 0; i < size; i += 4) {
2931                         unsigned int v32 = regs->gpr[rd];
2932
2933                         nb = size - i;
2934                         if (nb > 4)
2935                                 nb = 4;
2936                         if (unlikely(cross_endian))
2937                                 v32 = byterev_4(v32);
2938                         err = copy_mem_out((u8 *) &v32, ea, nb, regs);
2939                         if (err)
2940                                 break;
2941                         ea += 4;
2942                         /* reg number wraps from 31 to 0 for stsw[ix] */
2943                         rd = (rd + 1) & 0x1f;
2944                 }
2945                 break;
2946
2947         default:
2948                 return -EINVAL;
2949         }
2950
2951         if (err)
2952                 return err;
2953
2954         if (op->type & UPDATE)
2955                 regs->gpr[op->update_reg] = op->ea;
2956
2957         return 0;
2958 }
2959 NOKPROBE_SYMBOL(emulate_loadstore);
2960
2961 /*
2962  * Emulate instructions that cause a transfer of control,
2963  * loads and stores, and a few other instructions.
2964  * Returns 1 if the step was emulated, 0 if not,
2965  * or -1 if the instruction is one that should not be stepped,
2966  * such as an rfid, or a mtmsrd that would clear MSR_RI.
2967  */
2968 int emulate_step(struct pt_regs *regs, unsigned int instr)
2969 {
2970         struct instruction_op op;
2971         int r, err, type;
2972         unsigned long val;
2973         unsigned long ea;
2974
2975         r = analyse_instr(&op, regs, instr);
2976         if (r < 0)
2977                 return r;
2978         if (r > 0) {
2979                 emulate_update_regs(regs, &op);
2980                 return 1;
2981         }
2982
2983         err = 0;
2984         type = op.type & INSTR_TYPE_MASK;
2985
2986         if (OP_IS_LOAD_STORE(type)) {
2987                 err = emulate_loadstore(regs, &op);
2988                 if (err)
2989                         return 0;
2990                 goto instr_done;
2991         }
2992
2993         switch (type) {
2994         case CACHEOP:
2995                 ea = truncate_if_32bit(regs->msr, op.ea);
2996                 if (!address_ok(regs, ea, 8))
2997                         return 0;
2998                 switch (op.type & CACHEOP_MASK) {
2999                 case DCBST:
3000                         __cacheop_user_asmx(ea, err, "dcbst");
3001                         break;
3002                 case DCBF:
3003                         __cacheop_user_asmx(ea, err, "dcbf");
3004                         break;
3005                 case DCBTST:
3006                         if (op.reg == 0)
3007                                 prefetchw((void *) ea);
3008                         break;
3009                 case DCBT:
3010                         if (op.reg == 0)
3011                                 prefetch((void *) ea);
3012                         break;
3013                 case ICBI:
3014                         __cacheop_user_asmx(ea, err, "icbi");
3015                         break;
3016                 case DCBZ:
3017                         err = emulate_dcbz(ea, regs);
3018                         break;
3019                 }
3020                 if (err) {
3021                         regs->dar = ea;
3022                         return 0;
3023                 }
3024                 goto instr_done;
3025
3026         case MFMSR:
3027                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3028                 goto instr_done;
3029
3030         case MTMSR:
3031                 val = regs->gpr[op.reg];
3032                 if ((val & MSR_RI) == 0)
3033                         /* can't step mtmsr[d] that would clear MSR_RI */
3034                         return -1;
3035                 /* here op.val is the mask of bits to change */
3036                 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3037                 goto instr_done;
3038
3039 #ifdef CONFIG_PPC64
3040         case SYSCALL:   /* sc */
3041                 /*
3042                  * N.B. this uses knowledge about how the syscall
3043                  * entry code works.  If that is changed, this will
3044                  * need to be changed also.
3045                  */
3046                 if (regs->gpr[0] == 0x1ebe &&
3047                     cpu_has_feature(CPU_FTR_REAL_LE)) {
3048                         regs->msr ^= MSR_LE;
3049                         goto instr_done;
3050                 }
3051                 regs->gpr[9] = regs->gpr[13];
3052                 regs->gpr[10] = MSR_KERNEL;
3053                 regs->gpr[11] = regs->nip + 4;
3054                 regs->gpr[12] = regs->msr & MSR_MASK;
3055                 regs->gpr[13] = (unsigned long) get_paca();
3056                 regs->nip = (unsigned long) &system_call_common;
3057                 regs->msr = MSR_KERNEL;
3058                 return 1;
3059
3060         case RFI:
3061                 return -1;
3062 #endif
3063         }
3064         return 0;
3065
3066  instr_done:
3067         regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
3068         return 1;
3069 }
3070 NOKPROBE_SYMBOL(emulate_step);