2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
33 #include <asm/xive-regs.h>
34 #include <asm/thread_info.h>
36 /* Sign-extend HDEC if not on POWER9 */
37 #define EXTEND_HDEC(reg) \
40 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
42 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
44 /* Values in HSTATE_NAPPING(r13) */
45 #define NAPPING_CEDE 1
46 #define NAPPING_NOVCPU 2
48 /* Stack frame offsets for kvmppc_hv_entry */
50 #define STACK_SLOT_TRAP (SFS-4)
51 #define STACK_SLOT_TID (SFS-16)
52 #define STACK_SLOT_PSSCR (SFS-24)
53 #define STACK_SLOT_PID (SFS-32)
54 #define STACK_SLOT_IAMR (SFS-40)
55 #define STACK_SLOT_CIABR (SFS-48)
56 #define STACK_SLOT_DAWR (SFS-56)
57 #define STACK_SLOT_DAWRX (SFS-64)
58 #define STACK_SLOT_HFSCR (SFS-72)
61 * Call kvmppc_hv_entry in real mode.
62 * Must be called with interrupts hard-disabled.
66 * LR = return address to continue at after eventually re-enabling MMU
68 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
70 std r0, PPC_LR_STKOFF(r1)
73 std r10, HSTATE_HOST_MSR(r13)
74 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
79 mtmsrd r0,1 /* clear RI in MSR */
86 /* On P9, do LPCR setting, if necessary */
87 ld r3, HSTATE_SPLIT_MODE(r13)
90 lwz r4, KVM_SPLIT_DO_SET(r3)
96 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
98 ld r4, HSTATE_KVM_VCPU(r13)
101 /* Back from guest - restore host state and return to caller */
104 /* Restore host DABR and DABRX */
105 ld r5,HSTATE_DABR(r13)
109 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
112 ld r3,PACA_SPRG_VDSO(r13)
113 mtspr SPRN_SPRG_VDSO_WRITE,r3
115 /* Reload the host's PMU registers */
116 lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
118 beq 23f /* skip if not */
120 ld r3, HSTATE_MMCR0(r13)
121 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
124 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
125 lwz r3, HSTATE_PMC1(r13)
126 lwz r4, HSTATE_PMC2(r13)
127 lwz r5, HSTATE_PMC3(r13)
128 lwz r6, HSTATE_PMC4(r13)
129 lwz r8, HSTATE_PMC5(r13)
130 lwz r9, HSTATE_PMC6(r13)
137 ld r3, HSTATE_MMCR0(r13)
138 ld r4, HSTATE_MMCR1(r13)
139 ld r5, HSTATE_MMCRA(r13)
140 ld r6, HSTATE_SIAR(r13)
141 ld r7, HSTATE_SDAR(r13)
147 ld r8, HSTATE_MMCR2(r13)
148 ld r9, HSTATE_SIER(r13)
151 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
157 * Reload DEC. HDEC interrupts were disabled when
158 * we reloaded the host's LPCR value.
160 ld r3, HSTATE_DECEXP(r13)
165 /* hwthread_req may have got set by cede or no vcpu, so clear it */
167 stb r0, HSTATE_HWTHREAD_REQ(r13)
170 * For external interrupts we need to call the Linux
171 * handler to process the interrupt. We do that by jumping
172 * to absolute address 0x500 for external interrupts.
173 * The [h]rfid at the end of the handler will return to
174 * the book3s_hv_interrupts.S code. For other interrupts
175 * we do the rfid to get back to the book3s_hv_interrupts.S
178 ld r8, 112+PPC_LR_STKOFF(r1)
180 ld r7, HSTATE_HOST_MSR(r13)
182 /* Return the trap number on this thread as the return value */
186 * If we came back from the guest via a relocation-on interrupt,
187 * we will be in virtual mode at this point, which makes it a
188 * little easier to get back to the caller.
191 andi. r0, r0, MSR_IR /* in real mode? */
194 /* RFI into the highmem handler */
198 mtmsrd r6, 1 /* Clear RI in MSR */
203 /* Virtual-mode return */
208 kvmppc_primary_no_guest:
209 /* We handle this much like a ceded vcpu */
210 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
211 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
212 /* HDEC value came from DEC in the first place, it will fit */
216 * Make sure the primary has finished the MMU switch.
217 * We should never get here on a secondary thread, but
218 * check it for robustness' sake.
220 ld r5, HSTATE_KVM_VCORE(r13)
221 65: lbz r0, VCORE_IN_GUEST(r5)
228 /* set our bit in napping_threads */
229 ld r5, HSTATE_KVM_VCORE(r13)
230 lbz r7, HSTATE_PTID(r13)
233 addi r6, r5, VCORE_NAPPING_THREADS
238 /* order napping_threads update vs testing entry_exit_map */
241 lwz r7, VCORE_ENTRY_EXIT(r5)
243 bge kvm_novcpu_exit /* another thread already exiting */
244 li r3, NAPPING_NOVCPU
245 stb r3, HSTATE_NAPPING(r13)
247 li r3, 0 /* Don't wake on privileged (OS) doorbell */
252 * Entered from kvm_start_guest if kvm_hstate.napping is set
258 ld r1, HSTATE_HOST_R1(r13)
259 ld r5, HSTATE_KVM_VCORE(r13)
261 stb r0, HSTATE_NAPPING(r13)
263 /* check the wake reason */
264 bl kvmppc_check_wake_reason
267 * Restore volatile registers since we could have called
268 * a C routine in kvmppc_check_wake_reason.
271 ld r5, HSTATE_KVM_VCORE(r13)
273 /* see if any other thread is already exiting */
274 lwz r0, VCORE_ENTRY_EXIT(r5)
278 /* clear our bit in napping_threads */
279 lbz r7, HSTATE_PTID(r13)
282 addi r6, r5, VCORE_NAPPING_THREADS
288 /* See if the wake reason means we need to exit */
292 /* See if our timeslice has expired (HDEC is negative) */
295 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
299 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
300 ld r4, HSTATE_KVM_VCPU(r13)
302 beq kvmppc_primary_no_guest
304 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
305 addi r3, r4, VCPU_TB_RMENTRY
306 bl kvmhv_start_timing
311 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
312 ld r4, HSTATE_KVM_VCPU(r13)
315 addi r3, r4, VCPU_TB_RMEXIT
316 bl kvmhv_accumulate_time
319 stw r12, STACK_SLOT_TRAP(r1)
320 bl kvmhv_commence_exit
322 b kvmhv_switch_to_host
325 * We come in here when wakened from nap mode.
326 * Relocation is off and most register values are lost.
327 * r13 points to the PACA.
328 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
330 .globl kvm_start_guest
332 /* Set runlatch bit the minute you wake up from nap */
338 * Could avoid this and pass it through in r3. For now,
339 * code expects it to be in SRR1.
346 stb r0,PACA_FTRACE_ENABLED(r13)
348 li r0,KVM_HWTHREAD_IN_KVM
349 stb r0,HSTATE_HWTHREAD_STATE(r13)
351 /* NV GPR values from power7_idle() will no longer be valid */
353 stb r0,PACA_NAPSTATELOST(r13)
355 /* were we napping due to cede? */
356 lbz r0,HSTATE_NAPPING(r13)
357 cmpwi r0,NAPPING_CEDE
359 cmpwi r0,NAPPING_NOVCPU
360 beq kvm_novcpu_wakeup
362 ld r1,PACAEMERGSP(r13)
363 subi r1,r1,STACK_FRAME_OVERHEAD
366 * We weren't napping due to cede, so this must be a secondary
367 * thread being woken up to run a guest, or being woken up due
368 * to a stray IPI. (Or due to some machine check or hypervisor
369 * maintenance interrupt while the core is in KVM.)
372 /* Check the wake reason in SRR1 to see why we got here */
373 bl kvmppc_check_wake_reason
375 * kvmppc_check_wake_reason could invoke a C routine, but we
376 * have no volatile registers to restore when we return.
382 /* get vcore pointer, NULL if we have nothing to run */
383 ld r5,HSTATE_KVM_VCORE(r13)
385 /* if we have no vcore to run, go back to sleep */
388 kvm_secondary_got_guest:
390 /* Set HSTATE_DSCR(r13) to something sensible */
391 ld r6, PACA_DSCR_DEFAULT(r13)
392 std r6, HSTATE_DSCR(r13)
394 /* On thread 0 of a subcore, set HDEC to max */
395 lbz r4, HSTATE_PTID(r13)
398 LOAD_REG_ADDR(r6, decrementer_max)
401 /* and set per-LPAR registers, if doing dynamic micro-threading */
402 ld r6, HSTATE_SPLIT_MODE(r13)
406 ld r0, KVM_SPLIT_RPR(r6)
408 ld r0, KVM_SPLIT_PMMAR(r6)
410 ld r0, KVM_SPLIT_LDBAR(r6)
414 /* On P9 we use the split_info for coordinating LPCR changes */
415 lwz r4, KVM_SPLIT_DO_SET(r6)
422 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
424 /* Order load of vcpu after load of vcore */
426 ld r4, HSTATE_KVM_VCPU(r13)
429 /* Back from the guest, go back to nap */
430 /* Clear our vcpu and vcore pointers so we don't come back in early */
432 std r0, HSTATE_KVM_VCPU(r13)
434 * Once we clear HSTATE_KVM_VCORE(r13), the code in
435 * kvmppc_run_core() is going to assume that all our vcpu
436 * state is visible in memory. This lwsync makes sure
440 std r0, HSTATE_KVM_VCORE(r13)
443 * All secondaries exiting guest will fall through this path.
444 * Before proceeding, just check for HMI interrupt and
445 * invoke opal hmi handler. By now we are sure that the
446 * primary thread on this core/subcore has already made partition
447 * switch/TB resync and we are good to call opal hmi handler.
449 cmpwi r12, BOOK3S_INTERRUPT_HMI
452 li r3,0 /* NULL argument */
453 bl hmi_exception_realmode
455 * At this point we have finished executing in the guest.
456 * We need to wait for hwthread_req to become zero, since
457 * we may not turn on the MMU while hwthread_req is non-zero.
458 * While waiting we also need to check if we get given a vcpu to run.
461 lbz r3, HSTATE_HWTHREAD_REQ(r13)
465 li r0, KVM_HWTHREAD_IN_KERNEL
466 stb r0, HSTATE_HWTHREAD_STATE(r13)
467 /* need to recheck hwthread_req after a barrier, to avoid race */
469 lbz r3, HSTATE_HWTHREAD_REQ(r13)
473 * We jump to pnv_wakeup_loss, which will return to the caller
474 * of power7_nap in the powernv cpu offline loop. The value we
475 * put in r3 becomes the return value for power7_nap. pnv_wakeup_loss
476 * requires SRR1 in r12.
480 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
487 ld r5, HSTATE_KVM_VCORE(r13)
490 ld r3, HSTATE_SPLIT_MODE(r13)
493 lwz r0, KVM_SPLIT_DO_SET(r3)
496 lwz r0, KVM_SPLIT_DO_RESTORE(r3)
499 lbz r0, KVM_SPLIT_DO_NAP(r3)
505 b kvm_secondary_got_guest
507 54: li r0, KVM_HWTHREAD_IN_KVM
508 stb r0, HSTATE_HWTHREAD_STATE(r13)
512 /* Set LPCR, LPIDR etc. on P9 */
520 bl kvmhv_p9_restore_lpcr
525 * Here the primary thread is trying to return the core to
526 * whole-core mode, so we need to nap.
530 * When secondaries are napping in kvm_unsplit_nap() with
531 * hwthread_req = 1, HMI goes ignored even though subcores are
532 * already exited the guest. Hence HMI keeps waking up secondaries
533 * from nap in a loop and secondaries always go back to nap since
534 * no vcore is assigned to them. This makes impossible for primary
535 * thread to get hold of secondary threads resulting into a soft
536 * lockup in KVM path.
538 * Let us check if HMI is pending and handle it before we go to nap.
540 cmpwi r12, BOOK3S_INTERRUPT_HMI
542 li r3, 0 /* NULL argument */
543 bl hmi_exception_realmode
546 * Ensure that secondary doesn't nap when it has
547 * its vcore pointer set.
549 sync /* matches smp_mb() before setting split_info.do_nap */
550 ld r0, HSTATE_KVM_VCORE(r13)
553 /* clear any pending message */
555 lis r6, (PPC_DBELL_SERVER << (63-36))@h
557 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
558 /* Set kvm_split_mode.napped[tid] = 1 */
559 ld r3, HSTATE_SPLIT_MODE(r13)
561 lbz r4, HSTATE_TID(r13)
562 addi r4, r4, KVM_SPLIT_NAPPED
564 /* Check the do_nap flag again after setting napped[] */
566 lbz r0, KVM_SPLIT_DO_NAP(r3)
569 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
571 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
578 /******************************************************************************
582 *****************************************************************************/
584 .global kvmppc_hv_entry
589 * R4 = vcpu pointer (or NULL)
594 * all other volatile GPRS = free
595 * Does not preserve non-volatile GPRs or CR fields
598 std r0, PPC_LR_STKOFF(r1)
601 /* Save R1 in the PACA */
602 std r1, HSTATE_HOST_R1(r13)
604 li r6, KVM_GUEST_MODE_HOST_HV
605 stb r6, HSTATE_IN_GUEST(r13)
607 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
608 /* Store initial timestamp */
611 addi r3, r4, VCPU_TB_RMENTRY
612 bl kvmhv_start_timing
616 /* Use cr7 as an indication of radix mode */
617 ld r5, HSTATE_KVM_VCORE(r13)
618 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
619 lbz r0, KVM_RADIX(r9)
623 * POWER7/POWER8 host -> guest partition switch code.
624 * We don't have to lock against concurrent tlbies,
625 * but we do have to coordinate across hardware threads.
627 /* Set bit in entry map iff exit map is zero. */
629 lbz r6, HSTATE_PTID(r13)
631 addi r8, r5, VCORE_ENTRY_EXIT
633 cmpwi r3, 0x100 /* any threads starting to exit? */
634 bge secondary_too_late /* if so we're too late to the party */
639 /* Primary thread switches to guest partition. */
645 li r0,LPID_RSVD /* switch to reserved LPID */
648 mtspr SPRN_SDR1,r6 /* switch to partition page table */
649 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
653 /* See if we need to flush the TLB */
654 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
657 * On POWER9, individual threads can come in here, but the
658 * TLB is shared between the 4 threads in a core, hence
659 * invalidating on one thread invalidates for all.
660 * Thus we make all 4 threads use the same bit here.
663 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
664 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
665 srdi r6,r6,6 /* doubleword number */
666 sldi r6,r6,3 /* address offset */
668 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
674 /* Flush the TLB of any entries for this LPID */
675 lwz r0,KVM_TLB_SETS(r9)
677 li r7,0x800 /* IS field = 0b10 */
679 li r0,0 /* RS for P9 version of tlbiel */
681 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
685 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */
689 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
694 /* Add timebase offset onto timebase */
695 22: ld r8,VCORE_TB_OFFSET(r5)
698 std r8, VCORE_TB_OFFSET_APPL(r5)
699 mftb r6 /* current host timebase */
701 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
702 mftb r7 /* check if lower 24 bits overflowed */
707 addis r8,r8,0x100 /* if so, increment upper 40 bits */
710 /* Load guest PCR value to select appropriate compat mode */
711 37: ld r7, VCORE_PCR(r5)
718 /* DPDES and VTB are shared between threads */
719 ld r8, VCORE_DPDES(r5)
723 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
725 /* Mark the subcore state as inside guest */
726 bl kvmppc_subcore_enter_guest
728 ld r5, HSTATE_KVM_VCORE(r13)
729 ld r4, HSTATE_KVM_VCPU(r13)
731 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
733 /* Do we have a guest vcpu to run? */
735 beq kvmppc_primary_no_guest
737 /* Increment yield count if they have a VPA */
741 li r6, LPPACA_YIELDCOUNT
746 stb r6, VCPU_VPA_DIRTY(r4)
749 /* Save purr/spurr */
752 std r5,HSTATE_PURR(r13)
753 std r6,HSTATE_SPURR(r13)
759 /* Save host values of some registers */
765 std r5, STACK_SLOT_TID(r1)
766 std r6, STACK_SLOT_PSSCR(r1)
767 std r7, STACK_SLOT_PID(r1)
768 std r8, STACK_SLOT_IAMR(r1)
770 std r5, STACK_SLOT_HFSCR(r1)
771 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
776 std r5, STACK_SLOT_CIABR(r1)
777 std r6, STACK_SLOT_DAWR(r1)
778 std r7, STACK_SLOT_DAWRX(r1)
779 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
782 /* Set partition DABR */
783 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
784 lwz r5,VCPU_DABRX(r4)
789 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
791 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
793 * Branch around the call if both CPU_FTR_TM and
794 * CPU_FTR_P9_TM_HV_ASSIST are off.
798 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
800 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
806 /* Load guest PMU registers */
807 /* R4 is live here (vcpu pointer) */
809 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
810 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
814 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
817 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
818 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
819 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
820 lwz r6, VCPU_PMC + 8(r4)
821 lwz r7, VCPU_PMC + 12(r4)
822 lwz r8, VCPU_PMC + 16(r4)
823 lwz r9, VCPU_PMC + 20(r4)
831 ld r5, VCPU_MMCR + 8(r4)
832 ld r6, VCPU_MMCR + 16(r4)
840 ld r5, VCPU_MMCR + 24(r4)
844 BEGIN_FTR_SECTION_NESTED(96)
845 lwz r7, VCPU_PMC + 24(r4)
846 lwz r8, VCPU_PMC + 28(r4)
847 ld r9, VCPU_MMCR + 32(r4)
851 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
852 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
856 /* Load up FP, VMX and VSX registers */
859 ld r14, VCPU_GPR(R14)(r4)
860 ld r15, VCPU_GPR(R15)(r4)
861 ld r16, VCPU_GPR(R16)(r4)
862 ld r17, VCPU_GPR(R17)(r4)
863 ld r18, VCPU_GPR(R18)(r4)
864 ld r19, VCPU_GPR(R19)(r4)
865 ld r20, VCPU_GPR(R20)(r4)
866 ld r21, VCPU_GPR(R21)(r4)
867 ld r22, VCPU_GPR(R22)(r4)
868 ld r23, VCPU_GPR(R23)(r4)
869 ld r24, VCPU_GPR(R24)(r4)
870 ld r25, VCPU_GPR(R25)(r4)
871 ld r26, VCPU_GPR(R26)(r4)
872 ld r27, VCPU_GPR(R27)(r4)
873 ld r28, VCPU_GPR(R28)(r4)
874 ld r29, VCPU_GPR(R29)(r4)
875 ld r30, VCPU_GPR(R30)(r4)
876 ld r31, VCPU_GPR(R31)(r4)
878 /* Switch DSCR to guest value */
883 /* Skip next section on POWER7 */
885 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
886 /* Load up POWER8-specific registers */
888 lwz r6, VCPU_PSPB(r4)
894 ld r6, VCPU_DAWRX(r4)
895 ld r7, VCPU_CIABR(r4)
898 * Handle broken DAWR case by not writing it. This means we
899 * can still store the DAWR register for migration.
904 END_FTR_SECTION_IFSET(CPU_FTR_DAWR)
908 ld r8, VCPU_EBBHR(r4)
911 ld r5, VCPU_EBBRR(r4)
912 ld r6, VCPU_BESCR(r4)
913 lwz r7, VCPU_GUEST_PID(r4)
921 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
923 /* POWER8-only registers */
924 ld r5, VCPU_TCSCR(r4)
926 ld r7, VCPU_CSIGR(r4)
934 /* POWER9-only registers */
936 ld r6, VCPU_PSSCR(r4)
937 lbz r8, HSTATE_FAKE_SUSPEND(r13)
938 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
939 rldimi r6, r8, PSSCR_FAKE_SUSPEND_LG, 63 - PSSCR_FAKE_SUSPEND_LG
940 ld r7, VCPU_HFSCR(r4)
944 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
947 ld r5, VCPU_SPRG0(r4)
948 ld r6, VCPU_SPRG1(r4)
949 ld r7, VCPU_SPRG2(r4)
950 ld r8, VCPU_SPRG3(r4)
956 /* Load up DAR and DSISR */
958 lwz r6, VCPU_DSISR(r4)
962 /* Restore AMR and UAMOR, set AMOR to all 1s */
970 /* Restore state of CTRL run bit; assume 1 on entry */
978 /* Secondary threads wait for primary to have done partition switch */
979 ld r5, HSTATE_KVM_VCORE(r13)
980 lbz r6, HSTATE_PTID(r13)
983 lbz r0, VCORE_IN_GUEST(r5)
987 20: lwz r3, VCORE_ENTRY_EXIT(r5)
990 lbz r0, VCORE_IN_GUEST(r5)
1001 * Set the decrementer to the guest decrementer.
1003 ld r8,VCPU_DEC_EXPIRES(r4)
1004 /* r8 is a host timebase value here, convert to guest TB */
1005 ld r5,HSTATE_KVM_VCORE(r13)
1006 ld r6,VCORE_TB_OFFSET_APPL(r5)
1012 /* Check if HDEC expires soon */
1015 cmpdi r3, 512 /* 1 microsecond */
1018 /* For hash guest, clear out and reload the SLB */
1020 lbz r0, KVM_RADIX(r6)
1028 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
1029 lwz r5,VCPU_SLB_MAX(r4)
1034 1: ld r8,VCPU_SLB_E(r6)
1035 ld r9,VCPU_SLB_V(r6)
1037 addi r6,r6,VCPU_SLB_SIZE
1041 #ifdef CONFIG_KVM_XICS
1042 /* We are entering the guest on that thread, push VCPU to XIVE */
1043 ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1046 ld r11, VCPU_XIVE_SAVED_STATE(r4)
1050 lwz r11, VCPU_XIVE_CAM_WORD(r4)
1051 li r9, TM_QW1_OS + TM_WORD2
1054 stb r9, VCPU_XIVE_PUSHED(r4)
1058 * We clear the irq_pending flag. There is a small chance of a
1059 * race vs. the escalation interrupt happening on another
1060 * processor setting it again, but the only consequence is to
1061 * cause a spurrious wakeup on the next H_CEDE which is not an
1065 stb r0, VCPU_IRQ_PENDING(r4)
1068 * In single escalation mode, if the escalation interrupt is
1071 lbz r0, VCPU_XIVE_ESC_ON(r4)
1074 ld r10, VCPU_XIVE_ESC_RADDR(r4)
1075 li r9, XIVE_ESB_SET_PQ_01
1079 /* We have a possible subtle race here: The escalation interrupt might
1080 * have fired and be on its way to the host queue while we mask it,
1081 * and if we unmask it early enough (re-cede right away), there is
1082 * a theorical possibility that it fires again, thus landing in the
1083 * target queue more than once which is a big no-no.
1085 * Fortunately, solving this is rather easy. If the above load setting
1086 * PQ to 01 returns a previous value where P is set, then we know the
1087 * escalation interrupt is somewhere on its way to the host. In that
1088 * case we simply don't clear the xive_esc_on flag below. It will be
1089 * eventually cleared by the handler for the escalation interrupt.
1091 * Then, when doing a cede, we check that flag again before re-enabling
1092 * the escalation interrupt, and if set, we abort the cede.
1094 andi. r0, r0, XIVE_ESB_VAL_P
1097 /* Now P is 0, we can clear the flag */
1099 stb r0, VCPU_XIVE_ESC_ON(r4)
1102 #endif /* CONFIG_KVM_XICS */
1104 deliver_guest_interrupt:
1111 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
1113 ld r11, VCPU_MSR(r4)
1114 ld r6, VCPU_SRR0(r4)
1115 ld r7, VCPU_SRR1(r4)
1119 /* r11 = vcpu->arch.msr & ~MSR_HV */
1120 rldicl r11, r11, 63 - MSR_HV_LG, 1
1121 rotldi r11, r11, 1 + MSR_HV_LG
1122 ori r11, r11, MSR_ME
1124 /* Check if we can deliver an external or decrementer interrupt now */
1125 ld r0, VCPU_PENDING_EXC(r4)
1126 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1128 andi. r8, r11, MSR_EE
1130 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1131 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1135 li r0, BOOK3S_INTERRUPT_EXTERNAL
1139 /* On POWER9 check whether the guest has large decrementer enabled */
1140 andis. r8, r8, LPCR_LD@h
1142 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1145 li r0, BOOK3S_INTERRUPT_DECREMENTER
1148 12: mtspr SPRN_SRR0, r10
1150 mtspr SPRN_SRR1, r11
1152 bl kvmppc_msr_interrupt
1156 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1157 /* On POWER9, check for pending doorbell requests */
1158 lbz r0, VCPU_DBELL_REQ(r4)
1160 beq fast_guest_return
1161 ld r5, HSTATE_KVM_VCORE(r13)
1162 /* Set DPDES register so the CPU will take a doorbell interrupt */
1164 mtspr SPRN_DPDES, r0
1165 std r0, VCORE_DPDES(r5)
1166 /* Make sure other cpus see vcore->dpdes set before dbell req clear */
1168 /* Clear the pending doorbell request */
1170 stb r0, VCPU_DBELL_REQ(r4)
1175 * R10: value for HSRR0
1176 * R11: value for HSRR1
1181 stb r0,VCPU_CEDED(r4) /* cancel cede */
1182 mtspr SPRN_HSRR0,r10
1183 mtspr SPRN_HSRR1,r11
1185 /* Activate guest mode, so faults get handled by KVM */
1186 li r9, KVM_GUEST_MODE_GUEST_HV
1187 stb r9, HSTATE_IN_GUEST(r13)
1189 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1190 /* Accumulate timing */
1191 addi r3, r4, VCPU_TB_GUEST
1192 bl kvmhv_accumulate_time
1198 ld r5, VCPU_CFAR(r4)
1200 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1203 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1210 ld r1, VCPU_GPR(R1)(r4)
1211 ld r2, VCPU_GPR(R2)(r4)
1212 ld r3, VCPU_GPR(R3)(r4)
1213 ld r5, VCPU_GPR(R5)(r4)
1214 ld r6, VCPU_GPR(R6)(r4)
1215 ld r7, VCPU_GPR(R7)(r4)
1216 ld r8, VCPU_GPR(R8)(r4)
1217 ld r9, VCPU_GPR(R9)(r4)
1218 ld r10, VCPU_GPR(R10)(r4)
1219 ld r11, VCPU_GPR(R11)(r4)
1220 ld r12, VCPU_GPR(R12)(r4)
1221 ld r13, VCPU_GPR(R13)(r4)
1225 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1227 /* Move canary into DSISR to check for later */
1230 mtspr SPRN_HDSISR, r0
1231 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1233 ld r0, VCPU_GPR(R0)(r4)
1234 ld r4, VCPU_GPR(R4)(r4)
1240 stw r12, STACK_SLOT_TRAP(r1)
1243 stw r12, VCPU_TRAP(r4)
1244 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1245 addi r3, r4, VCPU_TB_RMEXIT
1246 bl kvmhv_accumulate_time
1248 11: b kvmhv_switch_to_host
1255 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1256 12: stw r12, VCPU_TRAP(r4)
1258 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1259 addi r3, r4, VCPU_TB_RMEXIT
1260 bl kvmhv_accumulate_time
1264 /******************************************************************************
1268 *****************************************************************************/
1271 * We come here from the first-level interrupt handlers.
1273 .globl kvmppc_interrupt_hv
1274 kvmppc_interrupt_hv:
1276 * Register contents:
1277 * R12 = (guest CR << 32) | interrupt vector
1279 * guest R12 saved in shadow VCPU SCRATCH0
1280 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1281 * guest R13 saved in SPRN_SCRATCH0
1283 std r9, HSTATE_SCRATCH2(r13)
1284 lbz r9, HSTATE_IN_GUEST(r13)
1285 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1286 beq kvmppc_bad_host_intr
1287 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1288 cmpwi r9, KVM_GUEST_MODE_GUEST
1289 ld r9, HSTATE_SCRATCH2(r13)
1290 beq kvmppc_interrupt_pr
1292 /* We're now back in the host but in guest MMU context */
1293 li r9, KVM_GUEST_MODE_HOST_HV
1294 stb r9, HSTATE_IN_GUEST(r13)
1296 ld r9, HSTATE_KVM_VCPU(r13)
1298 /* Save registers */
1300 std r0, VCPU_GPR(R0)(r9)
1301 std r1, VCPU_GPR(R1)(r9)
1302 std r2, VCPU_GPR(R2)(r9)
1303 std r3, VCPU_GPR(R3)(r9)
1304 std r4, VCPU_GPR(R4)(r9)
1305 std r5, VCPU_GPR(R5)(r9)
1306 std r6, VCPU_GPR(R6)(r9)
1307 std r7, VCPU_GPR(R7)(r9)
1308 std r8, VCPU_GPR(R8)(r9)
1309 ld r0, HSTATE_SCRATCH2(r13)
1310 std r0, VCPU_GPR(R9)(r9)
1311 std r10, VCPU_GPR(R10)(r9)
1312 std r11, VCPU_GPR(R11)(r9)
1313 ld r3, HSTATE_SCRATCH0(r13)
1314 std r3, VCPU_GPR(R12)(r9)
1315 /* CR is in the high half of r12 */
1319 ld r3, HSTATE_CFAR(r13)
1320 std r3, VCPU_CFAR(r9)
1321 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1323 ld r4, HSTATE_PPR(r13)
1324 std r4, VCPU_PPR(r9)
1325 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1327 /* Restore R1/R2 so we can handle faults */
1328 ld r1, HSTATE_HOST_R1(r13)
1331 mfspr r10, SPRN_SRR0
1332 mfspr r11, SPRN_SRR1
1333 std r10, VCPU_SRR0(r9)
1334 std r11, VCPU_SRR1(r9)
1335 /* trap is in the low half of r12, clear CR from the high half */
1337 andi. r0, r12, 2 /* need to read HSRR0/1? */
1339 mfspr r10, SPRN_HSRR0
1340 mfspr r11, SPRN_HSRR1
1342 1: std r10, VCPU_PC(r9)
1343 std r11, VCPU_MSR(r9)
1347 std r3, VCPU_GPR(R13)(r9)
1350 stw r12,VCPU_TRAP(r9)
1353 * Now that we have saved away SRR0/1 and HSRR0/1,
1354 * interrupts are recoverable in principle, so set MSR_RI.
1355 * This becomes important for relocation-on interrupts from
1356 * the guest, which we can get in radix mode on POWER9.
1361 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1362 addi r3, r9, VCPU_TB_RMINTR
1364 bl kvmhv_accumulate_time
1365 ld r5, VCPU_GPR(R5)(r9)
1366 ld r6, VCPU_GPR(R6)(r9)
1367 ld r7, VCPU_GPR(R7)(r9)
1368 ld r8, VCPU_GPR(R8)(r9)
1371 /* Save HEIR (HV emulation assist reg) in emul_inst
1372 if this is an HEI (HV emulation interrupt, e40) */
1373 li r3,KVM_INST_FETCH_FAILED
1374 stw r3,VCPU_LAST_INST(r9)
1375 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1378 11: stw r3,VCPU_HEIR(r9)
1380 /* these are volatile across C function calls */
1381 #ifdef CONFIG_RELOCATABLE
1382 ld r3, HSTATE_SCRATCH1(r13)
1388 std r3, VCPU_CTR(r9)
1389 std r4, VCPU_XER(r9)
1391 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1392 /* For softpatch interrupt, go off and do TM instruction emulation */
1393 cmpwi r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
1397 /* If this is a page table miss then see if it's theirs or ours */
1398 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1400 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1403 /* See if this is a leftover HDEC interrupt */
1404 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1410 bge fast_guest_return
1412 /* See if this is an hcall we can handle in real mode */
1413 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1414 beq hcall_try_real_mode
1416 /* Hypervisor doorbell - exit only if host IPI flag set */
1417 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1422 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1423 lbz r0, HSTATE_HOST_IPI(r13)
1428 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1429 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1431 mfspr r3, SPRN_HFSCR
1432 std r3, VCPU_HFSCR(r9)
1435 /* External interrupt ? */
1436 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1437 bne+ guest_exit_cont
1439 /* External interrupt, first check for host_ipi. If this is
1440 * set, we know the host wants us out so let's do it now
1445 * Restore the active volatile registers after returning from
1448 ld r9, HSTATE_KVM_VCPU(r13)
1449 li r12, BOOK3S_INTERRUPT_EXTERNAL
1452 * kvmppc_read_intr return codes:
1454 * Exit to host (r3 > 0)
1455 * 1 An interrupt is pending that needs to be handled by the host
1456 * Exit guest and return to host by branching to guest_exit_cont
1458 * 2 Passthrough that needs completion in the host
1459 * Exit guest and return to host by branching to guest_exit_cont
1460 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1461 * to indicate to the host to complete handling the interrupt
1463 * Before returning to guest, we check if any CPU is heading out
1464 * to the host and if so, we head out also. If no CPUs are heading
1465 * check return values <= 0.
1467 * Return to guest (r3 <= 0)
1468 * 0 No external interrupt is pending
1469 * -1 A guest wakeup IPI (which has now been cleared)
1470 * In either case, we return to guest to deliver any pending
1473 * -2 A PCI passthrough external interrupt was handled
1474 * (interrupt was delivered directly to guest)
1475 * Return to guest to deliver any pending guest interrupts.
1481 /* Return code = 2 */
1482 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1483 stw r12, VCPU_TRAP(r9)
1486 1: /* Return code <= 1 */
1490 /* Return code <= 0 */
1491 4: ld r5, HSTATE_KVM_VCORE(r13)
1492 lwz r0, VCORE_ENTRY_EXIT(r5)
1495 blt deliver_guest_interrupt
1497 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1498 /* Save more register state */
1501 std r6, VCPU_DAR(r9)
1502 stw r7, VCPU_DSISR(r9)
1503 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1504 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1506 std r6, VCPU_FAULT_DAR(r9)
1507 stw r7, VCPU_FAULT_DSISR(r9)
1509 /* See if it is a machine check */
1510 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1511 beq machine_check_realmode
1513 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1514 addi r3, r9, VCPU_TB_RMEXIT
1516 bl kvmhv_accumulate_time
1518 #ifdef CONFIG_KVM_XICS
1519 /* We are exiting, pull the VP from the XIVE */
1520 lbz r0, VCPU_XIVE_PUSHED(r9)
1523 li r7, TM_SPC_PULL_OS_CTX
1526 andi. r0, r0, MSR_DR /* in real mode? */
1528 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1531 /* First load to pull the context, we ignore the value */
1534 /* Second load to recover the context state (Words 0 and 1) */
1537 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1540 /* First load to pull the context, we ignore the value */
1543 /* Second load to recover the context state (Words 0 and 1) */
1545 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1546 /* Fixup some of the state for the next load */
1549 stb r10, VCPU_XIVE_PUSHED(r9)
1550 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1551 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1554 #endif /* CONFIG_KVM_XICS */
1556 /* For hash guest, read the guest SLB and save it away */
1558 lbz r0, KVM_RADIX(r5)
1561 bne 3f /* for radix, save 0 entries */
1562 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1567 andis. r0,r8,SLB_ESID_V@h
1569 add r8,r8,r6 /* put index in */
1571 std r8,VCPU_SLB_E(r7)
1572 std r3,VCPU_SLB_V(r7)
1573 addi r7,r7,VCPU_SLB_SIZE
1577 /* Finally clear out the SLB */
1582 3: stw r5,VCPU_SLB_MAX(r9)
1584 /* load host SLB entries */
1585 BEGIN_MMU_FTR_SECTION
1587 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1588 ld r8,PACA_SLBSHADOWPTR(r13)
1590 .rept SLB_NUM_BOLTED
1591 li r3, SLBSHADOW_SAVEAREA
1595 andis. r7,r5,SLB_ESID_V@h
1603 stw r12, STACK_SLOT_TRAP(r1)
1606 /* Do this before kvmhv_commence_exit so we know TB is guest TB */
1607 ld r3, HSTATE_KVM_VCORE(r13)
1610 /* On P9, if the guest has large decr enabled, don't sign extend */
1612 ld r4, VCORE_LPCR(r3)
1613 andis. r4, r4, LPCR_LD@h
1615 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1618 /* r5 is a guest timebase value here, convert to host TB */
1619 ld r4,VCORE_TB_OFFSET_APPL(r3)
1621 std r5,VCPU_DEC_EXPIRES(r9)
1623 /* Increment exit count, poke other threads to exit */
1625 bl kvmhv_commence_exit
1627 ld r9, HSTATE_KVM_VCPU(r13)
1629 /* Stop others sending VCPU interrupts to this physical CPU */
1631 stw r0, VCPU_CPU(r9)
1632 stw r0, VCPU_THREAD_CPU(r9)
1634 /* Save guest CTRL register, set runlatch to 1 */
1636 stw r6,VCPU_CTRL(r9)
1643 * Save the guest PURR/SPURR
1648 ld r8,VCPU_SPURR(r9)
1649 std r5,VCPU_PURR(r9)
1650 std r6,VCPU_SPURR(r9)
1655 * Restore host PURR/SPURR and add guest times
1656 * so that the time in the guest gets accounted.
1658 ld r3,HSTATE_PURR(r13)
1659 ld r4,HSTATE_SPURR(r13)
1667 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1668 /* Save POWER8-specific registers */
1672 std r5, VCPU_IAMR(r9)
1673 stw r6, VCPU_PSPB(r9)
1674 std r7, VCPU_FSCR(r9)
1678 std r7, VCPU_TAR(r9)
1679 mfspr r8, SPRN_EBBHR
1680 std r8, VCPU_EBBHR(r9)
1681 mfspr r5, SPRN_EBBRR
1682 mfspr r6, SPRN_BESCR
1685 std r5, VCPU_EBBRR(r9)
1686 std r6, VCPU_BESCR(r9)
1687 stw r7, VCPU_GUEST_PID(r9)
1688 std r8, VCPU_WORT(r9)
1690 mfspr r5, SPRN_TCSCR
1692 mfspr r7, SPRN_CSIGR
1694 std r5, VCPU_TCSCR(r9)
1695 std r6, VCPU_ACOP(r9)
1696 std r7, VCPU_CSIGR(r9)
1697 std r8, VCPU_TACR(r9)
1700 mfspr r6, SPRN_PSSCR
1701 std r5, VCPU_TID(r9)
1702 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1704 std r6, VCPU_PSSCR(r9)
1705 /* Restore host HFSCR value */
1706 ld r7, STACK_SLOT_HFSCR(r1)
1707 mtspr SPRN_HFSCR, r7
1708 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1710 * Restore various registers to 0, where non-zero values
1711 * set by the guest could disrupt the host.
1718 mtspr SPRN_TCSCR, r0
1719 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1722 mtspr SPRN_MMCRS, r0
1723 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1726 /* Save and reset AMR and UAMOR before turning on the MMU */
1730 std r6,VCPU_UAMOR(r9)
1733 mtspr SPRN_UAMOR, r6
1735 /* Switch DSCR back to host value */
1737 ld r7, HSTATE_DSCR(r13)
1738 std r8, VCPU_DSCR(r9)
1741 /* Save non-volatile GPRs */
1742 std r14, VCPU_GPR(R14)(r9)
1743 std r15, VCPU_GPR(R15)(r9)
1744 std r16, VCPU_GPR(R16)(r9)
1745 std r17, VCPU_GPR(R17)(r9)
1746 std r18, VCPU_GPR(R18)(r9)
1747 std r19, VCPU_GPR(R19)(r9)
1748 std r20, VCPU_GPR(R20)(r9)
1749 std r21, VCPU_GPR(R21)(r9)
1750 std r22, VCPU_GPR(R22)(r9)
1751 std r23, VCPU_GPR(R23)(r9)
1752 std r24, VCPU_GPR(R24)(r9)
1753 std r25, VCPU_GPR(R25)(r9)
1754 std r26, VCPU_GPR(R26)(r9)
1755 std r27, VCPU_GPR(R27)(r9)
1756 std r28, VCPU_GPR(R28)(r9)
1757 std r29, VCPU_GPR(R29)(r9)
1758 std r30, VCPU_GPR(R30)(r9)
1759 std r31, VCPU_GPR(R31)(r9)
1762 mfspr r3, SPRN_SPRG0
1763 mfspr r4, SPRN_SPRG1
1764 mfspr r5, SPRN_SPRG2
1765 mfspr r6, SPRN_SPRG3
1766 std r3, VCPU_SPRG0(r9)
1767 std r4, VCPU_SPRG1(r9)
1768 std r5, VCPU_SPRG2(r9)
1769 std r6, VCPU_SPRG3(r9)
1775 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1777 * Branch around the call if both CPU_FTR_TM and
1778 * CPU_FTR_P9_TM_HV_ASSIST are off.
1782 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
1784 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
1790 /* Increment yield count if they have a VPA */
1791 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1794 li r4, LPPACA_YIELDCOUNT
1799 stb r3, VCPU_VPA_DIRTY(r9)
1801 /* Save PMU registers if requested */
1802 /* r8 and cr0.eq are live here */
1805 * POWER8 seems to have a hardware bug where setting
1806 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1807 * when some counters are already negative doesn't seem
1808 * to cause a performance monitor alert (and hence interrupt).
1809 * The effect of this is that when saving the PMU state,
1810 * if there is no PMU alert pending when we read MMCR0
1811 * before freezing the counters, but one becomes pending
1812 * before we read the counters, we lose it.
1813 * To work around this, we need a way to freeze the counters
1814 * before reading MMCR0. Normally, freezing the counters
1815 * is done by writing MMCR0 (to set MMCR0[FC]) which
1816 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1817 * we can also freeze the counters using MMCR2, by writing
1818 * 1s to all the counter freeze condition bits (there are
1819 * 9 bits each for 6 counters).
1821 li r3, -1 /* set all freeze bits */
1823 mfspr r10, SPRN_MMCR2
1824 mtspr SPRN_MMCR2, r3
1826 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1828 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1829 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1830 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1831 mfspr r6, SPRN_MMCRA
1832 /* Clear MMCRA in order to disable SDAR updates */
1834 mtspr SPRN_MMCRA, r7
1836 beq 21f /* if no VPA, save PMU stuff anyway */
1837 lbz r7, LPPACA_PMCINUSE(r8)
1838 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1840 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1842 21: mfspr r5, SPRN_MMCR1
1845 std r4, VCPU_MMCR(r9)
1846 std r5, VCPU_MMCR + 8(r9)
1847 std r6, VCPU_MMCR + 16(r9)
1849 std r10, VCPU_MMCR + 24(r9)
1850 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1851 std r7, VCPU_SIAR(r9)
1852 std r8, VCPU_SDAR(r9)
1859 stw r3, VCPU_PMC(r9)
1860 stw r4, VCPU_PMC + 4(r9)
1861 stw r5, VCPU_PMC + 8(r9)
1862 stw r6, VCPU_PMC + 12(r9)
1863 stw r7, VCPU_PMC + 16(r9)
1864 stw r8, VCPU_PMC + 20(r9)
1867 std r5, VCPU_SIER(r9)
1868 BEGIN_FTR_SECTION_NESTED(96)
1869 mfspr r6, SPRN_SPMC1
1870 mfspr r7, SPRN_SPMC2
1871 mfspr r8, SPRN_MMCRS
1872 stw r6, VCPU_PMC + 24(r9)
1873 stw r7, VCPU_PMC + 28(r9)
1874 std r8, VCPU_MMCR + 32(r9)
1876 mtspr SPRN_MMCRS, r4
1877 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1878 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1881 /* Restore host values of some registers */
1883 ld r5, STACK_SLOT_CIABR(r1)
1884 ld r6, STACK_SLOT_DAWR(r1)
1885 ld r7, STACK_SLOT_DAWRX(r1)
1886 mtspr SPRN_CIABR, r5
1888 * If the DAWR doesn't work, it's ok to write these here as
1889 * this value should always be zero
1892 mtspr SPRN_DAWRX, r7
1893 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1895 ld r5, STACK_SLOT_TID(r1)
1896 ld r6, STACK_SLOT_PSSCR(r1)
1897 ld r7, STACK_SLOT_PID(r1)
1898 ld r8, STACK_SLOT_IAMR(r1)
1900 mtspr SPRN_PSSCR, r6
1903 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1905 #ifdef CONFIG_PPC_RADIX_MMU
1907 * Are we running hash or radix ?
1910 lbz r0, KVM_RADIX(r5)
1915 * Radix: do eieio; tlbsync; ptesync sequence in case we
1916 * interrupted the guest between a tlbie and a ptesync.
1922 /* Radix: Handle the case where the guest used an illegal PID */
1923 LOAD_REG_ADDR(r4, mmu_base_pid)
1924 lwz r3, VCPU_GUEST_PID(r9)
1930 * Illegal PID, the HW might have prefetched and cached in the TLB
1931 * some translations for the LPID 0 / guest PID combination which
1932 * Linux doesn't know about, so we need to flush that PID out of
1933 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1934 * the right context.
1940 /* Then do a congruence class local flush */
1942 lwz r0,KVM_TLB_SETS(r6)
1944 li r7,0x400 /* IS field = 0b01 */
1946 sldi r0,r3,32 /* RS has PID */
1947 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1952 2: /* Flush the ERAT on radix P9 DD1 guest exit */
1955 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
1957 #endif /* CONFIG_PPC_RADIX_MMU */
1960 * POWER7/POWER8 guest -> host partition switch code.
1961 * We don't have to lock against tlbies but we do
1962 * have to coordinate the hardware threads.
1963 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1965 kvmhv_switch_to_host:
1966 /* Secondary threads wait for primary to do partition switch */
1967 ld r5,HSTATE_KVM_VCORE(r13)
1968 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1969 lbz r3,HSTATE_PTID(r13)
1973 13: lbz r3,VCORE_IN_GUEST(r5)
1979 /* Primary thread waits for all the secondaries to exit guest */
1980 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1981 rlwinm r0,r3,32-8,0xff
1987 /* Did we actually switch to the guest at all? */
1988 lbz r6, VCORE_IN_GUEST(r5)
1992 /* Primary thread switches back to host partition */
1993 lwz r7,KVM_HOST_LPID(r4)
1995 ld r6,KVM_HOST_SDR1(r4)
1996 li r8,LPID_RSVD /* switch to reserved LPID */
1999 mtspr SPRN_SDR1,r6 /* switch to host page table */
2000 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
2005 /* DPDES and VTB are shared between threads */
2006 mfspr r7, SPRN_DPDES
2008 std r7, VCORE_DPDES(r5)
2009 std r8, VCORE_VTB(r5)
2010 /* clear DPDES so we don't get guest doorbells in the host */
2012 mtspr SPRN_DPDES, r8
2013 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2015 /* If HMI, call kvmppc_realmode_hmi_handler() */
2016 lwz r12, STACK_SLOT_TRAP(r1)
2017 cmpwi r12, BOOK3S_INTERRUPT_HMI
2019 bl kvmppc_realmode_hmi_handler
2023 * At this point kvmppc_realmode_hmi_handler may have resync-ed
2024 * the TB, and if it has, we must not subtract the guest timebase
2025 * offset from the timebase. So, skip it.
2027 * Also, do not call kvmppc_subcore_exit_guest() because it has
2028 * been invoked as part of kvmppc_realmode_hmi_handler().
2033 /* Subtract timebase offset from timebase */
2034 ld r8, VCORE_TB_OFFSET_APPL(r5)
2038 std r0, VCORE_TB_OFFSET_APPL(r5)
2039 mftb r6 /* current guest timebase */
2041 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
2042 mftb r7 /* check if lower 24 bits overflowed */
2047 addis r8,r8,0x100 /* if so, increment upper 40 bits */
2050 17: bl kvmppc_subcore_exit_guest
2052 30: ld r5,HSTATE_KVM_VCORE(r13)
2053 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
2056 ld r0, VCORE_PCR(r5)
2062 /* Signal secondary CPUs to continue */
2063 stb r0,VCORE_IN_GUEST(r5)
2064 19: lis r8,0x7fff /* MAX_INT@h */
2069 /* On POWER9 with HPT-on-radix we need to wait for all other threads */
2070 ld r3, HSTATE_SPLIT_MODE(r13)
2073 lwz r8, KVM_SPLIT_DO_RESTORE(r3)
2076 bl kvmhv_p9_restore_lpcr
2080 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2081 ld r8,KVM_HOST_LPCR(r4)
2085 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2086 /* Finish timing, if we have a vcpu */
2087 ld r4, HSTATE_KVM_VCPU(r13)
2091 bl kvmhv_accumulate_time
2094 /* Unset guest mode */
2095 li r0, KVM_GUEST_MODE_NONE
2096 stb r0, HSTATE_IN_GUEST(r13)
2098 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
2099 ld r0, SFS+PPC_LR_STKOFF(r1)
2104 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2106 * Softpatch interrupt for transactional memory emulation cases
2107 * on POWER9 DD2.2. This is early in the guest exit path - we
2108 * haven't saved registers or done a treclaim yet.
2111 /* Save instruction image in HEIR */
2113 stw r3, VCPU_HEIR(r9)
2116 * The cases we want to handle here are those where the guest
2117 * is in real suspend mode and is trying to transition to
2118 * transactional mode.
2120 lbz r0, HSTATE_FAKE_SUSPEND(r13)
2121 cmpwi r0, 0 /* keep exiting guest if in fake suspend */
2123 rldicl r3, r11, 64 - MSR_TS_S_LG, 62
2124 cmpwi r3, 1 /* or if not in suspend state */
2127 /* Call C code to do the emulation */
2129 bl kvmhv_p9_tm_emulation_early
2131 ld r9, HSTATE_KVM_VCPU(r13)
2132 li r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
2134 beq guest_exit_cont /* continue exiting if not handled */
2136 ld r11, VCPU_MSR(r9)
2137 b fast_interrupt_c_return /* go back to guest if handled */
2138 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2141 * Check whether an HDSI is an HPTE not found fault or something else.
2142 * If it is an HPTE not found fault that is due to the guest accessing
2143 * a page that they have mapped but which we have paged out, then
2144 * we continue on with the guest exit path. In all other cases,
2145 * reflect the HDSI to the guest as a DSI.
2149 lbz r0, KVM_RADIX(r3)
2151 mfspr r6, SPRN_HDSISR
2153 /* Look for DSISR canary. If we find it, retry instruction */
2156 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2158 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
2159 /* HPTE not found fault or protection fault? */
2160 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
2161 beq 1f /* if not, send it to the guest */
2162 andi. r0, r11, MSR_DR /* data relocation enabled? */
2165 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2167 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2169 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2170 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
2171 bne 7f /* if no SLB entry found */
2172 4: std r4, VCPU_FAULT_DAR(r9)
2173 stw r6, VCPU_FAULT_DSISR(r9)
2175 /* Search the hash table. */
2176 mr r3, r9 /* vcpu pointer */
2177 li r7, 1 /* data fault */
2178 bl kvmppc_hpte_hv_fault
2179 ld r9, HSTATE_KVM_VCPU(r13)
2181 ld r11, VCPU_MSR(r9)
2182 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
2183 cmpdi r3, 0 /* retry the instruction */
2185 cmpdi r3, -1 /* handle in kernel mode */
2187 cmpdi r3, -2 /* MMIO emulation; need instr word */
2190 /* Synthesize a DSI (or DSegI) for the guest */
2191 ld r4, VCPU_FAULT_DAR(r9)
2193 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
2194 mtspr SPRN_DSISR, r6
2195 7: mtspr SPRN_DAR, r4
2196 mtspr SPRN_SRR0, r10
2197 mtspr SPRN_SRR1, r11
2199 bl kvmppc_msr_interrupt
2200 fast_interrupt_c_return:
2201 6: ld r7, VCPU_CTR(r9)
2208 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2209 ld r5, KVM_VRMA_SLB_V(r5)
2212 /* If this is for emulated MMIO, load the instruction word */
2213 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2215 /* Set guest mode to 'jump over instruction' so if lwz faults
2216 * we'll just continue at the next IP. */
2217 li r0, KVM_GUEST_MODE_SKIP
2218 stb r0, HSTATE_IN_GUEST(r13)
2220 /* Do the access with MSR:DR enabled */
2222 ori r4, r3, MSR_DR /* Enable paging for data */
2227 /* Store the result */
2228 stw r8, VCPU_LAST_INST(r9)
2230 /* Unset guest mode. */
2231 li r0, KVM_GUEST_MODE_HOST_HV
2232 stb r0, HSTATE_IN_GUEST(r13)
2236 std r4, VCPU_FAULT_DAR(r9)
2237 stw r6, VCPU_FAULT_DSISR(r9)
2240 std r5, VCPU_FAULT_GPA(r9)
2244 * Similarly for an HISI, reflect it to the guest as an ISI unless
2245 * it is an HPTE not found fault for a page that we have paged out.
2249 lbz r0, KVM_RADIX(r3)
2251 bne .Lradix_hisi /* for radix, just save ASDR */
2252 andis. r0, r11, SRR1_ISI_NOPT@h
2254 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2257 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2259 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2261 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2262 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2263 bne 7f /* if no SLB entry found */
2265 /* Search the hash table. */
2266 mr r3, r9 /* vcpu pointer */
2269 li r7, 0 /* instruction fault */
2270 bl kvmppc_hpte_hv_fault
2271 ld r9, HSTATE_KVM_VCPU(r13)
2273 ld r11, VCPU_MSR(r9)
2274 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2275 cmpdi r3, 0 /* retry the instruction */
2276 beq fast_interrupt_c_return
2277 cmpdi r3, -1 /* handle in kernel mode */
2280 /* Synthesize an ISI (or ISegI) for the guest */
2282 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2283 7: mtspr SPRN_SRR0, r10
2284 mtspr SPRN_SRR1, r11
2286 bl kvmppc_msr_interrupt
2287 b fast_interrupt_c_return
2289 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2290 ld r5, KVM_VRMA_SLB_V(r6)
2294 * Try to handle an hcall in real mode.
2295 * Returns to the guest if we handle it, or continues on up to
2296 * the kernel if we can't (i.e. if we don't have a handler for
2297 * it, or if the handler returns H_TOO_HARD).
2299 * r5 - r8 contain hcall args,
2300 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2302 hcall_try_real_mode:
2303 ld r3,VCPU_GPR(R3)(r9)
2305 /* sc 1 from userspace - reflect to guest syscall */
2306 bne sc_1_fast_return
2308 cmpldi r3,hcall_real_table_end - hcall_real_table
2310 /* See if this hcall is enabled for in-kernel handling */
2312 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2313 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2315 ld r0, KVM_ENABLED_HCALLS(r4)
2316 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2320 /* Get pointer to handler, if any, and call it */
2321 LOAD_REG_ADDR(r4, hcall_real_table)
2327 mr r3,r9 /* get vcpu pointer */
2328 ld r4,VCPU_GPR(R4)(r9)
2331 beq hcall_real_fallback
2332 ld r4,HSTATE_KVM_VCPU(r13)
2333 std r3,VCPU_GPR(R3)(r4)
2341 li r10, BOOK3S_INTERRUPT_SYSCALL
2342 bl kvmppc_msr_interrupt
2346 /* We've attempted a real mode hcall, but it's punted it back
2347 * to userspace. We need to restore some clobbered volatiles
2348 * before resuming the pass-it-to-qemu path */
2349 hcall_real_fallback:
2350 li r12,BOOK3S_INTERRUPT_SYSCALL
2351 ld r9, HSTATE_KVM_VCPU(r13)
2355 .globl hcall_real_table
2357 .long 0 /* 0 - unused */
2358 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2359 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2360 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2361 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2362 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2363 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2364 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2365 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2366 .long 0 /* 0x24 - H_SET_SPRG0 */
2367 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2382 #ifdef CONFIG_KVM_XICS
2383 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2384 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2385 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2386 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2387 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2389 .long 0 /* 0x64 - H_EOI */
2390 .long 0 /* 0x68 - H_CPPR */
2391 .long 0 /* 0x6c - H_IPI */
2392 .long 0 /* 0x70 - H_IPOLL */
2393 .long 0 /* 0x74 - H_XIRR */
2421 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2422 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2438 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2442 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2443 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2444 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2556 #ifdef CONFIG_KVM_XICS
2557 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2559 .long 0 /* 0x2fc - H_XIRR_X*/
2561 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2562 .globl hcall_real_table_end
2563 hcall_real_table_end:
2565 _GLOBAL(kvmppc_h_set_xdabr)
2566 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2568 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2571 6: li r3, H_PARAMETER
2574 _GLOBAL(kvmppc_h_set_dabr)
2575 li r5, DABRX_USER | DABRX_KERNEL
2579 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2580 std r4,VCPU_DABR(r3)
2581 stw r5, VCPU_DABRX(r3)
2582 mtspr SPRN_DABRX, r5
2583 /* Work around P7 bug where DABR can get corrupted on mtspr */
2584 1: mtspr SPRN_DABR,r4
2594 /* POWER9 with disabled DAWR */
2597 END_FTR_SECTION_IFCLR(CPU_FTR_DAWR)
2598 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2599 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2600 rlwimi r5, r4, 2, DAWRX_WT
2602 std r4, VCPU_DAWR(r3)
2603 std r5, VCPU_DAWRX(r3)
2605 mtspr SPRN_DAWRX, r5
2609 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2611 std r11,VCPU_MSR(r3)
2613 stb r0,VCPU_CEDED(r3)
2614 sync /* order setting ceded vs. testing prodded */
2615 lbz r5,VCPU_PRODDED(r3)
2617 bne kvm_cede_prodded
2618 li r12,0 /* set trap to 0 to say hcall is handled */
2619 stw r12,VCPU_TRAP(r3)
2621 std r0,VCPU_GPR(R3)(r3)
2624 * Set our bit in the bitmask of napping threads unless all the
2625 * other threads are already napping, in which case we send this
2628 ld r5,HSTATE_KVM_VCORE(r13)
2629 lbz r6,HSTATE_PTID(r13)
2630 lwz r8,VCORE_ENTRY_EXIT(r5)
2634 addi r6,r5,VCORE_NAPPING_THREADS
2641 /* order napping_threads update vs testing entry_exit_map */
2644 stb r0,HSTATE_NAPPING(r13)
2645 lwz r7,VCORE_ENTRY_EXIT(r5)
2647 bge 33f /* another thread already exiting */
2650 * Although not specifically required by the architecture, POWER7
2651 * preserves the following registers in nap mode, even if an SMT mode
2652 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2653 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2655 /* Save non-volatile GPRs */
2656 std r14, VCPU_GPR(R14)(r3)
2657 std r15, VCPU_GPR(R15)(r3)
2658 std r16, VCPU_GPR(R16)(r3)
2659 std r17, VCPU_GPR(R17)(r3)
2660 std r18, VCPU_GPR(R18)(r3)
2661 std r19, VCPU_GPR(R19)(r3)
2662 std r20, VCPU_GPR(R20)(r3)
2663 std r21, VCPU_GPR(R21)(r3)
2664 std r22, VCPU_GPR(R22)(r3)
2665 std r23, VCPU_GPR(R23)(r3)
2666 std r24, VCPU_GPR(R24)(r3)
2667 std r25, VCPU_GPR(R25)(r3)
2668 std r26, VCPU_GPR(R26)(r3)
2669 std r27, VCPU_GPR(R27)(r3)
2670 std r28, VCPU_GPR(R28)(r3)
2671 std r29, VCPU_GPR(R29)(r3)
2672 std r30, VCPU_GPR(R30)(r3)
2673 std r31, VCPU_GPR(R31)(r3)
2678 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2680 * Branch around the call if both CPU_FTR_TM and
2681 * CPU_FTR_P9_TM_HV_ASSIST are off.
2685 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2687 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2689 ld r9, HSTATE_KVM_VCPU(r13)
2695 * Set DEC to the smaller of DEC and HDEC, so that we wake
2696 * no later than the end of our timeslice (HDEC interrupts
2697 * don't wake us from nap).
2703 /* On P9 check whether the guest has large decrementer mode enabled */
2704 ld r6, HSTATE_KVM_VCORE(r13)
2705 ld r6, VCORE_LPCR(r6)
2706 andis. r6, r6, LPCR_LD@h
2708 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2715 /* save expiry time of guest decrementer */
2717 ld r4, HSTATE_KVM_VCPU(r13)
2718 ld r5, HSTATE_KVM_VCORE(r13)
2719 ld r6, VCORE_TB_OFFSET_APPL(r5)
2720 subf r3, r6, r3 /* convert to host TB value */
2721 std r3, VCPU_DEC_EXPIRES(r4)
2723 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2724 ld r4, HSTATE_KVM_VCPU(r13)
2725 addi r3, r4, VCPU_TB_CEDE
2726 bl kvmhv_accumulate_time
2729 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2732 * Take a nap until a decrementer or external or doobell interrupt
2733 * occurs, with PECE1 and PECE0 set in LPCR.
2734 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2735 * Also clear the runlatch bit before napping.
2738 mfspr r0, SPRN_CTRLF
2740 mtspr SPRN_CTRLT, r0
2743 stb r0,HSTATE_HWTHREAD_REQ(r13)
2745 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2747 ori r5, r5, LPCR_PECEDH
2748 rlwimi r5, r3, 0, LPCR_PECEDP
2749 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2751 kvm_nap_sequence: /* desired LPCR value in r5 */
2754 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2755 * enable state loss = 1 (allow SMT mode switch)
2756 * requested level = 0 (just stop dispatching)
2758 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2759 mtspr SPRN_PSSCR, r3
2760 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2761 li r4, LPCR_PECE_HVEE@higher
2764 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2768 std r0, HSTATE_SCRATCH0(r13)
2770 ld r0, HSTATE_SCRATCH0(r13)
2777 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
2786 /* get vcpu pointer */
2787 ld r4, HSTATE_KVM_VCPU(r13)
2789 /* Woken by external or decrementer interrupt */
2790 ld r1, HSTATE_HOST_R1(r13)
2792 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2793 addi r3, r4, VCPU_TB_RMINTR
2794 bl kvmhv_accumulate_time
2797 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2799 * Branch around the call if both CPU_FTR_TM and
2800 * CPU_FTR_P9_TM_HV_ASSIST are off.
2804 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2806 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2808 bl kvmppc_restore_tm
2812 /* load up FP state */
2815 /* Restore guest decrementer */
2816 ld r3, VCPU_DEC_EXPIRES(r4)
2817 ld r5, HSTATE_KVM_VCORE(r13)
2818 ld r6, VCORE_TB_OFFSET_APPL(r5)
2819 add r3, r3, r6 /* convert host TB to guest TB value */
2825 ld r14, VCPU_GPR(R14)(r4)
2826 ld r15, VCPU_GPR(R15)(r4)
2827 ld r16, VCPU_GPR(R16)(r4)
2828 ld r17, VCPU_GPR(R17)(r4)
2829 ld r18, VCPU_GPR(R18)(r4)
2830 ld r19, VCPU_GPR(R19)(r4)
2831 ld r20, VCPU_GPR(R20)(r4)
2832 ld r21, VCPU_GPR(R21)(r4)
2833 ld r22, VCPU_GPR(R22)(r4)
2834 ld r23, VCPU_GPR(R23)(r4)
2835 ld r24, VCPU_GPR(R24)(r4)
2836 ld r25, VCPU_GPR(R25)(r4)
2837 ld r26, VCPU_GPR(R26)(r4)
2838 ld r27, VCPU_GPR(R27)(r4)
2839 ld r28, VCPU_GPR(R28)(r4)
2840 ld r29, VCPU_GPR(R29)(r4)
2841 ld r30, VCPU_GPR(R30)(r4)
2842 ld r31, VCPU_GPR(R31)(r4)
2844 /* Check the wake reason in SRR1 to see why we got here */
2845 bl kvmppc_check_wake_reason
2848 * Restore volatile registers since we could have called a
2849 * C routine in kvmppc_check_wake_reason
2851 * r3 tells us whether we need to return to host or not
2852 * WARNING: it gets checked further down:
2853 * should not modify r3 until this check is done.
2855 ld r4, HSTATE_KVM_VCPU(r13)
2857 /* clear our bit in vcore->napping_threads */
2858 34: ld r5,HSTATE_KVM_VCORE(r13)
2859 lbz r7,HSTATE_PTID(r13)
2862 addi r6,r5,VCORE_NAPPING_THREADS
2868 stb r0,HSTATE_NAPPING(r13)
2870 /* See if the wake reason saved in r3 means we need to exit */
2871 stw r12, VCPU_TRAP(r4)
2876 /* see if any other thread is already exiting */
2877 lwz r0,VCORE_ENTRY_EXIT(r5)
2881 b kvmppc_cede_reentry /* if not go back to guest */
2883 /* cede when already previously prodded case */
2886 stb r0,VCPU_PRODDED(r3)
2887 sync /* order testing prodded vs. clearing ceded */
2888 stb r0,VCPU_CEDED(r3)
2892 /* we've ceded but we want to give control to the host */
2894 ld r9, HSTATE_KVM_VCPU(r13)
2895 #ifdef CONFIG_KVM_XICS
2896 /* Abort if we still have a pending escalation */
2897 lbz r5, VCPU_XIVE_ESC_ON(r9)
2901 stb r0, VCPU_CEDED(r9)
2902 1: /* Enable XIVE escalation */
2903 li r5, XIVE_ESB_SET_PQ_00
2905 andi. r0, r0, MSR_DR /* in real mode? */
2907 ld r10, VCPU_XIVE_ESC_VADDR(r9)
2912 1: ld r10, VCPU_XIVE_ESC_RADDR(r9)
2918 stb r0, VCPU_XIVE_ESC_ON(r9)
2919 #endif /* CONFIG_KVM_XICS */
2920 3: b guest_exit_cont
2922 /* Try to handle a machine check in real mode */
2923 machine_check_realmode:
2924 mr r3, r9 /* get vcpu pointer */
2925 bl kvmppc_realmode_machine_check
2927 ld r9, HSTATE_KVM_VCPU(r13)
2928 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2930 * For the guest that is FWNMI capable, deliver all the MCE errors
2931 * (handled/unhandled) by exiting the guest with KVM_EXIT_NMI exit
2932 * reason. This new approach injects machine check errors in guest
2933 * address space to guest with additional information in the form
2934 * of RTAS event, thus enabling guest kernel to suitably handle
2937 * For the guest that is not FWNMI capable (old QEMU) fallback
2938 * to old behaviour for backward compatibility:
2939 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest either
2940 * through machine check interrupt (set HSRR0 to 0x200).
2941 * For handled errors (no-fatal), just go back to guest execution
2942 * with current HSRR0.
2943 * if we receive machine check with MSR(RI=0) then deliver it to
2944 * guest as machine check causing guest to crash.
2946 ld r11, VCPU_MSR(r9)
2947 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2948 bne mc_cont /* if so, exit to host */
2949 /* Check if guest is capable of handling NMI exit */
2950 ld r10, VCPU_KVM(r9)
2951 lbz r10, KVM_FWNMI(r10)
2952 cmpdi r10, 1 /* FWNMI capable? */
2953 beq mc_cont /* if so, exit with KVM_EXIT_NMI. */
2955 /* if not, fall through for backward compatibility. */
2956 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2957 beq 1f /* Deliver a machine check to guest */
2959 cmpdi r3, 0 /* Did we handle MCE ? */
2960 bne 2f /* Continue guest execution. */
2961 /* If not, deliver a machine check. SRR0/1 are already set */
2962 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2963 bl kvmppc_msr_interrupt
2964 2: b fast_interrupt_c_return
2967 * Check the reason we woke from nap, and take appropriate action.
2969 * 0 if nothing needs to be done
2970 * 1 if something happened that needs to be handled by the host
2971 * -1 if there was a guest wakeup (IPI or msgsnd)
2972 * -2 if we handled a PCI passthrough interrupt (returned by
2973 * kvmppc_read_intr only)
2975 * Also sets r12 to the interrupt vector for any interrupt that needs
2976 * to be handled now by the host (0x500 for external interrupt), or zero.
2977 * Modifies all volatile registers (since it may call a C function).
2978 * This routine calls kvmppc_read_intr, a C function, if an external
2979 * interrupt is pending.
2981 kvmppc_check_wake_reason:
2984 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2986 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2987 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2988 cmpwi r6, 8 /* was it an external interrupt? */
2989 beq 7f /* if so, see what it was */
2992 cmpwi r6, 6 /* was it the decrementer? */
2995 cmpwi r6, 5 /* privileged doorbell? */
2997 cmpwi r6, 3 /* hypervisor doorbell? */
2999 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3000 cmpwi r6, 0xa /* Hypervisor maintenance ? */
3002 li r3, 1 /* anything else, return 1 */
3005 /* hypervisor doorbell */
3006 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
3009 * Clear the doorbell as we will invoke the handler
3010 * explicitly in the guest exit path.
3012 lis r6, (PPC_DBELL_SERVER << (63-36))@h
3014 /* see if it's a host IPI */
3019 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
3020 lbz r0, HSTATE_HOST_IPI(r13)
3023 /* if not, return -1 */
3027 /* Woken up due to Hypervisor maintenance interrupt */
3028 4: li r12, BOOK3S_INTERRUPT_HMI
3032 /* external interrupt - create a stack frame so we can call C */
3034 std r0, PPC_LR_STKOFF(r1)
3035 stdu r1, -PPC_MIN_STKFRM(r1)
3038 li r12, BOOK3S_INTERRUPT_EXTERNAL
3043 * Return code of 2 means PCI passthrough interrupt, but
3044 * we need to return back to host to complete handling the
3045 * interrupt. Trap reason is expected in r12 by guest
3048 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
3050 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
3051 addi r1, r1, PPC_MIN_STKFRM
3056 * Save away FP, VMX and VSX registers.
3058 * N.B. r30 and r31 are volatile across this function,
3059 * thus it is not callable from C.
3066 #ifdef CONFIG_ALTIVEC
3068 oris r8,r8,MSR_VEC@h
3069 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3073 oris r8,r8,MSR_VSX@h
3074 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3077 addi r3,r3,VCPU_FPRS
3079 #ifdef CONFIG_ALTIVEC
3081 addi r3,r31,VCPU_VRS
3083 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3085 mfspr r6,SPRN_VRSAVE
3086 stw r6,VCPU_VRSAVE(r31)
3091 * Load up FP, VMX and VSX registers
3093 * N.B. r30 and r31 are volatile across this function,
3094 * thus it is not callable from C.
3101 #ifdef CONFIG_ALTIVEC
3103 oris r8,r8,MSR_VEC@h
3104 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3108 oris r8,r8,MSR_VSX@h
3109 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3112 addi r3,r4,VCPU_FPRS
3114 #ifdef CONFIG_ALTIVEC
3116 addi r3,r31,VCPU_VRS
3118 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3120 lwz r7,VCPU_VRSAVE(r31)
3121 mtspr SPRN_VRSAVE,r7
3126 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
3128 * Save transactional state and TM-related registers.
3129 * Called with r9 pointing to the vcpu struct.
3130 * This can modify all checkpointed registers, but
3131 * restores r1, r2 and r9 (vcpu pointer) before exit.
3135 std r0, PPC_LR_STKOFF(r1)
3136 stdu r1, -PPC_MIN_STKFRM(r1)
3141 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
3145 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3146 beq 1f /* TM not active in guest. */
3148 std r1, HSTATE_HOST_R1(r13)
3149 li r3, TM_CAUSE_KVM_RESCHED
3152 lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
3155 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
3157 BEGIN_FTR_SECTION_NESTED(96)
3158 bl pnv_power9_force_smt4_catch
3159 END_FTR_SECTION_NESTED(CPU_FTR_P9_TM_XER_SO_BUG, CPU_FTR_P9_TM_XER_SO_BUG, 96)
3163 /* Emulation of the treclaim instruction needs TEXASR before treclaim */
3164 mfspr r6, SPRN_TEXASR
3165 std r6, VCPU_ORIG_TEXASR(r9)
3167 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
3169 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
3173 /* All GPRs are volatile at this point. */
3176 /* Temporarily store r13 and r9 so we have some regs to play with */
3179 std r9, PACATMSCRATCH(r13)
3181 /* If doing TM emulation on POWER9 DD2.2, check for fake suspend mode */
3183 lbz r9, HSTATE_FAKE_SUSPEND(r13)
3187 * We were in fake suspend, so we are not going to save the
3188 * register state as the guest checkpointed state (since
3189 * we already have it), therefore we can now use any volatile GPR.
3191 /* Reload stack pointer and TOC. */
3192 ld r1, HSTATE_HOST_R1(r13)
3194 /* Set MSR RI now we have r1 and r13 back. */
3198 ld r6, HSTATE_DSCR(r13)
3200 BEGIN_FTR_SECTION_NESTED(96)
3201 bl pnv_power9_force_smt4_release
3202 END_FTR_SECTION_NESTED(CPU_FTR_P9_TM_XER_SO_BUG, CPU_FTR_P9_TM_XER_SO_BUG, 96)
3206 mfspr r3, SPRN_PSSCR
3207 /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */
3208 li r0, PSSCR_FAKE_SUSPEND
3210 mtspr SPRN_PSSCR, r3
3211 ld r9, HSTATE_KVM_VCPU(r13)
3212 /* Don't save TEXASR, use value from last exit in real suspend state */
3215 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
3217 ld r9, HSTATE_KVM_VCPU(r13)
3219 /* Get a few more GPRs free. */
3220 std r29, VCPU_GPRS_TM(29)(r9)
3221 std r30, VCPU_GPRS_TM(30)(r9)
3222 std r31, VCPU_GPRS_TM(31)(r9)
3224 /* Save away PPR and DSCR soon so don't run with user values. */
3227 mfspr r30, SPRN_DSCR
3228 ld r29, HSTATE_DSCR(r13)
3229 mtspr SPRN_DSCR, r29
3231 /* Save all but r9, r13 & r29-r31 */
3234 .if (reg != 9) && (reg != 13)
3235 std reg, VCPU_GPRS_TM(reg)(r9)
3239 /* ... now save r13 */
3241 std r4, VCPU_GPRS_TM(13)(r9)
3242 /* ... and save r9 */
3243 ld r4, PACATMSCRATCH(r13)
3244 std r4, VCPU_GPRS_TM(9)(r9)
3246 /* Reload stack pointer and TOC. */
3247 ld r1, HSTATE_HOST_R1(r13)
3250 /* Set MSR RI now we have r1 and r13 back. */
3254 /* Save away checkpinted SPRs. */
3255 std r31, VCPU_PPR_TM(r9)
3256 std r30, VCPU_DSCR_TM(r9)
3263 std r5, VCPU_LR_TM(r9)
3264 stw r6, VCPU_CR_TM(r9)
3265 std r7, VCPU_CTR_TM(r9)
3266 std r8, VCPU_AMR_TM(r9)
3267 std r10, VCPU_TAR_TM(r9)
3268 std r11, VCPU_XER_TM(r9)
3270 /* Restore r12 as trap number. */
3271 lwz r12, VCPU_TRAP(r9)
3274 addi r3, r9, VCPU_FPRS_TM
3276 addi r3, r9, VCPU_VRS_TM
3278 mfspr r6, SPRN_VRSAVE
3279 stw r6, VCPU_VRSAVE_TM(r9)
3282 * We need to save these SPRs after the treclaim so that the software
3283 * error code is recorded correctly in the TEXASR. Also the user may
3284 * change these outside of a transaction, so they must always be
3287 mfspr r7, SPRN_TEXASR
3288 std r7, VCPU_TEXASR(r9)
3290 mfspr r5, SPRN_TFHAR
3291 mfspr r6, SPRN_TFIAR
3292 std r5, VCPU_TFHAR(r9)
3293 std r6, VCPU_TFIAR(r9)
3295 addi r1, r1, PPC_MIN_STKFRM
3296 ld r0, PPC_LR_STKOFF(r1)
3301 * Restore transactional state and TM-related registers.
3302 * Called with r4 pointing to the vcpu struct.
3303 * This potentially modifies all checkpointed registers.
3304 * It restores r1, r2, r4 from the PACA.
3308 std r0, PPC_LR_STKOFF(r1)
3310 /* Turn on TM/FP/VSX/VMX so we can restore them. */
3316 oris r5, r5, (MSR_VEC | MSR_VSX)@h
3320 * The user may change these outside of a transaction, so they must
3321 * always be context switched.
3323 ld r5, VCPU_TFHAR(r4)
3324 ld r6, VCPU_TFIAR(r4)
3325 ld r7, VCPU_TEXASR(r4)
3326 mtspr SPRN_TFHAR, r5
3327 mtspr SPRN_TFIAR, r6
3328 mtspr SPRN_TEXASR, r7
3331 stb r0, HSTATE_FAKE_SUSPEND(r13)
3333 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3334 beqlr /* TM not active in guest */
3335 std r1, HSTATE_HOST_R1(r13)
3337 /* Make sure the failure summary is set, otherwise we'll program check
3338 * when we trechkpt. It's possible that this might have been not set
3339 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
3342 oris r7, r7, (TEXASR_FS)@h
3343 mtspr SPRN_TEXASR, r7
3346 * If we are doing TM emulation for the guest on a POWER9 DD2,
3347 * then we don't actually do a trechkpt -- we either set up
3348 * fake-suspend mode, or emulate a TM rollback.
3352 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
3355 * We need to load up the checkpointed state for the guest.
3356 * We need to do this early as it will blow away any GPRs, VSRs and
3361 addi r3, r31, VCPU_FPRS_TM
3363 addi r3, r31, VCPU_VRS_TM
3366 lwz r7, VCPU_VRSAVE_TM(r4)
3367 mtspr SPRN_VRSAVE, r7
3369 ld r5, VCPU_LR_TM(r4)
3370 lwz r6, VCPU_CR_TM(r4)
3371 ld r7, VCPU_CTR_TM(r4)
3372 ld r8, VCPU_AMR_TM(r4)
3373 ld r9, VCPU_TAR_TM(r4)
3374 ld r10, VCPU_XER_TM(r4)
3383 * Load up PPR and DSCR values but don't put them in the actual SPRs
3384 * till the last moment to avoid running with userspace PPR and DSCR for
3387 ld r29, VCPU_DSCR_TM(r4)
3388 ld r30, VCPU_PPR_TM(r4)
3390 std r2, PACATMSCRATCH(r13) /* Save TOC */
3392 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
3396 /* Load GPRs r0-r28 */
3399 ld reg, VCPU_GPRS_TM(reg)(r31)
3403 mtspr SPRN_DSCR, r29
3406 /* Load final GPRs */
3407 ld 29, VCPU_GPRS_TM(29)(r31)
3408 ld 30, VCPU_GPRS_TM(30)(r31)
3409 ld 31, VCPU_GPRS_TM(31)(r31)
3411 /* TM checkpointed state is now setup. All GPRs are now volatile. */
3414 /* Now let's get back the state we need. */
3417 ld r29, HSTATE_DSCR(r13)
3418 mtspr SPRN_DSCR, r29
3419 ld r4, HSTATE_KVM_VCPU(r13)
3420 ld r1, HSTATE_HOST_R1(r13)
3421 ld r2, PACATMSCRATCH(r13)
3423 /* Set the MSR RI since we have our registers back. */
3427 ld r0, PPC_LR_STKOFF(r1)
3432 cmpwi r5, 1 /* check for suspended state */
3434 stb r5, HSTATE_FAKE_SUSPEND(r13)
3435 b 9b /* and return */
3436 10: stdu r1, -PPC_MIN_STKFRM(r1)
3437 /* guest is in transactional state, so simulate rollback */
3439 bl kvmhv_emulate_tm_rollback
3441 ld r4, HSTATE_KVM_VCPU(r13) /* our vcpu pointer has been trashed */
3442 addi r1, r1, PPC_MIN_STKFRM
3447 * We come here if we get any exception or interrupt while we are
3448 * executing host real mode code while in guest MMU context.
3449 * r12 is (CR << 32) | vector
3450 * r13 points to our PACA
3451 * r12 is saved in HSTATE_SCRATCH0(r13)
3452 * ctr is saved in HSTATE_SCRATCH1(r13) if RELOCATABLE
3453 * r9 is saved in HSTATE_SCRATCH2(r13)
3454 * r13 is saved in HSPRG1
3455 * cfar is saved in HSTATE_CFAR(r13)
3456 * ppr is saved in HSTATE_PPR(r13)
3458 kvmppc_bad_host_intr:
3460 * Switch to the emergency stack, but start half-way down in
3461 * case we were already on it.
3465 ld r1, PACAEMERGSP(r13)
3466 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
3479 mfspr r3, SPRN_HSRR0
3480 mfspr r4, SPRN_HSRR1
3482 mfspr r6, SPRN_HDSISR
3484 1: mfspr r3, SPRN_SRR0
3487 mfspr r6, SPRN_DSISR
3492 ld r9, HSTATE_SCRATCH2(r13)
3493 ld r12, HSTATE_SCRATCH0(r13)
3498 ld r5, HSTATE_CFAR(r13)
3499 std r5, ORIG_GPR3(r1)
3501 #ifdef CONFIG_RELOCATABLE
3502 ld r4, HSTATE_SCRATCH1(r13)
3507 lbz r6, PACAIRQSOFTMASK(r13)
3513 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
3514 std r3, STACK_FRAME_OVERHEAD-16(r1)
3517 * On POWER9 do a minimal restore of the MMU and call C code,
3518 * which will print a message and panic.
3519 * XXX On POWER7 and POWER8, we just spin here since we don't
3520 * know what the other threads are doing (and we don't want to
3521 * coordinate with them) - but at least we now have register state
3522 * in memory that we might be able to look at from another CPU.
3526 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
3527 ld r9, HSTATE_KVM_VCPU(r13)
3528 ld r10, VCPU_KVM(r9)
3533 mtspr SPRN_CIABR, r0
3534 mtspr SPRN_DAWRX, r0
3536 /* Flush the ERAT on radix P9 DD1 guest exit */
3539 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
3541 BEGIN_MMU_FTR_SECTION
3543 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
3548 ld r8, PACA_SLBSHADOWPTR(r13)
3549 .rept SLB_NUM_BOLTED
3550 li r3, SLBSHADOW_SAVEAREA
3554 andis. r7, r5, SLB_ESID_V@h
3560 4: lwz r7, KVM_HOST_LPID(r10)
3563 ld r8, KVM_HOST_LPCR(r10)
3566 li r0, KVM_GUEST_MODE_NONE
3567 stb r0, HSTATE_IN_GUEST(r13)
3570 * Turn on the MMU and jump to C code
3574 addi r3, r3, 9f - 5b
3575 ld r4, PACAKMSR(r13)
3579 9: addi r3, r1, STACK_FRAME_OVERHEAD
3580 bl kvmppc_bad_interrupt
3584 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3585 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3586 * r11 has the guest MSR value (in/out)
3587 * r9 has a vcpu pointer (in)
3588 * r0 is used as a scratch register
3590 kvmppc_msr_interrupt:
3591 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3592 cmpwi r0, 2 /* Check if we are in transactional state.. */
3593 ld r11, VCPU_INTR_MSR(r9)
3595 /* ... if transactional, change to suspended */
3597 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3601 * This works around a hardware bug on POWER8E processors, where
3602 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3603 * performance monitor interrupt. Instead, when we need to have
3604 * an interrupt pending, we have to arrange for a counter to overflow.
3608 mtspr SPRN_MMCR2, r3
3609 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3610 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3611 mtspr SPRN_MMCR0, r3
3618 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3620 * Start timing an activity
3621 * r3 = pointer to time accumulation struct, r4 = vcpu
3624 ld r5, HSTATE_KVM_VCORE(r13)
3625 ld r6, VCORE_TB_OFFSET_APPL(r5)
3627 subf r5, r6, r5 /* subtract current timebase offset */
3628 std r3, VCPU_CUR_ACTIVITY(r4)
3629 std r5, VCPU_ACTIVITY_START(r4)
3633 * Accumulate time to one activity and start another.
3634 * r3 = pointer to new time accumulation struct, r4 = vcpu
3636 kvmhv_accumulate_time:
3637 ld r5, HSTATE_KVM_VCORE(r13)
3638 ld r8, VCORE_TB_OFFSET_APPL(r5)
3639 ld r5, VCPU_CUR_ACTIVITY(r4)
3640 ld r6, VCPU_ACTIVITY_START(r4)
3641 std r3, VCPU_CUR_ACTIVITY(r4)
3643 subf r7, r8, r7 /* subtract current timebase offset */
3644 std r7, VCPU_ACTIVITY_START(r4)
3648 ld r8, TAS_SEQCOUNT(r5)
3651 std r8, TAS_SEQCOUNT(r5)
3653 ld r7, TAS_TOTAL(r5)
3655 std r7, TAS_TOTAL(r5)
3661 3: std r3, TAS_MIN(r5)
3667 std r8, TAS_SEQCOUNT(r5)