3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/memory.h>
39 #include <linux/nmi.h>
42 #include <asm/kdump.h>
44 #include <asm/processor.h>
45 #include <asm/pgtable.h>
48 #include <asm/machdep.h>
51 #include <asm/cputable.h>
52 #include <asm/dt_cpu_ftrs.h>
53 #include <asm/sections.h>
54 #include <asm/btext.h>
55 #include <asm/nvram.h>
56 #include <asm/setup.h>
58 #include <asm/iommu.h>
59 #include <asm/serial.h>
60 #include <asm/cache.h>
63 #include <asm/firmware.h>
66 #include <asm/kexec.h>
67 #include <asm/code-patching.h>
68 #include <asm/livepatch.h>
70 #include <asm/cputhreads.h>
75 #define DBG(fmt...) udbg_printf(fmt)
80 int spinning_secondaries;
83 struct ppc64_caches ppc64_caches = {
93 EXPORT_SYMBOL_GPL(ppc64_caches);
95 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
96 void __init setup_tlb_core_data(void)
100 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
102 for_each_possible_cpu(cpu) {
103 int first = cpu_first_thread_sibling(cpu);
106 * If we boot via kdump on a non-primary thread,
107 * make sure we point at the thread that actually
110 if (cpu_first_thread_sibling(boot_cpuid) == first)
113 paca[cpu].tcd_ptr = &paca[first].tcd;
116 * If we have threads, we need either tlbsrx.
117 * or e6500 tablewalk mode, or else TLB handlers
118 * will be racy and could produce duplicate entries.
119 * Should we panic instead?
121 WARN_ONCE(smt_enabled_at_boot >= 2 &&
122 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
123 book3e_htw_mode != PPC_HTW_E6500,
124 "%s: unsupported MMU configuration\n", __func__);
131 static char *smt_enabled_cmdline;
133 /* Look for ibm,smt-enabled OF option */
134 void __init check_smt_enabled(void)
136 struct device_node *dn;
137 const char *smt_option;
139 /* Default to enabling all threads */
140 smt_enabled_at_boot = threads_per_core;
142 /* Allow the command line to overrule the OF option */
143 if (smt_enabled_cmdline) {
144 if (!strcmp(smt_enabled_cmdline, "on"))
145 smt_enabled_at_boot = threads_per_core;
146 else if (!strcmp(smt_enabled_cmdline, "off"))
147 smt_enabled_at_boot = 0;
152 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
154 smt_enabled_at_boot =
155 min(threads_per_core, smt);
158 dn = of_find_node_by_path("/options");
160 smt_option = of_get_property(dn, "ibm,smt-enabled",
164 if (!strcmp(smt_option, "on"))
165 smt_enabled_at_boot = threads_per_core;
166 else if (!strcmp(smt_option, "off"))
167 smt_enabled_at_boot = 0;
175 /* Look for smt-enabled= cmdline option */
176 static int __init early_smt_enabled(char *p)
178 smt_enabled_cmdline = p;
181 early_param("smt-enabled", early_smt_enabled);
183 #endif /* CONFIG_SMP */
185 /** Fix up paca fields required for the boot cpu */
186 static void __init fixup_boot_paca(void)
188 /* The boot cpu is started */
189 get_paca()->cpu_start = 1;
190 /* Allow percpu accesses to work until we setup percpu data */
191 get_paca()->data_offset = 0;
194 static void __init configure_exceptions(void)
197 * Setup the trampolines from the lowmem exception vectors
198 * to the kdump kernel when not using a relocatable kernel.
200 setup_kdump_trampoline();
202 /* Under a PAPR hypervisor, we need hypercalls */
203 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
204 /* Enable AIL if possible */
205 pseries_enable_reloc_on_exc();
208 * Tell the hypervisor that we want our exceptions to
209 * be taken in little endian mode.
211 * We don't call this for big endian as our calling convention
212 * makes us always enter in BE, and the call may fail under
213 * some circumstances with kdump.
215 #ifdef __LITTLE_ENDIAN__
216 pseries_little_endian_exceptions();
219 /* Set endian mode using OPAL */
220 if (firmware_has_feature(FW_FEATURE_OPAL))
221 opal_configure_cores();
223 /* AIL on native is done in cpu_ready_for_interrupts() */
227 static void cpu_ready_for_interrupts(void)
230 * Enable AIL if supported, and we are in hypervisor mode. This
231 * is called once for every processor.
233 * If we are not in hypervisor mode the job is done once for
234 * the whole partition in configure_exceptions().
236 if (cpu_has_feature(CPU_FTR_HVMODE) &&
237 cpu_has_feature(CPU_FTR_ARCH_207S)) {
238 unsigned long lpcr = mfspr(SPRN_LPCR);
239 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
243 * Fixup HFSCR:TM based on CPU features. The bit is set by our
244 * early asm init because at that point we haven't updated our
245 * CPU features from firmware and device-tree. Here we have,
248 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
249 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
251 /* Set IR and DR in PACA MSR */
252 get_paca()->kernel_msr = MSR_KERNEL;
256 * Early initialization entry point. This is called by head.S
257 * with MMU translation disabled. We rely on the "feature" of
258 * the CPU that ignores the top 2 bits of the address in real
259 * mode so we can access kernel globals normally provided we
260 * only toy with things in the RMO region. From here, we do
261 * some early parsing of the device-tree to setup out MEMBLOCK
262 * data structures, and allocate & initialize the hash table
263 * and segment tables so we can start running with translation
266 * It is this function which will call the probe() callback of
267 * the various platform types and copy the matching one to the
268 * global ppc_md structure. Your platform can eventually do
269 * some very early initializations from the probe() routine, but
270 * this is not recommended, be very careful as, for example, the
271 * device-tree is not accessible via normal means at this point.
274 void __init early_setup(unsigned long dt_ptr)
276 static __initdata struct paca_struct boot_paca;
278 /* -------- printk is _NOT_ safe to use here ! ------- */
280 /* Try new device tree based feature discovery ... */
281 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
282 /* Otherwise use the old style CPU table */
283 identify_cpu(0, mfspr(SPRN_PVR));
285 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
286 initialise_paca(&boot_paca, 0);
287 setup_paca(&boot_paca);
290 /* -------- printk is now safe to use ------- */
292 /* Enable early debugging if any specified (see udbg.h) */
295 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
298 * Do early initialization using the flattened device
299 * tree, such as retrieving the physical memory map or
300 * calculating/retrieving the hash table size.
302 early_init_devtree(__va(dt_ptr));
304 /* Now we know the logical id of our boot cpu, setup the paca. */
305 setup_paca(&paca[boot_cpuid]);
309 * Configure exception handlers. This include setting up trampolines
310 * if needed, setting exception endian mode, etc...
312 configure_exceptions();
314 /* Apply all the dynamic patching */
315 apply_feature_fixups();
316 setup_feature_keys();
318 /* Initialize the hash table or TLB handling */
322 * After firmware and early platform setup code has set things up,
323 * we note the SPR values for configurable control/performance
324 * registers, and use those as initial defaults.
326 record_spr_defaults();
329 * At this point, we can let interrupts switch to virtual mode
330 * (the MMU has been setup), so adjust the MSR in the PACA to
331 * have IR and DR set and enable AIL if it exists
333 cpu_ready_for_interrupts();
335 DBG(" <- early_setup()\n");
337 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
339 * This needs to be done *last* (after the above DBG() even)
341 * Right after we return from this function, we turn on the MMU
342 * which means the real-mode access trick that btext does will
343 * no longer work, it needs to switch to using a real MMU
344 * mapping. This call will ensure that it does
347 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
351 void early_setup_secondary(void)
353 /* Mark interrupts disabled in PACA */
354 get_paca()->soft_enabled = 0;
356 /* Initialize the hash table or TLB handling */
357 early_init_mmu_secondary();
360 * At this point, we can let interrupts switch to virtual mode
361 * (the MMU has been setup), so adjust the MSR in the PACA to
362 * have IR and DR set.
364 cpu_ready_for_interrupts();
367 #endif /* CONFIG_SMP */
369 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
370 static bool use_spinloop(void)
372 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
374 * See comments in head_64.S -- not all platforms insert
375 * secondaries at __secondary_hold and wait at the spin
378 if (firmware_has_feature(FW_FEATURE_OPAL))
384 * When book3e boots from kexec, the ePAPR spin table does
387 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
390 void smp_release_cpus(void)
398 DBG(" -> smp_release_cpus()\n");
400 /* All secondary cpus are spinning on a common spinloop, release them
401 * all now so they can start to spin on their individual paca
402 * spinloops. For non SMP kernels, the secondary cpus never get out
403 * of the common spinloop.
406 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
408 *ptr = ppc_function_entry(generic_secondary_smp_init);
410 /* And wait a bit for them to catch up */
411 for (i = 0; i < 100000; i++) {
414 if (spinning_secondaries == 0)
418 DBG("spinning_secondaries = %d\n", spinning_secondaries);
420 DBG(" <- smp_release_cpus()\n");
422 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
425 * Initialize some remaining members of the ppc64_caches and systemcfg
427 * (at least until we get rid of them completely). This is mostly some
428 * cache informations about the CPU that will be used by cache flush
429 * routines and/or provided to userland
432 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
437 info->line_size = lsize;
438 info->block_size = bsize;
439 info->log_block_size = __ilog2(bsize);
441 info->blocks_per_page = PAGE_SIZE / bsize;
443 info->blocks_per_page = 0;
446 info->assoc = 0xffff;
448 info->assoc = size / (sets * lsize);
451 static bool __init parse_cache_info(struct device_node *np,
453 struct ppc_cache_info *info)
455 static const char *ipropnames[] __initdata = {
458 "i-cache-block-size",
461 static const char *dpropnames[] __initdata = {
464 "d-cache-block-size",
467 const char **propnames = icache ? ipropnames : dpropnames;
468 const __be32 *sizep, *lsizep, *bsizep, *setsp;
469 u32 size, lsize, bsize, sets;
474 lsize = bsize = cur_cpu_spec->dcache_bsize;
475 sizep = of_get_property(np, propnames[0], NULL);
477 size = be32_to_cpu(*sizep);
478 setsp = of_get_property(np, propnames[1], NULL);
480 sets = be32_to_cpu(*setsp);
481 bsizep = of_get_property(np, propnames[2], NULL);
482 lsizep = of_get_property(np, propnames[3], NULL);
486 lsize = be32_to_cpu(*lsizep);
488 bsize = be32_to_cpu(*bsizep);
489 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
493 * OF is weird .. it represents fully associative caches
494 * as "1 way" which doesn't make much sense and doesn't
495 * leave room for direct mapped. We'll assume that 0
496 * in OF means direct mapped for that reason.
503 init_cache_info(info, size, lsize, bsize, sets);
508 void __init initialize_cache_info(void)
510 struct device_node *cpu = NULL, *l2, *l3 = NULL;
513 DBG(" -> initialize_cache_info()\n");
516 * All shipping POWER8 machines have a firmware bug that
517 * puts incorrect information in the device-tree. This will
518 * be (hopefully) fixed for future chips but for now hard
519 * code the values if we are running on one of these
521 pvr = PVR_VER(mfspr(SPRN_PVR));
522 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
523 pvr == PVR_POWER8NVL) {
524 /* size lsize blk sets */
525 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
526 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
527 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
528 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
530 cpu = of_find_node_by_type(NULL, "cpu");
533 * We're assuming *all* of the CPUs have the same
534 * d-cache and i-cache sizes... -Peter
537 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
538 DBG("Argh, can't find dcache properties !\n");
540 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
541 DBG("Argh, can't find icache properties !\n");
544 * Try to find the L2 and L3 if any. Assume they are
545 * unified and use the D-side properties.
547 l2 = of_find_next_cache_node(cpu);
550 parse_cache_info(l2, false, &ppc64_caches.l2);
551 l3 = of_find_next_cache_node(l2);
555 parse_cache_info(l3, false, &ppc64_caches.l3);
560 /* For use by binfmt_elf */
561 dcache_bsize = ppc64_caches.l1d.block_size;
562 icache_bsize = ppc64_caches.l1i.block_size;
564 cur_cpu_spec->dcache_bsize = dcache_bsize;
565 cur_cpu_spec->icache_bsize = icache_bsize;
567 DBG(" <- initialize_cache_info()\n");
570 /* This returns the limit below which memory accesses to the linear
571 * mapping are guarnateed not to cause a TLB or SLB miss. This is
572 * used to allocate interrupt or emergency stacks for which our
573 * exception entry path doesn't deal with being interrupted.
575 static __init u64 safe_stack_limit(void)
577 #ifdef CONFIG_PPC_BOOK3E
578 /* Freescale BookE bolts the entire linear mapping */
579 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
580 return linear_map_top;
581 /* Other BookE, we assume the first GB is bolted */
584 if (early_radix_enabled())
587 /* BookS, the first segment is bolted */
588 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
589 return 1UL << SID_SHIFT_1T;
590 return 1UL << SID_SHIFT;
594 void __init irqstack_early_init(void)
596 u64 limit = safe_stack_limit();
600 * Interrupt stacks must be in the first segment since we
601 * cannot afford to take SLB misses on them. They are not
602 * accessed in realmode.
604 for_each_possible_cpu(i) {
605 softirq_ctx[i] = (struct thread_info *)
606 __va(memblock_alloc_base(THREAD_SIZE,
607 THREAD_SIZE, limit));
608 hardirq_ctx[i] = (struct thread_info *)
609 __va(memblock_alloc_base(THREAD_SIZE,
610 THREAD_SIZE, limit));
614 #ifdef CONFIG_PPC_BOOK3E
615 void __init exc_lvl_early_init(void)
620 for_each_possible_cpu(i) {
621 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
622 critirq_ctx[i] = (struct thread_info *)__va(sp);
623 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
625 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
626 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
627 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
629 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
630 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
631 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
634 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
635 patch_exception(0x040, exc_debug_debug_book3e);
640 * Emergency stacks are used for a range of things, from asynchronous
641 * NMIs (system reset, machine check) to synchronous, process context.
642 * We set preempt_count to zero, even though that isn't necessarily correct. To
643 * get the right value we'd need to copy it from the previous thread_info, but
644 * doing that might fault causing more problems.
645 * TODO: what to do with accounting?
647 static void emerg_stack_init_thread_info(struct thread_info *ti, int cpu)
651 ti->preempt_count = 0;
654 klp_init_thread_info(ti);
658 * Stack space used when we detect a bad kernel stack pointer, and
659 * early in SMP boots before relocation is enabled. Exclusive emergency
660 * stack for machine checks.
662 void __init emergency_stack_init(void)
668 * Emergency stacks must be under 256MB, we cannot afford to take
669 * SLB misses on them. The ABI also requires them to be 128-byte
672 * Since we use these as temporary stacks during secondary CPU
673 * bringup, machine check, system reset, and HMI, we need to get
674 * at them in real mode. This means they must also be within the RMO
677 * The IRQ stacks allocated elsewhere in this file are zeroed and
678 * initialized in kernel/irq.c. These are initialized here in order
679 * to have emergency stacks available as early as possible.
681 limit = min(safe_stack_limit(), ppc64_rma_size);
683 for_each_possible_cpu(i) {
684 struct thread_info *ti;
685 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
686 memset(ti, 0, THREAD_SIZE);
687 emerg_stack_init_thread_info(ti, i);
688 paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
690 #ifdef CONFIG_PPC_BOOK3S_64
691 /* emergency stack for NMI exception handling. */
692 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
693 memset(ti, 0, THREAD_SIZE);
694 emerg_stack_init_thread_info(ti, i);
695 paca[i].nmi_emergency_sp = (void *)ti + THREAD_SIZE;
697 /* emergency stack for machine check exception handling. */
698 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
699 memset(ti, 0, THREAD_SIZE);
700 emerg_stack_init_thread_info(ti, i);
701 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
707 #define PCPU_DYN_SIZE ()
709 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
711 return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align,
712 __pa(MAX_DMA_ADDRESS));
715 static void __init pcpu_fc_free(void *ptr, size_t size)
717 free_bootmem(__pa(ptr), size);
720 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
722 if (early_cpu_to_node(from) == early_cpu_to_node(to))
723 return LOCAL_DISTANCE;
725 return REMOTE_DISTANCE;
728 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
729 EXPORT_SYMBOL(__per_cpu_offset);
731 void __init setup_per_cpu_areas(void)
733 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
740 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
741 * to group units. For larger mappings, use 1M atom which
742 * should be large enough to contain a number of units.
744 if (mmu_linear_psize == MMU_PAGE_4K)
745 atom_size = PAGE_SIZE;
749 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
750 pcpu_fc_alloc, pcpu_fc_free);
752 panic("cannot initialize percpu area (err=%d)", rc);
754 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
755 for_each_possible_cpu(cpu) {
756 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
757 paca[cpu].data_offset = __per_cpu_offset[cpu];
762 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
763 unsigned long memory_block_size_bytes(void)
765 if (ppc_md.memory_block_size)
766 return ppc_md.memory_block_size();
768 return MIN_MEMORY_BLOCK_SIZE;
772 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
773 struct ppc_pci_io ppc_pci_io;
774 EXPORT_SYMBOL(ppc_pci_io);
777 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
778 u64 hw_nmi_get_sample_period(int watchdog_thresh)
780 return ppc_proc_freq * watchdog_thresh;
785 * The perf based hardlockup detector breaks PMU event based branches, so
786 * disable it by default. Book3S has a soft-nmi hardlockup detector based
787 * on the decrementer interrupt, so it does not suffer from this problem.
789 * It is likely to get false positives in VM guests, so disable it there
792 static int __init disable_hardlockup_detector(void)
794 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
795 hardlockup_detector_disable();
797 if (firmware_has_feature(FW_FEATURE_LPAR))
798 hardlockup_detector_disable();
803 early_initcall(disable_hardlockup_detector);
805 #ifdef CONFIG_PPC_BOOK3S_64
806 static enum l1d_flush_type enabled_flush_types;
807 static void *l1d_flush_fallback_area;
808 static bool no_rfi_flush;
811 static int __init handle_no_rfi_flush(char *p)
813 pr_info("rfi-flush: disabled on command line.");
817 early_param("no_rfi_flush", handle_no_rfi_flush);
820 * The RFI flush is not KPTI, but because users will see doco that says to use
821 * nopti we hijack that option here to also disable the RFI flush.
823 static int __init handle_no_pti(char *p)
825 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
826 handle_no_rfi_flush(NULL);
829 early_param("nopti", handle_no_pti);
831 static void do_nothing(void *unused)
834 * We don't need to do the flush explicitly, just enter+exit kernel is
835 * sufficient, the RFI exit handlers will do the right thing.
839 void rfi_flush_enable(bool enable)
841 if (rfi_flush == enable)
845 do_rfi_flush_fixups(enabled_flush_types);
846 on_each_cpu(do_nothing, NULL, 1);
848 do_rfi_flush_fixups(L1D_FLUSH_NONE);
853 static void init_fallback_flush(void)
858 l1d_size = ppc64_caches.l1d.size;
859 limit = min(safe_stack_limit(), ppc64_rma_size);
862 * Align to L1d size, and size it at 2x L1d size, to catch possible
863 * hardware prefetch runoff. We don't have a recipe for load patterns to
864 * reliably avoid the prefetcher.
866 l1d_flush_fallback_area = __va(memblock_alloc_base(l1d_size * 2, l1d_size, limit));
867 memset(l1d_flush_fallback_area, 0, l1d_size * 2);
869 for_each_possible_cpu(cpu) {
871 * The fallback flush is currently coded for 8-way
872 * associativity. Different associativity is possible, but it
873 * will be treated as 8-way and may not evict the lines as
876 * 128 byte lines are mandatory.
878 u64 c = l1d_size / 8;
880 paca[cpu].rfi_flush_fallback_area = l1d_flush_fallback_area;
881 paca[cpu].l1d_flush_congruence = c;
882 paca[cpu].l1d_flush_sets = c / 128;
886 void __init setup_rfi_flush(enum l1d_flush_type types, bool enable)
888 if (types & L1D_FLUSH_FALLBACK) {
889 pr_info("rfi-flush: Using fallback displacement flush\n");
890 init_fallback_flush();
893 if (types & L1D_FLUSH_ORI)
894 pr_info("rfi-flush: Using ori type flush\n");
896 if (types & L1D_FLUSH_MTTRIG)
897 pr_info("rfi-flush: Using mttrig type flush\n");
899 enabled_flush_types = types;
902 rfi_flush_enable(enable);
904 #endif /* CONFIG_PPC_BOOK3S_64 */