arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/debug.h>
  20 #include <linux/sched/task.h>
  21 #include <linux/sched/task_stack.h>
  22 #include <linux/kernel.h>
  23 #include <linux/mm.h>
  24 #include <linux/smp.h>
  25 #include <linux/stddef.h>
  26 #include <linux/unistd.h>
  27 #include <linux/ptrace.h>
  28 #include <linux/slab.h>
  29 #include <linux/user.h>
  30 #include <linux/elf.h>
  31 #include <linux/prctl.h>
  32 #include <linux/init_task.h>
  33 #include <linux/export.h>
  34 #include <linux/kallsyms.h>
  35 #include <linux/mqueue.h>
  36 #include <linux/hardirq.h>
  37 #include <linux/utsname.h>
  38 #include <linux/ftrace.h>
  39 #include <linux/kernel_stat.h>
  40 #include <linux/personality.h>
  41 #include <linux/random.h>
  42 #include <linux/hw_breakpoint.h>
  43 #include <linux/uaccess.h>
  44 #include <linux/elf-randomize.h>
  45 #include <linux/pkeys.h>
  46
  47 #include <asm/pgtable.h>
  48 #include <asm/io.h>
  49 #include <asm/processor.h>
  50 #include <asm/mmu.h>
  51 #include <asm/prom.h>
  52 #include <asm/machdep.h>
  53 #include <asm/time.h>
  54 #include <asm/runlatch.h>
  55 #include <asm/syscalls.h>
  56 #include <asm/switch_to.h>
  57 #include <asm/tm.h>
  58 #include <asm/debug.h>
  59 #ifdef CONFIG_PPC64
  60 #include <asm/firmware.h>
  61 #include <asm/hw_irq.h>
  62 #endif
  63 #include <asm/code-patching.h>
  64 #include <asm/exec.h>
  65 #include <asm/livepatch.h>
  66 #include <asm/cpu_has_feature.h>
  67 #include <asm/asm-prototypes.h>
  68
  69 #include <linux/kprobes.h>
  70 #include <linux/kdebug.h>
  71
  72 /* Transactional Memory debug */
  73 #ifdef TM_DEBUG_SW
  74 #define TM_DEBUG(x...) printk(KERN_INFO x)
  75 #else
  76 #define TM_DEBUG(x...) do { } while(0)
  77 #endif
  78
  79 extern unsigned long _get_SP(void);
  80
  81 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  82 /*
  83  * Are we running in "Suspend disabled" mode? If so we have to block any
  84  * sigreturn that would get us into suspended state, and we also warn in some
  85  * other paths that we should never reach with suspend disabled.
  86  */
  87 bool tm_suspend_disabled __ro_after_init = false;
  88
  89 static void check_if_tm_restore_required(struct task_struct *tsk)
  90 {
  91         /*
  92          * If we are saving the current thread's registers, and the
  93          * thread is in a transactional state, set the TIF_RESTORE_TM
  94          * bit so that we know to restore the registers before
  95          * returning to userspace.
  96          */
  97         if (tsk == current && tsk->thread.regs &&
  98             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  99             !test_thread_flag(TIF_RESTORE_TM)) {
 100                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
 101                 set_thread_flag(TIF_RESTORE_TM);
 102         }
 103 }
 104
 105 static inline bool msr_tm_active(unsigned long msr)
 106 {
 107         return MSR_TM_ACTIVE(msr);
 108 }
 109
 110 static bool tm_active_with_fp(struct task_struct *tsk)
 111 {
 112         return msr_tm_active(tsk->thread.regs->msr) &&
 113                 (tsk->thread.ckpt_regs.msr & MSR_FP);
 114 }
 115
 116 static bool tm_active_with_altivec(struct task_struct *tsk)
 117 {
 118         return msr_tm_active(tsk->thread.regs->msr) &&
 119                 (tsk->thread.ckpt_regs.msr & MSR_VEC);
 120 }
 121 #else
 122 static inline bool msr_tm_active(unsigned long msr) { return false; }
 123 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 124 static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; }
 125 static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; }
 126 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 127
 128 bool strict_msr_control;
 129 EXPORT_SYMBOL(strict_msr_control);
 130
 131 static int __init enable_strict_msr_control(char *str)
 132 {
 133         strict_msr_control = true;
 134         pr_info("Enabling strict facility control\n");
 135
 136         return 0;
 137 }
 138 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 139
 140 unsigned long msr_check_and_set(unsigned long bits)
 141 {
 142         unsigned long oldmsr = mfmsr();
 143         unsigned long newmsr;
 144
 145         newmsr = oldmsr | bits;
 146
 147 #ifdef CONFIG_VSX
 148         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 149                 newmsr |= MSR_VSX;
 150 #endif
 151
 152         if (oldmsr != newmsr)
 153                 mtmsr_isync(newmsr);
 154
 155         return newmsr;
 156 }
 157 EXPORT_SYMBOL_GPL(msr_check_and_set);
 158
 159 void __msr_check_and_clear(unsigned long bits)
 160 {
 161         unsigned long oldmsr = mfmsr();
 162         unsigned long newmsr;
 163
 164         newmsr = oldmsr & ~bits;
 165
 166 #ifdef CONFIG_VSX
 167         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 168                 newmsr &= ~MSR_VSX;
 169 #endif
 170
 171         if (oldmsr != newmsr)
 172                 mtmsr_isync(newmsr);
 173 }
 174 EXPORT_SYMBOL(__msr_check_and_clear);
 175
 176 #ifdef CONFIG_PPC_FPU
 177 static void __giveup_fpu(struct task_struct *tsk)
 178 {
 179         unsigned long msr;
 180
 181         save_fpu(tsk);
 182         msr = tsk->thread.regs->msr;
 183         msr &= ~MSR_FP;
 184 #ifdef CONFIG_VSX
 185         if (cpu_has_feature(CPU_FTR_VSX))
 186                 msr &= ~MSR_VSX;
 187 #endif
 188         tsk->thread.regs->msr = msr;
 189 }
 190
 191 void giveup_fpu(struct task_struct *tsk)
 192 {
 193         check_if_tm_restore_required(tsk);
 194
 195         msr_check_and_set(MSR_FP);
 196         __giveup_fpu(tsk);
 197         msr_check_and_clear(MSR_FP);
 198 }
 199 EXPORT_SYMBOL(giveup_fpu);
 200
 201 /*
 202  * Make sure the floating-point register state in the
 203  * the thread_struct is up to date for task tsk.
 204  */
 205 void flush_fp_to_thread(struct task_struct *tsk)
 206 {
 207         if (tsk->thread.regs) {
 208                 /*
 209                  * We need to disable preemption here because if we didn't,
 210                  * another process could get scheduled after the regs->msr
 211                  * test but before we have finished saving the FP registers
 212                  * to the thread_struct.  That process could take over the
 213                  * FPU, and then when we get scheduled again we would store
 214                  * bogus values for the remaining FP registers.
 215                  */
 216                 preempt_disable();
 217                 if (tsk->thread.regs->msr & MSR_FP) {
 218                         /*
 219                          * This should only ever be called for current or
 220                          * for a stopped child process.  Since we save away
 221                          * the FP register state on context switch,
 222                          * there is something wrong if a stopped child appears
 223                          * to still have its FP state in the CPU registers.
 224                          */
 225                         BUG_ON(tsk != current);
 226                         giveup_fpu(tsk);
 227                 }
 228                 preempt_enable();
 229         }
 230 }
 231 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 232
 233 void enable_kernel_fp(void)
 234 {
 235         unsigned long cpumsr;
 236
 237         WARN_ON(preemptible());
 238
 239         cpumsr = msr_check_and_set(MSR_FP);
 240
 241         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 242                 check_if_tm_restore_required(current);
 243                 /*
 244                  * If a thread has already been reclaimed then the
 245                  * checkpointed registers are on the CPU but have definitely
 246                  * been saved by the reclaim code. Don't need to and *cannot*
 247                  * giveup as this would save  to the 'live' structure not the
 248                  * checkpointed structure.
 249                  */
 250                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 251                         return;
 252                 __giveup_fpu(current);
 253         }
 254 }
 255 EXPORT_SYMBOL(enable_kernel_fp);
 256
 257 static int restore_fp(struct task_struct *tsk)
 258 {
 259         if (tsk->thread.load_fp || tm_active_with_fp(tsk)) {
 260                 load_fp_state(&current->thread.fp_state);
 261                 current->thread.load_fp++;
 262                 return 1;
 263         }
 264         return 0;
 265 }
 266 #else
 267 static int restore_fp(struct task_struct *tsk) { return 0; }
 268 #endif /* CONFIG_PPC_FPU */
 269
 270 #ifdef CONFIG_ALTIVEC
 271 #define loadvec(thr) ((thr).load_vec)
 272
 273 static void __giveup_altivec(struct task_struct *tsk)
 274 {
 275         unsigned long msr;
 276
 277         save_altivec(tsk);
 278         msr = tsk->thread.regs->msr;
 279         msr &= ~MSR_VEC;
 280 #ifdef CONFIG_VSX
 281         if (cpu_has_feature(CPU_FTR_VSX))
 282                 msr &= ~MSR_VSX;
 283 #endif
 284         tsk->thread.regs->msr = msr;
 285 }
 286
 287 void giveup_altivec(struct task_struct *tsk)
 288 {
 289         check_if_tm_restore_required(tsk);
 290
 291         msr_check_and_set(MSR_VEC);
 292         __giveup_altivec(tsk);
 293         msr_check_and_clear(MSR_VEC);
 294 }
 295 EXPORT_SYMBOL(giveup_altivec);
 296
 297 void enable_kernel_altivec(void)
 298 {
 299         unsigned long cpumsr;
 300
 301         WARN_ON(preemptible());
 302
 303         cpumsr = msr_check_and_set(MSR_VEC);
 304
 305         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 306                 check_if_tm_restore_required(current);
 307                 /*
 308                  * If a thread has already been reclaimed then the
 309                  * checkpointed registers are on the CPU but have definitely
 310                  * been saved by the reclaim code. Don't need to and *cannot*
 311                  * giveup as this would save  to the 'live' structure not the
 312                  * checkpointed structure.
 313                  */
 314                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 315                         return;
 316                 __giveup_altivec(current);
 317         }
 318 }
 319 EXPORT_SYMBOL(enable_kernel_altivec);
 320
 321 /*
 322  * Make sure the VMX/Altivec register state in the
 323  * the thread_struct is up to date for task tsk.
 324  */
 325 void flush_altivec_to_thread(struct task_struct *tsk)
 326 {
 327         if (tsk->thread.regs) {
 328                 preempt_disable();
 329                 if (tsk->thread.regs->msr & MSR_VEC) {
 330                         BUG_ON(tsk != current);
 331                         giveup_altivec(tsk);
 332                 }
 333                 preempt_enable();
 334         }
 335 }
 336 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 337
 338 static int restore_altivec(struct task_struct *tsk)
 339 {
 340         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 341                 (tsk->thread.load_vec || tm_active_with_altivec(tsk))) {
 342                 load_vr_state(&tsk->thread.vr_state);
 343                 tsk->thread.used_vr = 1;
 344                 tsk->thread.load_vec++;
 345
 346                 return 1;
 347         }
 348         return 0;
 349 }
 350 #else
 351 #define loadvec(thr) 0
 352 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 353 #endif /* CONFIG_ALTIVEC */
 354
 355 #ifdef CONFIG_VSX
 356 static void __giveup_vsx(struct task_struct *tsk)
 357 {
 358         unsigned long msr = tsk->thread.regs->msr;
 359
 360         /*
 361          * We should never be ssetting MSR_VSX without also setting
 362          * MSR_FP and MSR_VEC
 363          */
 364         WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
 365
 366         /* __giveup_fpu will clear MSR_VSX */
 367         if (msr & MSR_FP)
 368                 __giveup_fpu(tsk);
 369         if (msr & MSR_VEC)
 370                 __giveup_altivec(tsk);
 371 }
 372
 373 static void giveup_vsx(struct task_struct *tsk)
 374 {
 375         check_if_tm_restore_required(tsk);
 376
 377         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 378         __giveup_vsx(tsk);
 379         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 380 }
 381
 382 void enable_kernel_vsx(void)
 383 {
 384         unsigned long cpumsr;
 385
 386         WARN_ON(preemptible());
 387
 388         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 389
 390         if (current->thread.regs &&
 391             (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
 392                 check_if_tm_restore_required(current);
 393                 /*
 394                  * If a thread has already been reclaimed then the
 395                  * checkpointed registers are on the CPU but have definitely
 396                  * been saved by the reclaim code. Don't need to and *cannot*
 397                  * giveup as this would save  to the 'live' structure not the
 398                  * checkpointed structure.
 399                  */
 400                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 401                         return;
 402                 __giveup_vsx(current);
 403         }
 404 }
 405 EXPORT_SYMBOL(enable_kernel_vsx);
 406
 407 void flush_vsx_to_thread(struct task_struct *tsk)
 408 {
 409         if (tsk->thread.regs) {
 410                 preempt_disable();
 411                 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
 412                         BUG_ON(tsk != current);
 413                         giveup_vsx(tsk);
 414                 }
 415                 preempt_enable();
 416         }
 417 }
 418 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 419
 420 static int restore_vsx(struct task_struct *tsk)
 421 {
 422         if (cpu_has_feature(CPU_FTR_VSX)) {
 423                 tsk->thread.used_vsr = 1;
 424                 return 1;
 425         }
 426
 427         return 0;
 428 }
 429 #else
 430 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 431 #endif /* CONFIG_VSX */
 432
 433 #ifdef CONFIG_SPE
 434 void giveup_spe(struct task_struct *tsk)
 435 {
 436         check_if_tm_restore_required(tsk);
 437
 438         msr_check_and_set(MSR_SPE);
 439         __giveup_spe(tsk);
 440         msr_check_and_clear(MSR_SPE);
 441 }
 442 EXPORT_SYMBOL(giveup_spe);
 443
 444 void enable_kernel_spe(void)
 445 {
 446         WARN_ON(preemptible());
 447
 448         msr_check_and_set(MSR_SPE);
 449
 450         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 451                 check_if_tm_restore_required(current);
 452                 __giveup_spe(current);
 453         }
 454 }
 455 EXPORT_SYMBOL(enable_kernel_spe);
 456
 457 void flush_spe_to_thread(struct task_struct *tsk)
 458 {
 459         if (tsk->thread.regs) {
 460                 preempt_disable();
 461                 if (tsk->thread.regs->msr & MSR_SPE) {
 462                         BUG_ON(tsk != current);
 463                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 464                         giveup_spe(tsk);
 465                 }
 466                 preempt_enable();
 467         }
 468 }
 469 #endif /* CONFIG_SPE */
 470
 471 static unsigned long msr_all_available;
 472
 473 static int __init init_msr_all_available(void)
 474 {
 475 #ifdef CONFIG_PPC_FPU
 476         msr_all_available |= MSR_FP;
 477 #endif
 478 #ifdef CONFIG_ALTIVEC
 479         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 480                 msr_all_available |= MSR_VEC;
 481 #endif
 482 #ifdef CONFIG_VSX
 483         if (cpu_has_feature(CPU_FTR_VSX))
 484                 msr_all_available |= MSR_VSX;
 485 #endif
 486 #ifdef CONFIG_SPE
 487         if (cpu_has_feature(CPU_FTR_SPE))
 488                 msr_all_available |= MSR_SPE;
 489 #endif
 490
 491         return 0;
 492 }
 493 early_initcall(init_msr_all_available);
 494
 495 void giveup_all(struct task_struct *tsk)
 496 {
 497         unsigned long usermsr;
 498
 499         if (!tsk->thread.regs)
 500                 return;
 501
 502         usermsr = tsk->thread.regs->msr;
 503
 504         if ((usermsr & msr_all_available) == 0)
 505                 return;
 506
 507         msr_check_and_set(msr_all_available);
 508         check_if_tm_restore_required(tsk);
 509
 510         WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
 511
 512 #ifdef CONFIG_PPC_FPU
 513         if (usermsr & MSR_FP)
 514                 __giveup_fpu(tsk);
 515 #endif
 516 #ifdef CONFIG_ALTIVEC
 517         if (usermsr & MSR_VEC)
 518                 __giveup_altivec(tsk);
 519 #endif
 520 #ifdef CONFIG_SPE
 521         if (usermsr & MSR_SPE)
 522                 __giveup_spe(tsk);
 523 #endif
 524
 525         msr_check_and_clear(msr_all_available);
 526 }
 527 EXPORT_SYMBOL(giveup_all);
 528
 529 void restore_math(struct pt_regs *regs)
 530 {
 531         unsigned long msr;
 532
 533         if (!msr_tm_active(regs->msr) &&
 534                 !current->thread.load_fp && !loadvec(current->thread))
 535                 return;
 536
 537         msr = regs->msr;
 538         msr_check_and_set(msr_all_available);
 539
 540         /*
 541          * Only reload if the bit is not set in the user MSR, the bit BEING set
 542          * indicates that the registers are hot
 543          */
 544         if ((!(msr & MSR_FP)) && restore_fp(current))
 545                 msr |= MSR_FP | current->thread.fpexc_mode;
 546
 547         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 548                 msr |= MSR_VEC;
 549
 550         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 551                         restore_vsx(current)) {
 552                 msr |= MSR_VSX;
 553         }
 554
 555         msr_check_and_clear(msr_all_available);
 556
 557         regs->msr = msr;
 558 }
 559
 560 static void save_all(struct task_struct *tsk)
 561 {
 562         unsigned long usermsr;
 563
 564         if (!tsk->thread.regs)
 565                 return;
 566
 567         usermsr = tsk->thread.regs->msr;
 568
 569         if ((usermsr & msr_all_available) == 0)
 570                 return;
 571
 572         msr_check_and_set(msr_all_available);
 573
 574         WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
 575
 576         if (usermsr & MSR_FP)
 577                 save_fpu(tsk);
 578
 579         if (usermsr & MSR_VEC)
 580                 save_altivec(tsk);
 581
 582         if (usermsr & MSR_SPE)
 583                 __giveup_spe(tsk);
 584
 585         msr_check_and_clear(msr_all_available);
 586         thread_pkey_regs_save(&tsk->thread);
 587 }
 588
 589 void flush_all_to_thread(struct task_struct *tsk)
 590 {
 591         if (tsk->thread.regs) {
 592                 preempt_disable();
 593                 BUG_ON(tsk != current);
 594                 save_all(tsk);
 595
 596 #ifdef CONFIG_SPE
 597                 if (tsk->thread.regs->msr & MSR_SPE)
 598                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 599 #endif
 600
 601                 preempt_enable();
 602         }
 603 }
 604 EXPORT_SYMBOL(flush_all_to_thread);
 605
 606 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 607 void do_send_trap(struct pt_regs *regs, unsigned long address,
 608                   unsigned long error_code, int breakpt)
 609 {
 610         current->thread.trap_nr = TRAP_HWBKPT;
 611         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 612                         11, SIGSEGV) == NOTIFY_STOP)
 613                 return;
 614
 615         /* Deliver the signal to userspace */
 616         force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
 617                                     (void __user *)address);
 618 }
 619 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 620 void do_break (struct pt_regs *regs, unsigned long address,
 621                     unsigned long error_code)
 622 {
 623         current->thread.trap_nr = TRAP_HWBKPT;
 624         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 625                         11, SIGSEGV) == NOTIFY_STOP)
 626                 return;
 627
 628         if (debugger_break_match(regs))
 629                 return;
 630
 631         /* Clear the breakpoint */
 632         hw_breakpoint_disable();
 633
 634         /* Deliver the signal to userspace */
 635         force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address, current);
 636 }
 637 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 638
 639 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 640
 641 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 642 /*
 643  * Set the debug registers back to their default "safe" values.
 644  */
 645 static void set_debug_reg_defaults(struct thread_struct *thread)
 646 {
 647         thread->debug.iac1 = thread->debug.iac2 = 0;
 648 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 649         thread->debug.iac3 = thread->debug.iac4 = 0;
 650 #endif
 651         thread->debug.dac1 = thread->debug.dac2 = 0;
 652 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 653         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 654 #endif
 655         thread->debug.dbcr0 = 0;
 656 #ifdef CONFIG_BOOKE
 657         /*
 658          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 659          */
 660         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 661                         DBCR1_IAC3US | DBCR1_IAC4US;
 662         /*
 663          * Force Data Address Compare User/Supervisor bits to be User-only
 664          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 665          */
 666         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 667 #else
 668         thread->debug.dbcr1 = 0;
 669 #endif
 670 }
 671
 672 static void prime_debug_regs(struct debug_reg *debug)
 673 {
 674         /*
 675          * We could have inherited MSR_DE from userspace, since
 676          * it doesn't get cleared on exception entry.  Make sure
 677          * MSR_DE is clear before we enable any debug events.
 678          */
 679         mtmsr(mfmsr() & ~MSR_DE);
 680
 681         mtspr(SPRN_IAC1, debug->iac1);
 682         mtspr(SPRN_IAC2, debug->iac2);
 683 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 684         mtspr(SPRN_IAC3, debug->iac3);
 685         mtspr(SPRN_IAC4, debug->iac4);
 686 #endif
 687         mtspr(SPRN_DAC1, debug->dac1);
 688         mtspr(SPRN_DAC2, debug->dac2);
 689 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 690         mtspr(SPRN_DVC1, debug->dvc1);
 691         mtspr(SPRN_DVC2, debug->dvc2);
 692 #endif
 693         mtspr(SPRN_DBCR0, debug->dbcr0);
 694         mtspr(SPRN_DBCR1, debug->dbcr1);
 695 #ifdef CONFIG_BOOKE
 696         mtspr(SPRN_DBCR2, debug->dbcr2);
 697 #endif
 698 }
 699 /*
 700  * Unless neither the old or new thread are making use of the
 701  * debug registers, set the debug registers from the values
 702  * stored in the new thread.
 703  */
 704 void switch_booke_debug_regs(struct debug_reg *new_debug)
 705 {
 706         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 707                 || (new_debug->dbcr0 & DBCR0_IDM))
 708                         prime_debug_regs(new_debug);
 709 }
 710 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 711 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 712 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 713 static void set_breakpoint(struct arch_hw_breakpoint *brk)
 714 {
 715         preempt_disable();
 716         __set_breakpoint(brk);
 717         preempt_enable();
 718 }
 719
 720 static void set_debug_reg_defaults(struct thread_struct *thread)
 721 {
 722         thread->hw_brk.address = 0;
 723         thread->hw_brk.type = 0;
 724         if (ppc_breakpoint_available())
 725                 set_breakpoint(&thread->hw_brk);
 726 }
 727 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 728 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 729
 730 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 731 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 732 {
 733         mtspr(SPRN_DAC1, dabr);
 734 #ifdef CONFIG_PPC_47x
 735         isync();
 736 #endif
 737         return 0;
 738 }
 739 #elif defined(CONFIG_PPC_BOOK3S)
 740 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 741 {
 742         mtspr(SPRN_DABR, dabr);
 743         if (cpu_has_feature(CPU_FTR_DABRX))
 744                 mtspr(SPRN_DABRX, dabrx);
 745         return 0;
 746 }
 747 #elif defined(CONFIG_PPC_8xx)
 748 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 749 {
 750         unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
 751         unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
 752         unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
 753
 754         if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
 755                 lctrl1 |= 0xa0000;
 756         else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
 757                 lctrl1 |= 0xf0000;
 758         else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
 759                 lctrl2 = 0;
 760
 761         mtspr(SPRN_LCTRL2, 0);
 762         mtspr(SPRN_CMPE, addr);
 763         mtspr(SPRN_CMPF, addr + 4);
 764         mtspr(SPRN_LCTRL1, lctrl1);
 765         mtspr(SPRN_LCTRL2, lctrl2);
 766
 767         return 0;
 768 }
 769 #else
 770 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 771 {
 772         return -EINVAL;
 773 }
 774 #endif
 775
 776 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 777 {
 778         unsigned long dabr, dabrx;
 779
 780         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 781         dabrx = ((brk->type >> 3) & 0x7);
 782
 783         if (ppc_md.set_dabr)
 784                 return ppc_md.set_dabr(dabr, dabrx);
 785
 786         return __set_dabr(dabr, dabrx);
 787 }
 788
 789 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 790 {
 791         unsigned long dawr, dawrx, mrd;
 792
 793         dawr = brk->address;
 794
 795         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 796                                    << (63 - 58); //* read/write bits */
 797         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 798                                    << (63 - 59); //* translate */
 799         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 800                                    >> 3; //* PRIM bits */
 801         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 802            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 803            0b111111=64DW.
 804            brk->len is in bytes.
 805            This aligns up to double word size, shifts and does the bias.
 806         */
 807         mrd = ((brk->len + 7) >> 3) - 1;
 808         dawrx |= (mrd & 0x3f) << (63 - 53);
 809
 810         if (ppc_md.set_dawr)
 811                 return ppc_md.set_dawr(dawr, dawrx);
 812         mtspr(SPRN_DAWR, dawr);
 813         mtspr(SPRN_DAWRX, dawrx);
 814         return 0;
 815 }
 816
 817 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 818 {
 819         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 820
 821         if (cpu_has_feature(CPU_FTR_DAWR))
 822                 // Power8 or later
 823                 set_dawr(brk);
 824         else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
 825                 // Power7 or earlier
 826                 set_dabr(brk);
 827         else
 828                 // Shouldn't happen due to higher level checks
 829                 WARN_ON_ONCE(1);
 830 }
 831
 832 /* Check if we have DAWR or DABR hardware */
 833 bool ppc_breakpoint_available(void)
 834 {
 835         if (cpu_has_feature(CPU_FTR_DAWR))
 836                 return true; /* POWER8 DAWR */
 837         if (cpu_has_feature(CPU_FTR_ARCH_207S))
 838                 return false; /* POWER9 with DAWR disabled */
 839         /* DABR: Everything but POWER8 and POWER9 */
 840         return true;
 841 }
 842 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
 843
 844 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 845                               struct arch_hw_breakpoint *b)
 846 {
 847         if (a->address != b->address)
 848                 return false;
 849         if (a->type != b->type)
 850                 return false;
 851         if (a->len != b->len)
 852                 return false;
 853         return true;
 854 }
 855
 856 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 857
 858 static inline bool tm_enabled(struct task_struct *tsk)
 859 {
 860         return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
 861 }
 862
 863 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
 864 {
 865         /*
 866          * Use the current MSR TM suspended bit to track if we have
 867          * checkpointed state outstanding.
 868          * On signal delivery, we'd normally reclaim the checkpointed
 869          * state to obtain stack pointer (see:get_tm_stackpointer()).
 870          * This will then directly return to userspace without going
 871          * through __switch_to(). However, if the stack frame is bad,
 872          * we need to exit this thread which calls __switch_to() which
 873          * will again attempt to reclaim the already saved tm state.
 874          * Hence we need to check that we've not already reclaimed
 875          * this state.
 876          * We do this using the current MSR, rather tracking it in
 877          * some specific thread_struct bit, as it has the additional
 878          * benefit of checking for a potential TM bad thing exception.
 879          */
 880         if (!MSR_TM_SUSPENDED(mfmsr()))
 881                 return;
 882
 883         giveup_all(container_of(thr, struct task_struct, thread));
 884
 885         tm_reclaim(thr, cause);
 886
 887         /*
 888          * If we are in a transaction and FP is off then we can't have
 889          * used FP inside that transaction. Hence the checkpointed
 890          * state is the same as the live state. We need to copy the
 891          * live state to the checkpointed state so that when the
 892          * transaction is restored, the checkpointed state is correct
 893          * and the aborted transaction sees the correct state. We use
 894          * ckpt_regs.msr here as that's what tm_reclaim will use to
 895          * determine if it's going to write the checkpointed state or
 896          * not. So either this will write the checkpointed registers,
 897          * or reclaim will. Similarly for VMX.
 898          */
 899         if ((thr->ckpt_regs.msr & MSR_FP) == 0)
 900                 memcpy(&thr->ckfp_state, &thr->fp_state,
 901                        sizeof(struct thread_fp_state));
 902         if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
 903                 memcpy(&thr->ckvr_state, &thr->vr_state,
 904                        sizeof(struct thread_vr_state));
 905 }
 906
 907 void tm_reclaim_current(uint8_t cause)
 908 {
 909         tm_enable();
 910         tm_reclaim_thread(&current->thread, cause);
 911 }
 912
 913 static inline void tm_reclaim_task(struct task_struct *tsk)
 914 {
 915         /* We have to work out if we're switching from/to a task that's in the
 916          * middle of a transaction.
 917          *
 918          * In switching we need to maintain a 2nd register state as
 919          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 920          * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
 921          * ckvr_state
 922          *
 923          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 924          */
 925         struct thread_struct *thr = &tsk->thread;
 926
 927         if (!thr->regs)
 928                 return;
 929
 930         if (!MSR_TM_ACTIVE(thr->regs->msr))
 931                 goto out_and_saveregs;
 932
 933         WARN_ON(tm_suspend_disabled);
 934
 935         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 936                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 937                  tsk->pid, thr->regs->nip,
 938                  thr->regs->ccr, thr->regs->msr,
 939                  thr->regs->trap);
 940
 941         tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
 942
 943         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 944                  tsk->pid);
 945
 946 out_and_saveregs:
 947         /* Always save the regs here, even if a transaction's not active.
 948          * This context-switches a thread's TM info SPRs.  We do it here to
 949          * be consistent with the restore path (in recheckpoint) which
 950          * cannot happen later in _switch().
 951          */
 952         tm_save_sprs(thr);
 953 }
 954
 955 extern void __tm_recheckpoint(struct thread_struct *thread);
 956
 957 void tm_recheckpoint(struct thread_struct *thread)
 958 {
 959         unsigned long flags;
 960
 961         if (!(thread->regs->msr & MSR_TM))
 962                 return;
 963
 964         /* We really can't be interrupted here as the TEXASR registers can't
 965          * change and later in the trecheckpoint code, we have a userspace R1.
 966          * So let's hard disable over this region.
 967          */
 968         local_irq_save(flags);
 969         hard_irq_disable();
 970
 971         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 972          * before the trecheckpoint and no explosion occurs.
 973          */
 974         tm_restore_sprs(thread);
 975
 976         __tm_recheckpoint(thread);
 977
 978         local_irq_restore(flags);
 979 }
 980
 981 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 982 {
 983         if (!cpu_has_feature(CPU_FTR_TM))
 984                 return;
 985
 986         /* Recheckpoint the registers of the thread we're about to switch to.
 987          *
 988          * If the task was using FP, we non-lazily reload both the original and
 989          * the speculative FP register states.  This is because the kernel
 990          * doesn't see if/when a TM rollback occurs, so if we take an FP
 991          * unavailable later, we are unable to determine which set of FP regs
 992          * need to be restored.
 993          */
 994         if (!tm_enabled(new))
 995                 return;
 996
 997         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 998                 tm_restore_sprs(&new->thread);
 999                 return;
1000         }
1001         /* Recheckpoint to restore original checkpointed register state. */
1002         TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1003                  new->pid, new->thread.regs->msr);
1004
1005         tm_recheckpoint(&new->thread);
1006
1007         /*
1008          * The checkpointed state has been restored but the live state has
1009          * not, ensure all the math functionality is turned off to trigger
1010          * restore_math() to reload.
1011          */
1012         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1013
1014         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1015                  "(kernel msr 0x%lx)\n",
1016                  new->pid, mfmsr());
1017 }
1018
1019 static inline void __switch_to_tm(struct task_struct *prev,
1020                 struct task_struct *new)
1021 {
1022         if (cpu_has_feature(CPU_FTR_TM)) {
1023                 if (tm_enabled(prev) || tm_enabled(new))
1024                         tm_enable();
1025
1026                 if (tm_enabled(prev)) {
1027                         prev->thread.load_tm++;
1028                         tm_reclaim_task(prev);
1029                         if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1030                                 prev->thread.regs->msr &= ~MSR_TM;
1031                 }
1032
1033                 tm_recheckpoint_new_task(new);
1034         }
1035 }
1036
1037 /*
1038  * This is called if we are on the way out to userspace and the
1039  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1040  * FP and/or vector state and does so if necessary.
1041  * If userspace is inside a transaction (whether active or
1042  * suspended) and FP/VMX/VSX instructions have ever been enabled
1043  * inside that transaction, then we have to keep them enabled
1044  * and keep the FP/VMX/VSX state loaded while ever the transaction
1045  * continues.  The reason is that if we didn't, and subsequently
1046  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1047  * we don't know whether it's the same transaction, and thus we
1048  * don't know which of the checkpointed state and the transactional
1049  * state to use.
1050  */
1051 void restore_tm_state(struct pt_regs *regs)
1052 {
1053         unsigned long msr_diff;
1054
1055         /*
1056          * This is the only moment we should clear TIF_RESTORE_TM as
1057          * it is here that ckpt_regs.msr and pt_regs.msr become the same
1058          * again, anything else could lead to an incorrect ckpt_msr being
1059          * saved and therefore incorrect signal contexts.
1060          */
1061         clear_thread_flag(TIF_RESTORE_TM);
1062         if (!MSR_TM_ACTIVE(regs->msr))
1063                 return;
1064
1065         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1066         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1067
1068         /* Ensure that restore_math() will restore */
1069         if (msr_diff & MSR_FP)
1070                 current->thread.load_fp = 1;
1071 #ifdef CONFIG_ALTIVEC
1072         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1073                 current->thread.load_vec = 1;
1074 #endif
1075         restore_math(regs);
1076
1077         regs->msr |= msr_diff;
1078 }
1079
1080 #else
1081 #define tm_recheckpoint_new_task(new)
1082 #define __switch_to_tm(prev, new)
1083 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1084
1085 static inline void save_sprs(struct thread_struct *t)
1086 {
1087 #ifdef CONFIG_ALTIVEC
1088         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1089                 t->vrsave = mfspr(SPRN_VRSAVE);
1090 #endif
1091 #ifdef CONFIG_PPC_BOOK3S_64
1092         if (cpu_has_feature(CPU_FTR_DSCR))
1093                 t->dscr = mfspr(SPRN_DSCR);
1094
1095         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1096                 t->bescr = mfspr(SPRN_BESCR);
1097                 t->ebbhr = mfspr(SPRN_EBBHR);
1098                 t->ebbrr = mfspr(SPRN_EBBRR);
1099
1100                 t->fscr = mfspr(SPRN_FSCR);
1101
1102                 /*
1103                  * Note that the TAR is not available for use in the kernel.
1104                  * (To provide this, the TAR should be backed up/restored on
1105                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1106                  * this should be in pt_regs anyway (for debug).)
1107                  */
1108                 t->tar = mfspr(SPRN_TAR);
1109         }
1110 #endif
1111
1112         thread_pkey_regs_save(t);
1113 }
1114
1115 static inline void restore_sprs(struct thread_struct *old_thread,
1116                                 struct thread_struct *new_thread)
1117 {
1118 #ifdef CONFIG_ALTIVEC
1119         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1120             old_thread->vrsave != new_thread->vrsave)
1121                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1122 #endif
1123 #ifdef CONFIG_PPC_BOOK3S_64
1124         if (cpu_has_feature(CPU_FTR_DSCR)) {
1125                 u64 dscr = get_paca()->dscr_default;
1126                 if (new_thread->dscr_inherit)
1127                         dscr = new_thread->dscr;
1128
1129                 if (old_thread->dscr != dscr)
1130                         mtspr(SPRN_DSCR, dscr);
1131         }
1132
1133         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1134                 if (old_thread->bescr != new_thread->bescr)
1135                         mtspr(SPRN_BESCR, new_thread->bescr);
1136                 if (old_thread->ebbhr != new_thread->ebbhr)
1137                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1138                 if (old_thread->ebbrr != new_thread->ebbrr)
1139                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1140
1141                 if (old_thread->fscr != new_thread->fscr)
1142                         mtspr(SPRN_FSCR, new_thread->fscr);
1143
1144                 if (old_thread->tar != new_thread->tar)
1145                         mtspr(SPRN_TAR, new_thread->tar);
1146         }
1147
1148         if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1149             old_thread->tidr != new_thread->tidr)
1150                 mtspr(SPRN_TIDR, new_thread->tidr);
1151 #endif
1152
1153         thread_pkey_regs_restore(new_thread, old_thread);
1154 }
1155
1156 #ifdef CONFIG_PPC_BOOK3S_64
1157 #define CP_SIZE 128
1158 static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE)));
1159 #endif
1160
1161 struct task_struct *__switch_to(struct task_struct *prev,
1162         struct task_struct *new)
1163 {
1164         struct thread_struct *new_thread, *old_thread;
1165         struct task_struct *last;
1166 #ifdef CONFIG_PPC_BOOK3S_64
1167         struct ppc64_tlb_batch *batch;
1168 #endif
1169
1170         new_thread = &new->thread;
1171         old_thread = &current->thread;
1172
1173         WARN_ON(!irqs_disabled());
1174
1175 #ifdef CONFIG_PPC_BOOK3S_64
1176         batch = this_cpu_ptr(&ppc64_tlb_batch);
1177         if (batch->active) {
1178                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1179                 if (batch->index)
1180                         __flush_tlb_pending(batch);
1181                 batch->active = 0;
1182         }
1183 #endif /* CONFIG_PPC_BOOK3S_64 */
1184
1185 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1186         switch_booke_debug_regs(&new->thread.debug);
1187 #else
1188 /*
1189  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1190  * schedule DABR
1191  */
1192 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1193         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1194                 __set_breakpoint(&new->thread.hw_brk);
1195 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1196 #endif
1197
1198         /*
1199          * We need to save SPRs before treclaim/trecheckpoint as these will
1200          * change a number of them.
1201          */
1202         save_sprs(&prev->thread);
1203
1204         /* Save FPU, Altivec, VSX and SPE state */
1205         giveup_all(prev);
1206
1207         __switch_to_tm(prev, new);
1208
1209         if (!radix_enabled()) {
1210                 /*
1211                  * We can't take a PMU exception inside _switch() since there
1212                  * is a window where the kernel stack SLB and the kernel stack
1213                  * are out of sync. Hard disable here.
1214                  */
1215                 hard_irq_disable();
1216         }
1217
1218         /*
1219          * Call restore_sprs() before calling _switch(). If we move it after
1220          * _switch() then we miss out on calling it for new tasks. The reason
1221          * for this is we manually create a stack frame for new tasks that
1222          * directly returns through ret_from_fork() or
1223          * ret_from_kernel_thread(). See copy_thread() for details.
1224          */
1225         restore_sprs(old_thread, new_thread);
1226
1227         last = _switch(old_thread, new_thread);
1228
1229 #ifdef CONFIG_PPC_BOOK3S_64
1230         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1231                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1232                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1233                 batch->active = 1;
1234         }
1235
1236         if (current_thread_info()->task->thread.regs) {
1237                 restore_math(current_thread_info()->task->thread.regs);
1238
1239                 /*
1240                  * The copy-paste buffer can only store into foreign real
1241                  * addresses, so unprivileged processes can not see the
1242                  * data or use it in any way unless they have foreign real
1243                  * mappings. If the new process has the foreign real address
1244                  * mappings, we must issue a cp_abort to clear any state and
1245                  * prevent snooping, corruption or a covert channel.
1246                  */
1247                 if (current_thread_info()->task->thread.used_vas)
1248                         asm volatile(PPC_CP_ABORT);
1249         }
1250 #endif /* CONFIG_PPC_BOOK3S_64 */
1251
1252         return last;
1253 }
1254
1255 static int instructions_to_print = 16;
1256
1257 static void show_instructions(struct pt_regs *regs)
1258 {
1259         int i;
1260         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1261                         sizeof(int));
1262
1263         printk("Instruction dump:");
1264
1265         for (i = 0; i < instructions_to_print; i++) {
1266                 int instr;
1267
1268                 if (!(i % 8))
1269                         pr_cont("\n");
1270
1271 #if !defined(CONFIG_BOOKE)
1272                 /* If executing with the IMMU off, adjust pc rather
1273                  * than print XXXXXXXX.
1274                  */
1275                 if (!(regs->msr & MSR_IR))
1276                         pc = (unsigned long)phys_to_virt(pc);
1277 #endif
1278
1279                 if (!__kernel_text_address(pc) ||
1280                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1281                         pr_cont("XXXXXXXX ");
1282                 } else {
1283                         if (regs->nip == pc)
1284                                 pr_cont("<%08x> ", instr);
1285                         else
1286                                 pr_cont("%08x ", instr);
1287                 }
1288
1289                 pc += sizeof(int);
1290         }
1291
1292         pr_cont("\n");
1293 }
1294
1295 void show_user_instructions(struct pt_regs *regs)
1296 {
1297         unsigned long pc;
1298         int i;
1299
1300         pc = regs->nip - (instructions_to_print * 3 / 4 * sizeof(int));
1301
1302         /*
1303          * Make sure the NIP points at userspace, not kernel text/data or
1304          * elsewhere.
1305          */
1306         if (!__access_ok(pc, instructions_to_print * sizeof(int), USER_DS)) {
1307                 pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1308                         current->comm, current->pid);
1309                 return;
1310         }
1311
1312         pr_info("%s[%d]: code: ", current->comm, current->pid);
1313
1314         for (i = 0; i < instructions_to_print; i++) {
1315                 int instr;
1316
1317                 if (!(i % 8) && (i > 0)) {
1318                         pr_cont("\n");
1319                         pr_info("%s[%d]: code: ", current->comm, current->pid);
1320                 }
1321
1322                 if (probe_kernel_address((unsigned int __user *)pc, instr)) {
1323                         pr_cont("XXXXXXXX ");
1324                 } else {
1325                         if (regs->nip == pc)
1326                                 pr_cont("<%08x> ", instr);
1327                         else
1328                                 pr_cont("%08x ", instr);
1329                 }
1330
1331                 pc += sizeof(int);
1332         }
1333
1334         pr_cont("\n");
1335 }
1336
1337 struct regbit {
1338         unsigned long bit;
1339         const char *name;
1340 };
1341
1342 static struct regbit msr_bits[] = {
1343 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1344         {MSR_SF,        "SF"},
1345         {MSR_HV,        "HV"},
1346 #endif
1347         {MSR_VEC,       "VEC"},
1348         {MSR_VSX,       "VSX"},
1349 #ifdef CONFIG_BOOKE
1350         {MSR_CE,        "CE"},
1351 #endif
1352         {MSR_EE,        "EE"},
1353         {MSR_PR,        "PR"},
1354         {MSR_FP,        "FP"},
1355         {MSR_ME,        "ME"},
1356 #ifdef CONFIG_BOOKE
1357         {MSR_DE,        "DE"},
1358 #else
1359         {MSR_SE,        "SE"},
1360         {MSR_BE,        "BE"},
1361 #endif
1362         {MSR_IR,        "IR"},
1363         {MSR_DR,        "DR"},
1364         {MSR_PMM,       "PMM"},
1365 #ifndef CONFIG_BOOKE
1366         {MSR_RI,        "RI"},
1367         {MSR_LE,        "LE"},
1368 #endif
1369         {0,             NULL}
1370 };
1371
1372 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1373 {
1374         const char *s = "";
1375
1376         for (; bits->bit; ++bits)
1377                 if (val & bits->bit) {
1378                         pr_cont("%s%s", s, bits->name);
1379                         s = sep;
1380                 }
1381 }
1382
1383 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1384 static struct regbit msr_tm_bits[] = {
1385         {MSR_TS_T,      "T"},
1386         {MSR_TS_S,      "S"},
1387         {MSR_TM,        "E"},
1388         {0,             NULL}
1389 };
1390
1391 static void print_tm_bits(unsigned long val)
1392 {
1393 /*
1394  * This only prints something if at least one of the TM bit is set.
1395  * Inside the TM[], the output means:
1396  *   E: Enabled         (bit 32)
1397  *   S: Suspended       (bit 33)
1398  *   T: Transactional   (bit 34)
1399  */
1400         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1401                 pr_cont(",TM[");
1402                 print_bits(val, msr_tm_bits, "");
1403                 pr_cont("]");
1404         }
1405 }
1406 #else
1407 static void print_tm_bits(unsigned long val) {}
1408 #endif
1409
1410 static void print_msr_bits(unsigned long val)
1411 {
1412         pr_cont("<");
1413         print_bits(val, msr_bits, ",");
1414         print_tm_bits(val);
1415         pr_cont(">");
1416 }
1417
1418 #ifdef CONFIG_PPC64
1419 #define REG             "%016lx"
1420 #define REGS_PER_LINE   4
1421 #define LAST_VOLATILE   13
1422 #else
1423 #define REG             "%08lx"
1424 #define REGS_PER_LINE   8
1425 #define LAST_VOLATILE   12
1426 #endif
1427
1428 void show_regs(struct pt_regs * regs)
1429 {
1430         int i, trap;
1431
1432         show_regs_print_info(KERN_DEFAULT);
1433
1434         printk("NIP:  "REG" LR: "REG" CTR: "REG"\n",
1435                regs->nip, regs->link, regs->ctr);
1436         printk("REGS: %px TRAP: %04lx   %s  (%s)\n",
1437                regs, regs->trap, print_tainted(), init_utsname()->release);
1438         printk("MSR:  "REG" ", regs->msr);
1439         print_msr_bits(regs->msr);
1440         pr_cont("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1441         trap = TRAP(regs);
1442         if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1443                 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1444         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1445 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1446                 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1447 #else
1448                 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1449 #endif
1450 #ifdef CONFIG_PPC64
1451         pr_cont("IRQMASK: %lx ", regs->softe);
1452 #endif
1453 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1454         if (MSR_TM_ACTIVE(regs->msr))
1455                 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1456 #endif
1457
1458         for (i = 0;  i < 32;  i++) {
1459                 if ((i % REGS_PER_LINE) == 0)
1460                         pr_cont("\nGPR%02d: ", i);
1461                 pr_cont(REG " ", regs->gpr[i]);
1462                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1463                         break;
1464         }
1465         pr_cont("\n");
1466 #ifdef CONFIG_KALLSYMS
1467         /*
1468          * Lookup NIP late so we have the best change of getting the
1469          * above info out without failing
1470          */
1471         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1472         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1473 #endif
1474         show_stack(current, (unsigned long *) regs->gpr[1]);
1475         if (!user_mode(regs))
1476                 show_instructions(regs);
1477 }
1478
1479 void flush_thread(void)
1480 {
1481 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1482         flush_ptrace_hw_breakpoint(current);
1483 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1484         set_debug_reg_defaults(&current->thread);
1485 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1486 }
1487
1488 int set_thread_uses_vas(void)
1489 {
1490 #ifdef CONFIG_PPC_BOOK3S_64
1491         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1492                 return -EINVAL;
1493
1494         current->thread.used_vas = 1;
1495
1496         /*
1497          * Even a process that has no foreign real address mapping can use
1498          * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1499          * to clear any pending COPY and prevent a covert channel.
1500          *
1501          * __switch_to() will issue CP_ABORT on future context switches.
1502          */
1503         asm volatile(PPC_CP_ABORT);
1504
1505 #endif /* CONFIG_PPC_BOOK3S_64 */
1506         return 0;
1507 }
1508
1509 #ifdef CONFIG_PPC64
1510 /**
1511  * Assign a TIDR (thread ID) for task @t and set it in the thread
1512  * structure. For now, we only support setting TIDR for 'current' task.
1513  *
1514  * Since the TID value is a truncated form of it PID, it is possible
1515  * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1516  * that 2 threads share the same TID and are waiting, one of the following
1517  * cases will happen:
1518  *
1519  * 1. The correct thread is running, the wrong thread is not
1520  * In this situation, the correct thread is woken and proceeds to pass it's
1521  * condition check.
1522  *
1523  * 2. Neither threads are running
1524  * In this situation, neither thread will be woken. When scheduled, the waiting
1525  * threads will execute either a wait, which will return immediately, followed
1526  * by a condition check, which will pass for the correct thread and fail
1527  * for the wrong thread, or they will execute the condition check immediately.
1528  *
1529  * 3. The wrong thread is running, the correct thread is not
1530  * The wrong thread will be woken, but will fail it's condition check and
1531  * re-execute wait. The correct thread, when scheduled, will execute either
1532  * it's condition check (which will pass), or wait, which returns immediately
1533  * when called the first time after the thread is scheduled, followed by it's
1534  * condition check (which will pass).
1535  *
1536  * 4. Both threads are running
1537  * Both threads will be woken. The wrong thread will fail it's condition check
1538  * and execute another wait, while the correct thread will pass it's condition
1539  * check.
1540  *
1541  * @t: the task to set the thread ID for
1542  */
1543 int set_thread_tidr(struct task_struct *t)
1544 {
1545         if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1546                 return -EINVAL;
1547
1548         if (t != current)
1549                 return -EINVAL;
1550
1551         if (t->thread.tidr)
1552                 return 0;
1553
1554         t->thread.tidr = (u16)task_pid_nr(t);
1555         mtspr(SPRN_TIDR, t->thread.tidr);
1556
1557         return 0;
1558 }
1559 EXPORT_SYMBOL_GPL(set_thread_tidr);
1560
1561 #endif /* CONFIG_PPC64 */
1562
1563 void
1564 release_thread(struct task_struct *t)
1565 {
1566 }
1567
1568 /*
1569  * this gets called so that we can store coprocessor state into memory and
1570  * copy the current task into the new thread.
1571  */
1572 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1573 {
1574         flush_all_to_thread(src);
1575         /*
1576          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1577          * flush but it removes the checkpointed state from the current CPU and
1578          * transitions the CPU out of TM mode.  Hence we need to call
1579          * tm_recheckpoint_new_task() (on the same task) to restore the
1580          * checkpointed state back and the TM mode.
1581          *
1582          * Can't pass dst because it isn't ready. Doesn't matter, passing
1583          * dst is only important for __switch_to()
1584          */
1585         __switch_to_tm(src, src);
1586
1587         *dst = *src;
1588
1589         clear_task_ebb(dst);
1590
1591         return 0;
1592 }
1593
1594 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1595 {
1596 #ifdef CONFIG_PPC_BOOK3S_64
1597         unsigned long sp_vsid;
1598         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1599
1600         if (radix_enabled())
1601                 return;
1602
1603         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1604                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1605                         << SLB_VSID_SHIFT_1T;
1606         else
1607                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1608                         << SLB_VSID_SHIFT;
1609         sp_vsid |= SLB_VSID_KERNEL | llp;
1610         p->thread.ksp_vsid = sp_vsid;
1611 #endif
1612 }
1613
1614 /*
1615  * Copy a thread..
1616  */
1617
1618 /*
1619  * Copy architecture-specific thread state
1620  */
1621 int copy_thread(unsigned long clone_flags, unsigned long usp,
1622                 unsigned long kthread_arg, struct task_struct *p)
1623 {
1624         struct pt_regs *childregs, *kregs;
1625         extern void ret_from_fork(void);
1626         extern void ret_from_kernel_thread(void);
1627         void (*f)(void);
1628         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1629         struct thread_info *ti = task_thread_info(p);
1630
1631         klp_init_thread_info(ti);
1632
1633         /* Copy registers */
1634         sp -= sizeof(struct pt_regs);
1635         childregs = (struct pt_regs *) sp;
1636         if (unlikely(p->flags & PF_KTHREAD)) {
1637                 /* kernel thread */
1638                 memset(childregs, 0, sizeof(struct pt_regs));
1639                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1640                 /* function */
1641                 if (usp)
1642                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1643 #ifdef CONFIG_PPC64
1644                 clear_tsk_thread_flag(p, TIF_32BIT);
1645                 childregs->softe = IRQS_ENABLED;
1646 #endif
1647                 childregs->gpr[15] = kthread_arg;
1648                 p->thread.regs = NULL;  /* no user register state */
1649                 ti->flags |= _TIF_RESTOREALL;
1650                 f = ret_from_kernel_thread;
1651         } else {
1652                 /* user thread */
1653                 struct pt_regs *regs = current_pt_regs();
1654                 CHECK_FULL_REGS(regs);
1655                 *childregs = *regs;
1656                 if (usp)
1657                         childregs->gpr[1] = usp;
1658                 p->thread.regs = childregs;
1659                 childregs->gpr[3] = 0;  /* Result from fork() */
1660                 if (clone_flags & CLONE_SETTLS) {
1661 #ifdef CONFIG_PPC64
1662                         if (!is_32bit_task())
1663                                 childregs->gpr[13] = childregs->gpr[6];
1664                         else
1665 #endif
1666                                 childregs->gpr[2] = childregs->gpr[6];
1667                 }
1668
1669                 f = ret_from_fork;
1670         }
1671         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1672         sp -= STACK_FRAME_OVERHEAD;
1673
1674         /*
1675          * The way this works is that at some point in the future
1676          * some task will call _switch to switch to the new task.
1677          * That will pop off the stack frame created below and start
1678          * the new task running at ret_from_fork.  The new task will
1679          * do some house keeping and then return from the fork or clone
1680          * system call, using the stack frame created above.
1681          */
1682         ((unsigned long *)sp)[0] = 0;
1683         sp -= sizeof(struct pt_regs);
1684         kregs = (struct pt_regs *) sp;
1685         sp -= STACK_FRAME_OVERHEAD;
1686         p->thread.ksp = sp;
1687 #ifdef CONFIG_PPC32
1688         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1689                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1690 #endif
1691 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1692         p->thread.ptrace_bps[0] = NULL;
1693 #endif
1694
1695         p->thread.fp_save_area = NULL;
1696 #ifdef CONFIG_ALTIVEC
1697         p->thread.vr_save_area = NULL;
1698 #endif
1699
1700         setup_ksp_vsid(p, sp);
1701
1702 #ifdef CONFIG_PPC64
1703         if (cpu_has_feature(CPU_FTR_DSCR)) {
1704                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1705                 p->thread.dscr = mfspr(SPRN_DSCR);
1706         }
1707         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1708                 p->thread.ppr = INIT_PPR;
1709
1710         p->thread.tidr = 0;
1711 #endif
1712         kregs->nip = ppc_function_entry(f);
1713         return 0;
1714 }
1715
1716 /*
1717  * Set up a thread for executing a new program
1718  */
1719 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1720 {
1721 #ifdef CONFIG_PPC64
1722         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1723 #endif
1724
1725         /*
1726          * If we exec out of a kernel thread then thread.regs will not be
1727          * set.  Do it now.
1728          */
1729         if (!current->thread.regs) {
1730                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1731                 current->thread.regs = regs - 1;
1732         }
1733
1734 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1735         /*
1736          * Clear any transactional state, we're exec()ing. The cause is
1737          * not important as there will never be a recheckpoint so it's not
1738          * user visible.
1739          */
1740         if (MSR_TM_SUSPENDED(mfmsr()))
1741                 tm_reclaim_current(0);
1742 #endif
1743
1744         memset(regs->gpr, 0, sizeof(regs->gpr));
1745         regs->ctr = 0;
1746         regs->link = 0;
1747         regs->xer = 0;
1748         regs->ccr = 0;
1749         regs->gpr[1] = sp;
1750
1751         /*
1752          * We have just cleared all the nonvolatile GPRs, so make
1753          * FULL_REGS(regs) return true.  This is necessary to allow
1754          * ptrace to examine the thread immediately after exec.
1755          */
1756         regs->trap &= ~1UL;
1757
1758 #ifdef CONFIG_PPC32
1759         regs->mq = 0;
1760         regs->nip = start;
1761         regs->msr = MSR_USER;
1762 #else
1763         if (!is_32bit_task()) {
1764                 unsigned long entry;
1765
1766                 if (is_elf2_task()) {
1767                         /* Look ma, no function descriptors! */
1768                         entry = start;
1769
1770                         /*
1771                          * Ulrich says:
1772                          *   The latest iteration of the ABI requires that when
1773                          *   calling a function (at its global entry point),
1774                          *   the caller must ensure r12 holds the entry point
1775                          *   address (so that the function can quickly
1776                          *   establish addressability).
1777                          */
1778                         regs->gpr[12] = start;
1779                         /* Make sure that's restored on entry to userspace. */
1780                         set_thread_flag(TIF_RESTOREALL);
1781                 } else {
1782                         unsigned long toc;
1783
1784                         /* start is a relocated pointer to the function
1785                          * descriptor for the elf _start routine.  The first
1786                          * entry in the function descriptor is the entry
1787                          * address of _start and the second entry is the TOC
1788                          * value we need to use.
1789                          */
1790                         __get_user(entry, (unsigned long __user *)start);
1791                         __get_user(toc, (unsigned long __user *)start+1);
1792
1793                         /* Check whether the e_entry function descriptor entries
1794                          * need to be relocated before we can use them.
1795                          */
1796                         if (load_addr != 0) {
1797                                 entry += load_addr;
1798                                 toc   += load_addr;
1799                         }
1800                         regs->gpr[2] = toc;
1801                 }
1802                 regs->nip = entry;
1803                 regs->msr = MSR_USER64;
1804         } else {
1805                 regs->nip = start;
1806                 regs->gpr[2] = 0;
1807                 regs->msr = MSR_USER32;
1808         }
1809 #endif
1810 #ifdef CONFIG_VSX
1811         current->thread.used_vsr = 0;
1812 #endif
1813         current->thread.load_fp = 0;
1814         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1815         current->thread.fp_save_area = NULL;
1816 #ifdef CONFIG_ALTIVEC
1817         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1818         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1819         current->thread.vr_save_area = NULL;
1820         current->thread.vrsave = 0;
1821         current->thread.used_vr = 0;
1822         current->thread.load_vec = 0;
1823 #endif /* CONFIG_ALTIVEC */
1824 #ifdef CONFIG_SPE
1825         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1826         current->thread.acc = 0;
1827         current->thread.spefscr = 0;
1828         current->thread.used_spe = 0;
1829 #endif /* CONFIG_SPE */
1830 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1831         current->thread.tm_tfhar = 0;
1832         current->thread.tm_texasr = 0;
1833         current->thread.tm_tfiar = 0;
1834         current->thread.load_tm = 0;
1835 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1836
1837         thread_pkey_regs_init(&current->thread);
1838 }
1839 EXPORT_SYMBOL(start_thread);
1840
1841 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1842                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1843
1844 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1845 {
1846         struct pt_regs *regs = tsk->thread.regs;
1847
1848         /* This is a bit hairy.  If we are an SPE enabled  processor
1849          * (have embedded fp) we store the IEEE exception enable flags in
1850          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1851          * mode (asyn, precise, disabled) for 'Classic' FP. */
1852         if (val & PR_FP_EXC_SW_ENABLE) {
1853 #ifdef CONFIG_SPE
1854                 if (cpu_has_feature(CPU_FTR_SPE)) {
1855                         /*
1856                          * When the sticky exception bits are set
1857                          * directly by userspace, it must call prctl
1858                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1859                          * in the existing prctl settings) or
1860                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1861                          * the bits being set).  <fenv.h> functions
1862                          * saving and restoring the whole
1863                          * floating-point environment need to do so
1864                          * anyway to restore the prctl settings from
1865                          * the saved environment.
1866                          */
1867                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1868                         tsk->thread.fpexc_mode = val &
1869                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1870                         return 0;
1871                 } else {
1872                         return -EINVAL;
1873                 }
1874 #else
1875                 return -EINVAL;
1876 #endif
1877         }
1878
1879         /* on a CONFIG_SPE this does not hurt us.  The bits that
1880          * __pack_fe01 use do not overlap with bits used for
1881          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1882          * on CONFIG_SPE implementations are reserved so writing to
1883          * them does not change anything */
1884         if (val > PR_FP_EXC_PRECISE)
1885                 return -EINVAL;
1886         tsk->thread.fpexc_mode = __pack_fe01(val);
1887         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1888                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1889                         | tsk->thread.fpexc_mode;
1890         return 0;
1891 }
1892
1893 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1894 {
1895         unsigned int val;
1896
1897         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1898 #ifdef CONFIG_SPE
1899                 if (cpu_has_feature(CPU_FTR_SPE)) {
1900                         /*
1901                          * When the sticky exception bits are set
1902                          * directly by userspace, it must call prctl
1903                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1904                          * in the existing prctl settings) or
1905                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1906                          * the bits being set).  <fenv.h> functions
1907                          * saving and restoring the whole
1908                          * floating-point environment need to do so
1909                          * anyway to restore the prctl settings from
1910                          * the saved environment.
1911                          */
1912                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1913                         val = tsk->thread.fpexc_mode;
1914                 } else
1915                         return -EINVAL;
1916 #else
1917                 return -EINVAL;
1918 #endif
1919         else
1920                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1921         return put_user(val, (unsigned int __user *) adr);
1922 }
1923
1924 int set_endian(struct task_struct *tsk, unsigned int val)
1925 {
1926         struct pt_regs *regs = tsk->thread.regs;
1927
1928         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1929             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1930                 return -EINVAL;
1931
1932         if (regs == NULL)
1933                 return -EINVAL;
1934
1935         if (val == PR_ENDIAN_BIG)
1936                 regs->msr &= ~MSR_LE;
1937         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1938                 regs->msr |= MSR_LE;
1939         else
1940                 return -EINVAL;
1941
1942         return 0;
1943 }
1944
1945 int get_endian(struct task_struct *tsk, unsigned long adr)
1946 {
1947         struct pt_regs *regs = tsk->thread.regs;
1948         unsigned int val;
1949
1950         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1951             !cpu_has_feature(CPU_FTR_REAL_LE))
1952                 return -EINVAL;
1953
1954         if (regs == NULL)
1955                 return -EINVAL;
1956
1957         if (regs->msr & MSR_LE) {
1958                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1959                         val = PR_ENDIAN_LITTLE;
1960                 else
1961                         val = PR_ENDIAN_PPC_LITTLE;
1962         } else
1963                 val = PR_ENDIAN_BIG;
1964
1965         return put_user(val, (unsigned int __user *)adr);
1966 }
1967
1968 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1969 {
1970         tsk->thread.align_ctl = val;
1971         return 0;
1972 }
1973
1974 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1975 {
1976         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1977 }
1978
1979 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1980                                   unsigned long nbytes)
1981 {
1982         unsigned long stack_page;
1983         unsigned long cpu = task_cpu(p);
1984
1985         /*
1986          * Avoid crashing if the stack has overflowed and corrupted
1987          * task_cpu(p), which is in the thread_info struct.
1988          */
1989         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1990                 stack_page = (unsigned long) hardirq_ctx[cpu];
1991                 if (sp >= stack_page + sizeof(struct thread_struct)
1992                     && sp <= stack_page + THREAD_SIZE - nbytes)
1993                         return 1;
1994
1995                 stack_page = (unsigned long) softirq_ctx[cpu];
1996                 if (sp >= stack_page + sizeof(struct thread_struct)
1997                     && sp <= stack_page + THREAD_SIZE - nbytes)
1998                         return 1;
1999         }
2000         return 0;
2001 }
2002
2003 int validate_sp(unsigned long sp, struct task_struct *p,
2004                        unsigned long nbytes)
2005 {
2006         unsigned long stack_page = (unsigned long)task_stack_page(p);
2007
2008         if (sp >= stack_page + sizeof(struct thread_struct)
2009             && sp <= stack_page + THREAD_SIZE - nbytes)
2010                 return 1;
2011
2012         return valid_irq_stack(sp, p, nbytes);
2013 }
2014
2015 EXPORT_SYMBOL(validate_sp);
2016
2017 unsigned long get_wchan(struct task_struct *p)
2018 {
2019         unsigned long ip, sp;
2020         int count = 0;
2021
2022         if (!p || p == current || p->state == TASK_RUNNING)
2023                 return 0;
2024
2025         sp = p->thread.ksp;
2026         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2027                 return 0;
2028
2029         do {
2030                 sp = *(unsigned long *)sp;
2031                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2032                     p->state == TASK_RUNNING)
2033                         return 0;
2034                 if (count > 0) {
2035                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2036                         if (!in_sched_functions(ip))
2037                                 return ip;
2038                 }
2039         } while (count++ < 16);
2040         return 0;
2041 }
2042
2043 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2044
2045 void show_stack(struct task_struct *tsk, unsigned long *stack)
2046 {
2047         unsigned long sp, ip, lr, newsp;
2048         int count = 0;
2049         int firstframe = 1;
2050 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2051         int curr_frame = current->curr_ret_stack;
2052         extern void return_to_handler(void);
2053         unsigned long rth = (unsigned long)return_to_handler;
2054 #endif
2055
2056         sp = (unsigned long) stack;
2057         if (tsk == NULL)
2058                 tsk = current;
2059         if (sp == 0) {
2060                 if (tsk == current)
2061                         sp = current_stack_pointer();
2062                 else
2063                         sp = tsk->thread.ksp;
2064         }
2065
2066         lr = 0;
2067         printk("Call Trace:\n");
2068         do {
2069                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2070                         return;
2071
2072                 stack = (unsigned long *) sp;
2073                 newsp = stack[0];
2074                 ip = stack[STACK_FRAME_LR_SAVE];
2075                 if (!firstframe || ip != lr) {
2076                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2077 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2078                         if ((ip == rth) && curr_frame >= 0) {
2079                                 pr_cont(" (%pS)",
2080                                        (void *)current->ret_stack[curr_frame].ret);
2081                                 curr_frame--;
2082                         }
2083 #endif
2084                         if (firstframe)
2085                                 pr_cont(" (unreliable)");
2086                         pr_cont("\n");
2087                 }
2088                 firstframe = 0;
2089
2090                 /*
2091                  * See if this is an exception frame.
2092                  * We look for the "regshere" marker in the current frame.
2093                  */
2094                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2095                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2096                         struct pt_regs *regs = (struct pt_regs *)
2097                                 (sp + STACK_FRAME_OVERHEAD);
2098                         lr = regs->link;
2099                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
2100                                regs->trap, (void *)regs->nip, (void *)lr);
2101                         firstframe = 1;
2102                 }
2103
2104                 sp = newsp;
2105         } while (count++ < kstack_depth_to_print);
2106 }
2107
2108 #ifdef CONFIG_PPC64
2109 /* Called with hard IRQs off */
2110 void notrace __ppc64_runlatch_on(void)
2111 {
2112         struct thread_info *ti = current_thread_info();
2113
2114         if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2115                 /*
2116                  * Least significant bit (RUN) is the only writable bit of
2117                  * the CTRL register, so we can avoid mfspr. 2.06 is not the
2118                  * earliest ISA where this is the case, but it's convenient.
2119                  */
2120                 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2121         } else {
2122                 unsigned long ctrl;
2123
2124                 /*
2125                  * Some architectures (e.g., Cell) have writable fields other
2126                  * than RUN, so do the read-modify-write.
2127                  */
2128                 ctrl = mfspr(SPRN_CTRLF);
2129                 ctrl |= CTRL_RUNLATCH;
2130                 mtspr(SPRN_CTRLT, ctrl);
2131         }
2132
2133         ti->local_flags |= _TLF_RUNLATCH;
2134 }
2135
2136 /* Called with hard IRQs off */
2137 void notrace __ppc64_runlatch_off(void)
2138 {
2139         struct thread_info *ti = current_thread_info();
2140
2141         ti->local_flags &= ~_TLF_RUNLATCH;
2142
2143         if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2144                 mtspr(SPRN_CTRLT, 0);
2145         } else {
2146                 unsigned long ctrl;
2147
2148                 ctrl = mfspr(SPRN_CTRLF);
2149                 ctrl &= ~CTRL_RUNLATCH;
2150                 mtspr(SPRN_CTRLT, ctrl);
2151         }
2152 }
2153 #endif /* CONFIG_PPC64 */
2154
2155 unsigned long arch_align_stack(unsigned long sp)
2156 {
2157         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2158                 sp -= get_random_int() & ~PAGE_MASK;
2159         return sp & ~0xf;
2160 }
2161
2162 static inline unsigned long brk_rnd(void)
2163 {
2164         unsigned long rnd = 0;
2165
2166         /* 8MB for 32bit, 1GB for 64bit */
2167         if (is_32bit_task())
2168                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2169         else
2170                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2171
2172         return rnd << PAGE_SHIFT;
2173 }
2174
2175 unsigned long arch_randomize_brk(struct mm_struct *mm)
2176 {
2177         unsigned long base = mm->brk;
2178         unsigned long ret;
2179
2180 #ifdef CONFIG_PPC_BOOK3S_64
2181         /*
2182          * If we are using 1TB segments and we are allowed to randomise
2183          * the heap, we can put it above 1TB so it is backed by a 1TB
2184          * segment. Otherwise the heap will be in the bottom 1TB
2185          * which always uses 256MB segments and this may result in a
2186          * performance penalty. We don't need to worry about radix. For
2187          * radix, mmu_highuser_ssize remains unchanged from 256MB.
2188          */
2189         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2190                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2191 #endif
2192
2193         ret = PAGE_ALIGN(base + brk_rnd());
2194
2195         if (ret < mm->brk)
2196                 return mm->brk;
2197
2198         return ret;
2199 }
2200