arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/debug.h>
  20 #include <linux/sched/task.h>
  21 #include <linux/sched/task_stack.h>
  22 #include <linux/kernel.h>
  23 #include <linux/mm.h>
  24 #include <linux/smp.h>
  25 #include <linux/stddef.h>
  26 #include <linux/unistd.h>
  27 #include <linux/ptrace.h>
  28 #include <linux/slab.h>
  29 #include <linux/user.h>
  30 #include <linux/elf.h>
  31 #include <linux/prctl.h>
  32 #include <linux/init_task.h>
  33 #include <linux/export.h>
  34 #include <linux/kallsyms.h>
  35 #include <linux/mqueue.h>
  36 #include <linux/hardirq.h>
  37 #include <linux/utsname.h>
  38 #include <linux/ftrace.h>
  39 #include <linux/kernel_stat.h>
  40 #include <linux/personality.h>
  41 #include <linux/random.h>
  42 #include <linux/hw_breakpoint.h>
  43 #include <linux/uaccess.h>
  44 #include <linux/elf-randomize.h>
  45
  46 #include <asm/pgtable.h>
  47 #include <asm/io.h>
  48 #include <asm/processor.h>
  49 #include <asm/mmu.h>
  50 #include <asm/prom.h>
  51 #include <asm/machdep.h>
  52 #include <asm/time.h>
  53 #include <asm/runlatch.h>
  54 #include <asm/syscalls.h>
  55 #include <asm/switch_to.h>
  56 #include <asm/tm.h>
  57 #include <asm/debug.h>
  58 #ifdef CONFIG_PPC64
  59 #include <asm/firmware.h>
  60 #endif
  61 #include <asm/code-patching.h>
  62 #include <asm/exec.h>
  63 #include <asm/livepatch.h>
  64 #include <asm/cpu_has_feature.h>
  65 #include <asm/asm-prototypes.h>
  66
  67 #include <linux/kprobes.h>
  68 #include <linux/kdebug.h>
  69
  70 /* Transactional Memory debug */
  71 #ifdef TM_DEBUG_SW
  72 #define TM_DEBUG(x...) printk(KERN_INFO x)
  73 #else
  74 #define TM_DEBUG(x...) do { } while(0)
  75 #endif
  76
  77 extern unsigned long _get_SP(void);
  78
  79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  80 /*
  81  * Are we running in "Suspend disabled" mode? If so we have to block any
  82  * sigreturn that would get us into suspended state, and we also warn in some
  83  * other paths that we should never reach with suspend disabled.
  84  */
  85 bool tm_suspend_disabled __ro_after_init = false;
  86
  87 static void check_if_tm_restore_required(struct task_struct *tsk)
  88 {
  89         /*
  90          * If we are saving the current thread's registers, and the
  91          * thread is in a transactional state, set the TIF_RESTORE_TM
  92          * bit so that we know to restore the registers before
  93          * returning to userspace.
  94          */
  95         if (tsk == current && tsk->thread.regs &&
  96             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  97             !test_thread_flag(TIF_RESTORE_TM)) {
  98                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  99                 set_thread_flag(TIF_RESTORE_TM);
 100         }
 101 }
 102
 103 static inline bool msr_tm_active(unsigned long msr)
 104 {
 105         return MSR_TM_ACTIVE(msr);
 106 }
 107
 108 static bool tm_active_with_fp(struct task_struct *tsk)
 109 {
 110         return msr_tm_active(tsk->thread.regs->msr) &&
 111                 (tsk->thread.ckpt_regs.msr & MSR_FP);
 112 }
 113
 114 static bool tm_active_with_altivec(struct task_struct *tsk)
 115 {
 116         return msr_tm_active(tsk->thread.regs->msr) &&
 117                 (tsk->thread.ckpt_regs.msr & MSR_VEC);
 118 }
 119 #else
 120 static inline bool msr_tm_active(unsigned long msr) { return false; }
 121 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 122 static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; }
 123 static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; }
 124 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 125
 126 bool strict_msr_control;
 127 EXPORT_SYMBOL(strict_msr_control);
 128
 129 static int __init enable_strict_msr_control(char *str)
 130 {
 131         strict_msr_control = true;
 132         pr_info("Enabling strict facility control\n");
 133
 134         return 0;
 135 }
 136 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 137
 138 unsigned long msr_check_and_set(unsigned long bits)
 139 {
 140         unsigned long oldmsr = mfmsr();
 141         unsigned long newmsr;
 142
 143         newmsr = oldmsr | bits;
 144
 145 #ifdef CONFIG_VSX
 146         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 147                 newmsr |= MSR_VSX;
 148 #endif
 149
 150         if (oldmsr != newmsr)
 151                 mtmsr_isync(newmsr);
 152
 153         return newmsr;
 154 }
 155
 156 void __msr_check_and_clear(unsigned long bits)
 157 {
 158         unsigned long oldmsr = mfmsr();
 159         unsigned long newmsr;
 160
 161         newmsr = oldmsr & ~bits;
 162
 163 #ifdef CONFIG_VSX
 164         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 165                 newmsr &= ~MSR_VSX;
 166 #endif
 167
 168         if (oldmsr != newmsr)
 169                 mtmsr_isync(newmsr);
 170 }
 171 EXPORT_SYMBOL(__msr_check_and_clear);
 172
 173 #ifdef CONFIG_PPC_FPU
 174 void __giveup_fpu(struct task_struct *tsk)
 175 {
 176         unsigned long msr;
 177
 178         save_fpu(tsk);
 179         msr = tsk->thread.regs->msr;
 180         msr &= ~MSR_FP;
 181 #ifdef CONFIG_VSX
 182         if (cpu_has_feature(CPU_FTR_VSX))
 183                 msr &= ~MSR_VSX;
 184 #endif
 185         tsk->thread.regs->msr = msr;
 186 }
 187
 188 void giveup_fpu(struct task_struct *tsk)
 189 {
 190         check_if_tm_restore_required(tsk);
 191
 192         msr_check_and_set(MSR_FP);
 193         __giveup_fpu(tsk);
 194         msr_check_and_clear(MSR_FP);
 195 }
 196 EXPORT_SYMBOL(giveup_fpu);
 197
 198 /*
 199  * Make sure the floating-point register state in the
 200  * the thread_struct is up to date for task tsk.
 201  */
 202 void flush_fp_to_thread(struct task_struct *tsk)
 203 {
 204         if (tsk->thread.regs) {
 205                 /*
 206                  * We need to disable preemption here because if we didn't,
 207                  * another process could get scheduled after the regs->msr
 208                  * test but before we have finished saving the FP registers
 209                  * to the thread_struct.  That process could take over the
 210                  * FPU, and then when we get scheduled again we would store
 211                  * bogus values for the remaining FP registers.
 212                  */
 213                 preempt_disable();
 214                 if (tsk->thread.regs->msr & MSR_FP) {
 215                         /*
 216                          * This should only ever be called for current or
 217                          * for a stopped child process.  Since we save away
 218                          * the FP register state on context switch,
 219                          * there is something wrong if a stopped child appears
 220                          * to still have its FP state in the CPU registers.
 221                          */
 222                         BUG_ON(tsk != current);
 223                         giveup_fpu(tsk);
 224                 }
 225                 preempt_enable();
 226         }
 227 }
 228 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 229
 230 void enable_kernel_fp(void)
 231 {
 232         unsigned long cpumsr;
 233
 234         WARN_ON(preemptible());
 235
 236         cpumsr = msr_check_and_set(MSR_FP);
 237
 238         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 239                 check_if_tm_restore_required(current);
 240                 /*
 241                  * If a thread has already been reclaimed then the
 242                  * checkpointed registers are on the CPU but have definitely
 243                  * been saved by the reclaim code. Don't need to and *cannot*
 244                  * giveup as this would save  to the 'live' structure not the
 245                  * checkpointed structure.
 246                  */
 247                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 248                         return;
 249                 __giveup_fpu(current);
 250         }
 251 }
 252 EXPORT_SYMBOL(enable_kernel_fp);
 253
 254 static int restore_fp(struct task_struct *tsk)
 255 {
 256         if (tsk->thread.load_fp || tm_active_with_fp(tsk)) {
 257                 load_fp_state(&current->thread.fp_state);
 258                 current->thread.load_fp++;
 259                 return 1;
 260         }
 261         return 0;
 262 }
 263 #else
 264 static int restore_fp(struct task_struct *tsk) { return 0; }
 265 #endif /* CONFIG_PPC_FPU */
 266
 267 #ifdef CONFIG_ALTIVEC
 268 #define loadvec(thr) ((thr).load_vec)
 269
 270 static void __giveup_altivec(struct task_struct *tsk)
 271 {
 272         unsigned long msr;
 273
 274         save_altivec(tsk);
 275         msr = tsk->thread.regs->msr;
 276         msr &= ~MSR_VEC;
 277 #ifdef CONFIG_VSX
 278         if (cpu_has_feature(CPU_FTR_VSX))
 279                 msr &= ~MSR_VSX;
 280 #endif
 281         tsk->thread.regs->msr = msr;
 282 }
 283
 284 void giveup_altivec(struct task_struct *tsk)
 285 {
 286         check_if_tm_restore_required(tsk);
 287
 288         msr_check_and_set(MSR_VEC);
 289         __giveup_altivec(tsk);
 290         msr_check_and_clear(MSR_VEC);
 291 }
 292 EXPORT_SYMBOL(giveup_altivec);
 293
 294 void enable_kernel_altivec(void)
 295 {
 296         unsigned long cpumsr;
 297
 298         WARN_ON(preemptible());
 299
 300         cpumsr = msr_check_and_set(MSR_VEC);
 301
 302         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 303                 check_if_tm_restore_required(current);
 304                 /*
 305                  * If a thread has already been reclaimed then the
 306                  * checkpointed registers are on the CPU but have definitely
 307                  * been saved by the reclaim code. Don't need to and *cannot*
 308                  * giveup as this would save  to the 'live' structure not the
 309                  * checkpointed structure.
 310                  */
 311                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 312                         return;
 313                 __giveup_altivec(current);
 314         }
 315 }
 316 EXPORT_SYMBOL(enable_kernel_altivec);
 317
 318 /*
 319  * Make sure the VMX/Altivec register state in the
 320  * the thread_struct is up to date for task tsk.
 321  */
 322 void flush_altivec_to_thread(struct task_struct *tsk)
 323 {
 324         if (tsk->thread.regs) {
 325                 preempt_disable();
 326                 if (tsk->thread.regs->msr & MSR_VEC) {
 327                         BUG_ON(tsk != current);
 328                         giveup_altivec(tsk);
 329                 }
 330                 preempt_enable();
 331         }
 332 }
 333 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 334
 335 static int restore_altivec(struct task_struct *tsk)
 336 {
 337         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 338                 (tsk->thread.load_vec || tm_active_with_altivec(tsk))) {
 339                 load_vr_state(&tsk->thread.vr_state);
 340                 tsk->thread.used_vr = 1;
 341                 tsk->thread.load_vec++;
 342
 343                 return 1;
 344         }
 345         return 0;
 346 }
 347 #else
 348 #define loadvec(thr) 0
 349 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 350 #endif /* CONFIG_ALTIVEC */
 351
 352 #ifdef CONFIG_VSX
 353 static void __giveup_vsx(struct task_struct *tsk)
 354 {
 355         unsigned long msr = tsk->thread.regs->msr;
 356
 357         /*
 358          * We should never be ssetting MSR_VSX without also setting
 359          * MSR_FP and MSR_VEC
 360          */
 361         WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
 362
 363         /* __giveup_fpu will clear MSR_VSX */
 364         if (msr & MSR_FP)
 365                 __giveup_fpu(tsk);
 366         if (msr & MSR_VEC)
 367                 __giveup_altivec(tsk);
 368 }
 369
 370 static void giveup_vsx(struct task_struct *tsk)
 371 {
 372         check_if_tm_restore_required(tsk);
 373
 374         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 375         __giveup_vsx(tsk);
 376         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 377 }
 378
 379 void enable_kernel_vsx(void)
 380 {
 381         unsigned long cpumsr;
 382
 383         WARN_ON(preemptible());
 384
 385         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 386
 387         if (current->thread.regs &&
 388             (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
 389                 check_if_tm_restore_required(current);
 390                 /*
 391                  * If a thread has already been reclaimed then the
 392                  * checkpointed registers are on the CPU but have definitely
 393                  * been saved by the reclaim code. Don't need to and *cannot*
 394                  * giveup as this would save  to the 'live' structure not the
 395                  * checkpointed structure.
 396                  */
 397                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 398                         return;
 399                 __giveup_vsx(current);
 400         }
 401 }
 402 EXPORT_SYMBOL(enable_kernel_vsx);
 403
 404 void flush_vsx_to_thread(struct task_struct *tsk)
 405 {
 406         if (tsk->thread.regs) {
 407                 preempt_disable();
 408                 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
 409                         BUG_ON(tsk != current);
 410                         giveup_vsx(tsk);
 411                 }
 412                 preempt_enable();
 413         }
 414 }
 415 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 416
 417 static int restore_vsx(struct task_struct *tsk)
 418 {
 419         if (cpu_has_feature(CPU_FTR_VSX)) {
 420                 tsk->thread.used_vsr = 1;
 421                 return 1;
 422         }
 423
 424         return 0;
 425 }
 426 #else
 427 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 428 #endif /* CONFIG_VSX */
 429
 430 #ifdef CONFIG_SPE
 431 void giveup_spe(struct task_struct *tsk)
 432 {
 433         check_if_tm_restore_required(tsk);
 434
 435         msr_check_and_set(MSR_SPE);
 436         __giveup_spe(tsk);
 437         msr_check_and_clear(MSR_SPE);
 438 }
 439 EXPORT_SYMBOL(giveup_spe);
 440
 441 void enable_kernel_spe(void)
 442 {
 443         WARN_ON(preemptible());
 444
 445         msr_check_and_set(MSR_SPE);
 446
 447         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 448                 check_if_tm_restore_required(current);
 449                 __giveup_spe(current);
 450         }
 451 }
 452 EXPORT_SYMBOL(enable_kernel_spe);
 453
 454 void flush_spe_to_thread(struct task_struct *tsk)
 455 {
 456         if (tsk->thread.regs) {
 457                 preempt_disable();
 458                 if (tsk->thread.regs->msr & MSR_SPE) {
 459                         BUG_ON(tsk != current);
 460                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 461                         giveup_spe(tsk);
 462                 }
 463                 preempt_enable();
 464         }
 465 }
 466 #endif /* CONFIG_SPE */
 467
 468 static unsigned long msr_all_available;
 469
 470 static int __init init_msr_all_available(void)
 471 {
 472 #ifdef CONFIG_PPC_FPU
 473         msr_all_available |= MSR_FP;
 474 #endif
 475 #ifdef CONFIG_ALTIVEC
 476         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 477                 msr_all_available |= MSR_VEC;
 478 #endif
 479 #ifdef CONFIG_VSX
 480         if (cpu_has_feature(CPU_FTR_VSX))
 481                 msr_all_available |= MSR_VSX;
 482 #endif
 483 #ifdef CONFIG_SPE
 484         if (cpu_has_feature(CPU_FTR_SPE))
 485                 msr_all_available |= MSR_SPE;
 486 #endif
 487
 488         return 0;
 489 }
 490 early_initcall(init_msr_all_available);
 491
 492 void giveup_all(struct task_struct *tsk)
 493 {
 494         unsigned long usermsr;
 495
 496         if (!tsk->thread.regs)
 497                 return;
 498
 499         usermsr = tsk->thread.regs->msr;
 500
 501         if ((usermsr & msr_all_available) == 0)
 502                 return;
 503
 504         msr_check_and_set(msr_all_available);
 505         check_if_tm_restore_required(tsk);
 506
 507         WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
 508
 509 #ifdef CONFIG_PPC_FPU
 510         if (usermsr & MSR_FP)
 511                 __giveup_fpu(tsk);
 512 #endif
 513 #ifdef CONFIG_ALTIVEC
 514         if (usermsr & MSR_VEC)
 515                 __giveup_altivec(tsk);
 516 #endif
 517 #ifdef CONFIG_SPE
 518         if (usermsr & MSR_SPE)
 519                 __giveup_spe(tsk);
 520 #endif
 521
 522         msr_check_and_clear(msr_all_available);
 523 }
 524 EXPORT_SYMBOL(giveup_all);
 525
 526 void restore_math(struct pt_regs *regs)
 527 {
 528         unsigned long msr;
 529
 530         if (!msr_tm_active(regs->msr) &&
 531                 !current->thread.load_fp && !loadvec(current->thread))
 532                 return;
 533
 534         msr = regs->msr;
 535         msr_check_and_set(msr_all_available);
 536
 537         /*
 538          * Only reload if the bit is not set in the user MSR, the bit BEING set
 539          * indicates that the registers are hot
 540          */
 541         if ((!(msr & MSR_FP)) && restore_fp(current))
 542                 msr |= MSR_FP | current->thread.fpexc_mode;
 543
 544         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 545                 msr |= MSR_VEC;
 546
 547         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 548                         restore_vsx(current)) {
 549                 msr |= MSR_VSX;
 550         }
 551
 552         msr_check_and_clear(msr_all_available);
 553
 554         regs->msr = msr;
 555 }
 556
 557 void save_all(struct task_struct *tsk)
 558 {
 559         unsigned long usermsr;
 560
 561         if (!tsk->thread.regs)
 562                 return;
 563
 564         usermsr = tsk->thread.regs->msr;
 565
 566         if ((usermsr & msr_all_available) == 0)
 567                 return;
 568
 569         msr_check_and_set(msr_all_available);
 570
 571         WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
 572
 573         if (usermsr & MSR_FP)
 574                 save_fpu(tsk);
 575
 576         if (usermsr & MSR_VEC)
 577                 save_altivec(tsk);
 578
 579         if (usermsr & MSR_SPE)
 580                 __giveup_spe(tsk);
 581
 582         msr_check_and_clear(msr_all_available);
 583 }
 584
 585 void flush_all_to_thread(struct task_struct *tsk)
 586 {
 587         if (tsk->thread.regs) {
 588                 preempt_disable();
 589                 BUG_ON(tsk != current);
 590                 save_all(tsk);
 591
 592 #ifdef CONFIG_SPE
 593                 if (tsk->thread.regs->msr & MSR_SPE)
 594                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 595 #endif
 596
 597                 preempt_enable();
 598         }
 599 }
 600 EXPORT_SYMBOL(flush_all_to_thread);
 601
 602 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 603 void do_send_trap(struct pt_regs *regs, unsigned long address,
 604                   unsigned long error_code, int breakpt)
 605 {
 606         current->thread.trap_nr = TRAP_HWBKPT;
 607         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 608                         11, SIGSEGV) == NOTIFY_STOP)
 609                 return;
 610
 611         /* Deliver the signal to userspace */
 612         force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
 613                                     (void __user *)address);
 614 }
 615 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 616 void do_break (struct pt_regs *regs, unsigned long address,
 617                     unsigned long error_code)
 618 {
 619         siginfo_t info;
 620
 621         current->thread.trap_nr = TRAP_HWBKPT;
 622         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 623                         11, SIGSEGV) == NOTIFY_STOP)
 624                 return;
 625
 626         if (debugger_break_match(regs))
 627                 return;
 628
 629         /* Clear the breakpoint */
 630         hw_breakpoint_disable();
 631
 632         /* Deliver the signal to userspace */
 633         info.si_signo = SIGTRAP;
 634         info.si_errno = 0;
 635         info.si_code = TRAP_HWBKPT;
 636         info.si_addr = (void __user *)address;
 637         force_sig_info(SIGTRAP, &info, current);
 638 }
 639 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 640
 641 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 642
 643 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 644 /*
 645  * Set the debug registers back to their default "safe" values.
 646  */
 647 static void set_debug_reg_defaults(struct thread_struct *thread)
 648 {
 649         thread->debug.iac1 = thread->debug.iac2 = 0;
 650 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 651         thread->debug.iac3 = thread->debug.iac4 = 0;
 652 #endif
 653         thread->debug.dac1 = thread->debug.dac2 = 0;
 654 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 655         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 656 #endif
 657         thread->debug.dbcr0 = 0;
 658 #ifdef CONFIG_BOOKE
 659         /*
 660          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 661          */
 662         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 663                         DBCR1_IAC3US | DBCR1_IAC4US;
 664         /*
 665          * Force Data Address Compare User/Supervisor bits to be User-only
 666          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 667          */
 668         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 669 #else
 670         thread->debug.dbcr1 = 0;
 671 #endif
 672 }
 673
 674 static void prime_debug_regs(struct debug_reg *debug)
 675 {
 676         /*
 677          * We could have inherited MSR_DE from userspace, since
 678          * it doesn't get cleared on exception entry.  Make sure
 679          * MSR_DE is clear before we enable any debug events.
 680          */
 681         mtmsr(mfmsr() & ~MSR_DE);
 682
 683         mtspr(SPRN_IAC1, debug->iac1);
 684         mtspr(SPRN_IAC2, debug->iac2);
 685 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 686         mtspr(SPRN_IAC3, debug->iac3);
 687         mtspr(SPRN_IAC4, debug->iac4);
 688 #endif
 689         mtspr(SPRN_DAC1, debug->dac1);
 690         mtspr(SPRN_DAC2, debug->dac2);
 691 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 692         mtspr(SPRN_DVC1, debug->dvc1);
 693         mtspr(SPRN_DVC2, debug->dvc2);
 694 #endif
 695         mtspr(SPRN_DBCR0, debug->dbcr0);
 696         mtspr(SPRN_DBCR1, debug->dbcr1);
 697 #ifdef CONFIG_BOOKE
 698         mtspr(SPRN_DBCR2, debug->dbcr2);
 699 #endif
 700 }
 701 /*
 702  * Unless neither the old or new thread are making use of the
 703  * debug registers, set the debug registers from the values
 704  * stored in the new thread.
 705  */
 706 void switch_booke_debug_regs(struct debug_reg *new_debug)
 707 {
 708         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 709                 || (new_debug->dbcr0 & DBCR0_IDM))
 710                         prime_debug_regs(new_debug);
 711 }
 712 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 713 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 714 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 715 static void set_debug_reg_defaults(struct thread_struct *thread)
 716 {
 717         thread->hw_brk.address = 0;
 718         thread->hw_brk.type = 0;
 719         set_breakpoint(&thread->hw_brk);
 720 }
 721 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 722 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 723
 724 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 725 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 726 {
 727         mtspr(SPRN_DAC1, dabr);
 728 #ifdef CONFIG_PPC_47x
 729         isync();
 730 #endif
 731         return 0;
 732 }
 733 #elif defined(CONFIG_PPC_BOOK3S)
 734 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 735 {
 736         mtspr(SPRN_DABR, dabr);
 737         if (cpu_has_feature(CPU_FTR_DABRX))
 738                 mtspr(SPRN_DABRX, dabrx);
 739         return 0;
 740 }
 741 #elif defined(CONFIG_PPC_8xx)
 742 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 743 {
 744         unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
 745         unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
 746         unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
 747
 748         if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
 749                 lctrl1 |= 0xa0000;
 750         else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
 751                 lctrl1 |= 0xf0000;
 752         else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
 753                 lctrl2 = 0;
 754
 755         mtspr(SPRN_LCTRL2, 0);
 756         mtspr(SPRN_CMPE, addr);
 757         mtspr(SPRN_CMPF, addr + 4);
 758         mtspr(SPRN_LCTRL1, lctrl1);
 759         mtspr(SPRN_LCTRL2, lctrl2);
 760
 761         return 0;
 762 }
 763 #else
 764 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 765 {
 766         return -EINVAL;
 767 }
 768 #endif
 769
 770 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 771 {
 772         unsigned long dabr, dabrx;
 773
 774         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 775         dabrx = ((brk->type >> 3) & 0x7);
 776
 777         if (ppc_md.set_dabr)
 778                 return ppc_md.set_dabr(dabr, dabrx);
 779
 780         return __set_dabr(dabr, dabrx);
 781 }
 782
 783 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 784 {
 785         unsigned long dawr, dawrx, mrd;
 786
 787         dawr = brk->address;
 788
 789         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 790                                    << (63 - 58); //* read/write bits */
 791         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 792                                    << (63 - 59); //* translate */
 793         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 794                                    >> 3; //* PRIM bits */
 795         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 796            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 797            0b111111=64DW.
 798            brk->len is in bytes.
 799            This aligns up to double word size, shifts and does the bias.
 800         */
 801         mrd = ((brk->len + 7) >> 3) - 1;
 802         dawrx |= (mrd & 0x3f) << (63 - 53);
 803
 804         if (ppc_md.set_dawr)
 805                 return ppc_md.set_dawr(dawr, dawrx);
 806         mtspr(SPRN_DAWR, dawr);
 807         mtspr(SPRN_DAWRX, dawrx);
 808         return 0;
 809 }
 810
 811 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 812 {
 813         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 814
 815         if (cpu_has_feature(CPU_FTR_DAWR))
 816                 set_dawr(brk);
 817         else
 818                 set_dabr(brk);
 819 }
 820
 821 void set_breakpoint(struct arch_hw_breakpoint *brk)
 822 {
 823         preempt_disable();
 824         __set_breakpoint(brk);
 825         preempt_enable();
 826 }
 827
 828 #ifdef CONFIG_PPC64
 829 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 830 #endif
 831
 832 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 833                               struct arch_hw_breakpoint *b)
 834 {
 835         if (a->address != b->address)
 836                 return false;
 837         if (a->type != b->type)
 838                 return false;
 839         if (a->len != b->len)
 840                 return false;
 841         return true;
 842 }
 843
 844 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 845
 846 static inline bool tm_enabled(struct task_struct *tsk)
 847 {
 848         return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
 849 }
 850
 851 static void tm_reclaim_thread(struct thread_struct *thr,
 852                               struct thread_info *ti, uint8_t cause)
 853 {
 854         /*
 855          * Use the current MSR TM suspended bit to track if we have
 856          * checkpointed state outstanding.
 857          * On signal delivery, we'd normally reclaim the checkpointed
 858          * state to obtain stack pointer (see:get_tm_stackpointer()).
 859          * This will then directly return to userspace without going
 860          * through __switch_to(). However, if the stack frame is bad,
 861          * we need to exit this thread which calls __switch_to() which
 862          * will again attempt to reclaim the already saved tm state.
 863          * Hence we need to check that we've not already reclaimed
 864          * this state.
 865          * We do this using the current MSR, rather tracking it in
 866          * some specific thread_struct bit, as it has the additional
 867          * benefit of checking for a potential TM bad thing exception.
 868          */
 869         if (!MSR_TM_SUSPENDED(mfmsr()))
 870                 return;
 871
 872         giveup_all(container_of(thr, struct task_struct, thread));
 873
 874         tm_reclaim(thr, cause);
 875
 876         /*
 877          * If we are in a transaction and FP is off then we can't have
 878          * used FP inside that transaction. Hence the checkpointed
 879          * state is the same as the live state. We need to copy the
 880          * live state to the checkpointed state so that when the
 881          * transaction is restored, the checkpointed state is correct
 882          * and the aborted transaction sees the correct state. We use
 883          * ckpt_regs.msr here as that's what tm_reclaim will use to
 884          * determine if it's going to write the checkpointed state or
 885          * not. So either this will write the checkpointed registers,
 886          * or reclaim will. Similarly for VMX.
 887          */
 888         if ((thr->ckpt_regs.msr & MSR_FP) == 0)
 889                 memcpy(&thr->ckfp_state, &thr->fp_state,
 890                        sizeof(struct thread_fp_state));
 891         if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
 892                 memcpy(&thr->ckvr_state, &thr->vr_state,
 893                        sizeof(struct thread_vr_state));
 894 }
 895
 896 void tm_reclaim_current(uint8_t cause)
 897 {
 898         tm_enable();
 899         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 900 }
 901
 902 static inline void tm_reclaim_task(struct task_struct *tsk)
 903 {
 904         /* We have to work out if we're switching from/to a task that's in the
 905          * middle of a transaction.
 906          *
 907          * In switching we need to maintain a 2nd register state as
 908          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 909          * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
 910          * ckvr_state
 911          *
 912          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 913          */
 914         struct thread_struct *thr = &tsk->thread;
 915
 916         if (!thr->regs)
 917                 return;
 918
 919         if (!MSR_TM_ACTIVE(thr->regs->msr))
 920                 goto out_and_saveregs;
 921
 922         WARN_ON(tm_suspend_disabled);
 923
 924         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 925                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 926                  tsk->pid, thr->regs->nip,
 927                  thr->regs->ccr, thr->regs->msr,
 928                  thr->regs->trap);
 929
 930         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 931
 932         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 933                  tsk->pid);
 934
 935 out_and_saveregs:
 936         /* Always save the regs here, even if a transaction's not active.
 937          * This context-switches a thread's TM info SPRs.  We do it here to
 938          * be consistent with the restore path (in recheckpoint) which
 939          * cannot happen later in _switch().
 940          */
 941         tm_save_sprs(thr);
 942 }
 943
 944 extern void __tm_recheckpoint(struct thread_struct *thread);
 945
 946 void tm_recheckpoint(struct thread_struct *thread)
 947 {
 948         unsigned long flags;
 949
 950         if (!(thread->regs->msr & MSR_TM))
 951                 return;
 952
 953         /* We really can't be interrupted here as the TEXASR registers can't
 954          * change and later in the trecheckpoint code, we have a userspace R1.
 955          * So let's hard disable over this region.
 956          */
 957         local_irq_save(flags);
 958         hard_irq_disable();
 959
 960         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 961          * before the trecheckpoint and no explosion occurs.
 962          */
 963         tm_restore_sprs(thread);
 964
 965         __tm_recheckpoint(thread);
 966
 967         local_irq_restore(flags);
 968 }
 969
 970 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 971 {
 972         if (!cpu_has_feature(CPU_FTR_TM))
 973                 return;
 974
 975         /* Recheckpoint the registers of the thread we're about to switch to.
 976          *
 977          * If the task was using FP, we non-lazily reload both the original and
 978          * the speculative FP register states.  This is because the kernel
 979          * doesn't see if/when a TM rollback occurs, so if we take an FP
 980          * unavailable later, we are unable to determine which set of FP regs
 981          * need to be restored.
 982          */
 983         if (!tm_enabled(new))
 984                 return;
 985
 986         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 987                 tm_restore_sprs(&new->thread);
 988                 return;
 989         }
 990         /* Recheckpoint to restore original checkpointed register state. */
 991         TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
 992                  new->pid, new->thread.regs->msr);
 993
 994         tm_recheckpoint(&new->thread);
 995
 996         /*
 997          * The checkpointed state has been restored but the live state has
 998          * not, ensure all the math functionality is turned off to trigger
 999          * restore_math() to reload.
1000          */
1001         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1002
1003         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1004                  "(kernel msr 0x%lx)\n",
1005                  new->pid, mfmsr());
1006 }
1007
1008 static inline void __switch_to_tm(struct task_struct *prev,
1009                 struct task_struct *new)
1010 {
1011         if (cpu_has_feature(CPU_FTR_TM)) {
1012                 if (tm_enabled(prev) || tm_enabled(new))
1013                         tm_enable();
1014
1015                 if (tm_enabled(prev)) {
1016                         prev->thread.load_tm++;
1017                         tm_reclaim_task(prev);
1018                         if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1019                                 prev->thread.regs->msr &= ~MSR_TM;
1020                 }
1021
1022                 tm_recheckpoint_new_task(new);
1023         }
1024 }
1025
1026 /*
1027  * This is called if we are on the way out to userspace and the
1028  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1029  * FP and/or vector state and does so if necessary.
1030  * If userspace is inside a transaction (whether active or
1031  * suspended) and FP/VMX/VSX instructions have ever been enabled
1032  * inside that transaction, then we have to keep them enabled
1033  * and keep the FP/VMX/VSX state loaded while ever the transaction
1034  * continues.  The reason is that if we didn't, and subsequently
1035  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1036  * we don't know whether it's the same transaction, and thus we
1037  * don't know which of the checkpointed state and the transactional
1038  * state to use.
1039  */
1040 void restore_tm_state(struct pt_regs *regs)
1041 {
1042         unsigned long msr_diff;
1043
1044         /*
1045          * This is the only moment we should clear TIF_RESTORE_TM as
1046          * it is here that ckpt_regs.msr and pt_regs.msr become the same
1047          * again, anything else could lead to an incorrect ckpt_msr being
1048          * saved and therefore incorrect signal contexts.
1049          */
1050         clear_thread_flag(TIF_RESTORE_TM);
1051         if (!MSR_TM_ACTIVE(regs->msr))
1052                 return;
1053
1054         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1055         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1056
1057         /* Ensure that restore_math() will restore */
1058         if (msr_diff & MSR_FP)
1059                 current->thread.load_fp = 1;
1060 #ifdef CONFIG_ALTIVEC
1061         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1062                 current->thread.load_vec = 1;
1063 #endif
1064         restore_math(regs);
1065
1066         regs->msr |= msr_diff;
1067 }
1068
1069 #else
1070 #define tm_recheckpoint_new_task(new)
1071 #define __switch_to_tm(prev, new)
1072 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1073
1074 static inline void save_sprs(struct thread_struct *t)
1075 {
1076 #ifdef CONFIG_ALTIVEC
1077         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1078                 t->vrsave = mfspr(SPRN_VRSAVE);
1079 #endif
1080 #ifdef CONFIG_PPC_BOOK3S_64
1081         if (cpu_has_feature(CPU_FTR_DSCR))
1082                 t->dscr = mfspr(SPRN_DSCR);
1083
1084         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1085                 t->bescr = mfspr(SPRN_BESCR);
1086                 t->ebbhr = mfspr(SPRN_EBBHR);
1087                 t->ebbrr = mfspr(SPRN_EBBRR);
1088
1089                 t->fscr = mfspr(SPRN_FSCR);
1090
1091                 /*
1092                  * Note that the TAR is not available for use in the kernel.
1093                  * (To provide this, the TAR should be backed up/restored on
1094                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1095                  * this should be in pt_regs anyway (for debug).)
1096                  */
1097                 t->tar = mfspr(SPRN_TAR);
1098         }
1099 #endif
1100 }
1101
1102 static inline void restore_sprs(struct thread_struct *old_thread,
1103                                 struct thread_struct *new_thread)
1104 {
1105 #ifdef CONFIG_ALTIVEC
1106         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1107             old_thread->vrsave != new_thread->vrsave)
1108                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1109 #endif
1110 #ifdef CONFIG_PPC_BOOK3S_64
1111         if (cpu_has_feature(CPU_FTR_DSCR)) {
1112                 u64 dscr = get_paca()->dscr_default;
1113                 if (new_thread->dscr_inherit)
1114                         dscr = new_thread->dscr;
1115
1116                 if (old_thread->dscr != dscr)
1117                         mtspr(SPRN_DSCR, dscr);
1118         }
1119
1120         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1121                 if (old_thread->bescr != new_thread->bescr)
1122                         mtspr(SPRN_BESCR, new_thread->bescr);
1123                 if (old_thread->ebbhr != new_thread->ebbhr)
1124                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1125                 if (old_thread->ebbrr != new_thread->ebbrr)
1126                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1127
1128                 if (old_thread->fscr != new_thread->fscr)
1129                         mtspr(SPRN_FSCR, new_thread->fscr);
1130
1131                 if (old_thread->tar != new_thread->tar)
1132                         mtspr(SPRN_TAR, new_thread->tar);
1133         }
1134
1135         if (cpu_has_feature(CPU_FTR_ARCH_300) &&
1136             old_thread->tidr != new_thread->tidr)
1137                 mtspr(SPRN_TIDR, new_thread->tidr);
1138 #endif
1139 }
1140
1141 #ifdef CONFIG_PPC_BOOK3S_64
1142 #define CP_SIZE 128
1143 static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE)));
1144 #endif
1145
1146 struct task_struct *__switch_to(struct task_struct *prev,
1147         struct task_struct *new)
1148 {
1149         struct thread_struct *new_thread, *old_thread;
1150         struct task_struct *last;
1151 #ifdef CONFIG_PPC_BOOK3S_64
1152         struct ppc64_tlb_batch *batch;
1153 #endif
1154
1155         new_thread = &new->thread;
1156         old_thread = &current->thread;
1157
1158         WARN_ON(!irqs_disabled());
1159
1160 #ifdef CONFIG_PPC64
1161         /*
1162          * Collect processor utilization data per process
1163          */
1164         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1165                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1166                 long unsigned start_tb, current_tb;
1167                 start_tb = old_thread->start_tb;
1168                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1169                 old_thread->accum_tb += (current_tb - start_tb);
1170                 new_thread->start_tb = current_tb;
1171         }
1172 #endif /* CONFIG_PPC64 */
1173
1174 #ifdef CONFIG_PPC_BOOK3S_64
1175         batch = this_cpu_ptr(&ppc64_tlb_batch);
1176         if (batch->active) {
1177                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1178                 if (batch->index)
1179                         __flush_tlb_pending(batch);
1180                 batch->active = 0;
1181         }
1182 #endif /* CONFIG_PPC_BOOK3S_64 */
1183
1184 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1185         switch_booke_debug_regs(&new->thread.debug);
1186 #else
1187 /*
1188  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1189  * schedule DABR
1190  */
1191 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1192         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1193                 __set_breakpoint(&new->thread.hw_brk);
1194 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1195 #endif
1196
1197         /*
1198          * We need to save SPRs before treclaim/trecheckpoint as these will
1199          * change a number of them.
1200          */
1201         save_sprs(&prev->thread);
1202
1203         /* Save FPU, Altivec, VSX and SPE state */
1204         giveup_all(prev);
1205
1206         __switch_to_tm(prev, new);
1207
1208         if (!radix_enabled()) {
1209                 /*
1210                  * We can't take a PMU exception inside _switch() since there
1211                  * is a window where the kernel stack SLB and the kernel stack
1212                  * are out of sync. Hard disable here.
1213                  */
1214                 hard_irq_disable();
1215         }
1216
1217         /*
1218          * Call restore_sprs() before calling _switch(). If we move it after
1219          * _switch() then we miss out on calling it for new tasks. The reason
1220          * for this is we manually create a stack frame for new tasks that
1221          * directly returns through ret_from_fork() or
1222          * ret_from_kernel_thread(). See copy_thread() for details.
1223          */
1224         restore_sprs(old_thread, new_thread);
1225
1226         last = _switch(old_thread, new_thread);
1227
1228 #ifdef CONFIG_PPC_BOOK3S_64
1229         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1230                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1231                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1232                 batch->active = 1;
1233         }
1234
1235         if (current_thread_info()->task->thread.regs) {
1236                 restore_math(current_thread_info()->task->thread.regs);
1237
1238                 /*
1239                  * The copy-paste buffer can only store into foreign real
1240                  * addresses, so unprivileged processes can not see the
1241                  * data or use it in any way unless they have foreign real
1242                  * mappings. If the new process has the foreign real address
1243                  * mappings, we must issue a cp_abort to clear any state and
1244                  * prevent snooping, corruption or a covert channel.
1245                  *
1246                  * DD1 allows paste into normal system memory so we do an
1247                  * unpaired copy, rather than cp_abort, to clear the buffer,
1248                  * since cp_abort is quite expensive.
1249                  */
1250                 if (current_thread_info()->task->thread.used_vas) {
1251                         asm volatile(PPC_CP_ABORT);
1252                 } else if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
1253                         asm volatile(PPC_COPY(%0, %1)
1254                                         : : "r"(dummy_copy_buffer), "r"(0));
1255                 }
1256         }
1257 #endif /* CONFIG_PPC_BOOK3S_64 */
1258
1259         return last;
1260 }
1261
1262 static int instructions_to_print = 16;
1263
1264 static void show_instructions(struct pt_regs *regs)
1265 {
1266         int i;
1267         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1268                         sizeof(int));
1269
1270         printk("Instruction dump:");
1271
1272         for (i = 0; i < instructions_to_print; i++) {
1273                 int instr;
1274
1275                 if (!(i % 8))
1276                         pr_cont("\n");
1277
1278 #if !defined(CONFIG_BOOKE)
1279                 /* If executing with the IMMU off, adjust pc rather
1280                  * than print XXXXXXXX.
1281                  */
1282                 if (!(regs->msr & MSR_IR))
1283                         pc = (unsigned long)phys_to_virt(pc);
1284 #endif
1285
1286                 if (!__kernel_text_address(pc) ||
1287                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1288                         pr_cont("XXXXXXXX ");
1289                 } else {
1290                         if (regs->nip == pc)
1291                                 pr_cont("<%08x> ", instr);
1292                         else
1293                                 pr_cont("%08x ", instr);
1294                 }
1295
1296                 pc += sizeof(int);
1297         }
1298
1299         pr_cont("\n");
1300 }
1301
1302 struct regbit {
1303         unsigned long bit;
1304         const char *name;
1305 };
1306
1307 static struct regbit msr_bits[] = {
1308 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1309         {MSR_SF,        "SF"},
1310         {MSR_HV,        "HV"},
1311 #endif
1312         {MSR_VEC,       "VEC"},
1313         {MSR_VSX,       "VSX"},
1314 #ifdef CONFIG_BOOKE
1315         {MSR_CE,        "CE"},
1316 #endif
1317         {MSR_EE,        "EE"},
1318         {MSR_PR,        "PR"},
1319         {MSR_FP,        "FP"},
1320         {MSR_ME,        "ME"},
1321 #ifdef CONFIG_BOOKE
1322         {MSR_DE,        "DE"},
1323 #else
1324         {MSR_SE,        "SE"},
1325         {MSR_BE,        "BE"},
1326 #endif
1327         {MSR_IR,        "IR"},
1328         {MSR_DR,        "DR"},
1329         {MSR_PMM,       "PMM"},
1330 #ifndef CONFIG_BOOKE
1331         {MSR_RI,        "RI"},
1332         {MSR_LE,        "LE"},
1333 #endif
1334         {0,             NULL}
1335 };
1336
1337 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1338 {
1339         const char *s = "";
1340
1341         for (; bits->bit; ++bits)
1342                 if (val & bits->bit) {
1343                         pr_cont("%s%s", s, bits->name);
1344                         s = sep;
1345                 }
1346 }
1347
1348 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1349 static struct regbit msr_tm_bits[] = {
1350         {MSR_TS_T,      "T"},
1351         {MSR_TS_S,      "S"},
1352         {MSR_TM,        "E"},
1353         {0,             NULL}
1354 };
1355
1356 static void print_tm_bits(unsigned long val)
1357 {
1358 /*
1359  * This only prints something if at least one of the TM bit is set.
1360  * Inside the TM[], the output means:
1361  *   E: Enabled         (bit 32)
1362  *   S: Suspended       (bit 33)
1363  *   T: Transactional   (bit 34)
1364  */
1365         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1366                 pr_cont(",TM[");
1367                 print_bits(val, msr_tm_bits, "");
1368                 pr_cont("]");
1369         }
1370 }
1371 #else
1372 static void print_tm_bits(unsigned long val) {}
1373 #endif
1374
1375 static void print_msr_bits(unsigned long val)
1376 {
1377         pr_cont("<");
1378         print_bits(val, msr_bits, ",");
1379         print_tm_bits(val);
1380         pr_cont(">");
1381 }
1382
1383 #ifdef CONFIG_PPC64
1384 #define REG             "%016lx"
1385 #define REGS_PER_LINE   4
1386 #define LAST_VOLATILE   13
1387 #else
1388 #define REG             "%08lx"
1389 #define REGS_PER_LINE   8
1390 #define LAST_VOLATILE   12
1391 #endif
1392
1393 void show_regs(struct pt_regs * regs)
1394 {
1395         int i, trap;
1396
1397         show_regs_print_info(KERN_DEFAULT);
1398
1399         printk("NIP:  "REG" LR: "REG" CTR: "REG"\n",
1400                regs->nip, regs->link, regs->ctr);
1401         printk("REGS: %px TRAP: %04lx   %s  (%s)\n",
1402                regs, regs->trap, print_tainted(), init_utsname()->release);
1403         printk("MSR:  "REG" ", regs->msr);
1404         print_msr_bits(regs->msr);
1405         pr_cont("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1406         trap = TRAP(regs);
1407         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1408                 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1409         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1410 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1411                 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1412 #else
1413                 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1414 #endif
1415 #ifdef CONFIG_PPC64
1416         pr_cont("SOFTE: %ld ", regs->softe);
1417 #endif
1418 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1419         if (MSR_TM_ACTIVE(regs->msr))
1420                 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1421 #endif
1422
1423         for (i = 0;  i < 32;  i++) {
1424                 if ((i % REGS_PER_LINE) == 0)
1425                         pr_cont("\nGPR%02d: ", i);
1426                 pr_cont(REG " ", regs->gpr[i]);
1427                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1428                         break;
1429         }
1430         pr_cont("\n");
1431 #ifdef CONFIG_KALLSYMS
1432         /*
1433          * Lookup NIP late so we have the best change of getting the
1434          * above info out without failing
1435          */
1436         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1437         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1438 #endif
1439         show_stack(current, (unsigned long *) regs->gpr[1]);
1440         if (!user_mode(regs))
1441                 show_instructions(regs);
1442 }
1443
1444 void flush_thread(void)
1445 {
1446 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1447         flush_ptrace_hw_breakpoint(current);
1448 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1449         set_debug_reg_defaults(&current->thread);
1450 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1451 }
1452
1453 int set_thread_uses_vas(void)
1454 {
1455 #ifdef CONFIG_PPC_BOOK3S_64
1456         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1457                 return -EINVAL;
1458
1459         current->thread.used_vas = 1;
1460
1461         /*
1462          * Even a process that has no foreign real address mapping can use
1463          * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1464          * to clear any pending COPY and prevent a covert channel.
1465          *
1466          * __switch_to() will issue CP_ABORT on future context switches.
1467          */
1468         asm volatile(PPC_CP_ABORT);
1469
1470 #endif /* CONFIG_PPC_BOOK3S_64 */
1471         return 0;
1472 }
1473
1474 #ifdef CONFIG_PPC64
1475 static DEFINE_SPINLOCK(vas_thread_id_lock);
1476 static DEFINE_IDA(vas_thread_ida);
1477
1478 /*
1479  * We need to assign a unique thread id to each thread in a process.
1480  *
1481  * This thread id, referred to as TIDR, and separate from the Linux's tgid,
1482  * is intended to be used to direct an ASB_Notify from the hardware to the
1483  * thread, when a suitable event occurs in the system.
1484  *
1485  * One such event is a "paste" instruction in the context of Fast Thread
1486  * Wakeup (aka Core-to-core wake up in the Virtual Accelerator Switchboard
1487  * (VAS) in POWER9.
1488  *
1489  * To get a unique TIDR per process we could simply reuse task_pid_nr() but
1490  * the problem is that task_pid_nr() is not yet available copy_thread() is
1491  * called. Fixing that would require changing more intrusive arch-neutral
1492  * code in code path in copy_process()?.
1493  *
1494  * Further, to assign unique TIDRs within each process, we need an atomic
1495  * field (or an IDR) in task_struct, which again intrudes into the arch-
1496  * neutral code. So try to assign globally unique TIDRs for now.
1497  *
1498  * NOTE: TIDR 0 indicates that the thread does not need a TIDR value.
1499  *       For now, only threads that expect to be notified by the VAS
1500  *       hardware need a TIDR value and we assign values > 0 for those.
1501  */
1502 #define MAX_THREAD_CONTEXT      ((1 << 16) - 1)
1503 static int assign_thread_tidr(void)
1504 {
1505         int index;
1506         int err;
1507
1508 again:
1509         if (!ida_pre_get(&vas_thread_ida, GFP_KERNEL))
1510                 return -ENOMEM;
1511
1512         spin_lock(&vas_thread_id_lock);
1513         err = ida_get_new_above(&vas_thread_ida, 1, &index);
1514         spin_unlock(&vas_thread_id_lock);
1515
1516         if (err == -EAGAIN)
1517                 goto again;
1518         else if (err)
1519                 return err;
1520
1521         if (index > MAX_THREAD_CONTEXT) {
1522                 spin_lock(&vas_thread_id_lock);
1523                 ida_remove(&vas_thread_ida, index);
1524                 spin_unlock(&vas_thread_id_lock);
1525                 return -ENOMEM;
1526         }
1527
1528         return index;
1529 }
1530
1531 static void free_thread_tidr(int id)
1532 {
1533         spin_lock(&vas_thread_id_lock);
1534         ida_remove(&vas_thread_ida, id);
1535         spin_unlock(&vas_thread_id_lock);
1536 }
1537
1538 /*
1539  * Clear any TIDR value assigned to this thread.
1540  */
1541 void clear_thread_tidr(struct task_struct *t)
1542 {
1543         if (!t->thread.tidr)
1544                 return;
1545
1546         if (!cpu_has_feature(CPU_FTR_ARCH_300)) {
1547                 WARN_ON_ONCE(1);
1548                 return;
1549         }
1550
1551         mtspr(SPRN_TIDR, 0);
1552         free_thread_tidr(t->thread.tidr);
1553         t->thread.tidr = 0;
1554 }
1555
1556 void arch_release_task_struct(struct task_struct *t)
1557 {
1558         clear_thread_tidr(t);
1559 }
1560
1561 /*
1562  * Assign a unique TIDR (thread id) for task @t and set it in the thread
1563  * structure. For now, we only support setting TIDR for 'current' task.
1564  */
1565 int set_thread_tidr(struct task_struct *t)
1566 {
1567         int rc;
1568
1569         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1570                 return -EINVAL;
1571
1572         if (t != current)
1573                 return -EINVAL;
1574
1575         if (t->thread.tidr)
1576                 return 0;
1577
1578         rc = assign_thread_tidr();
1579         if (rc < 0)
1580                 return rc;
1581
1582         t->thread.tidr = rc;
1583         mtspr(SPRN_TIDR, t->thread.tidr);
1584
1585         return 0;
1586 }
1587
1588 #endif /* CONFIG_PPC64 */
1589
1590 void
1591 release_thread(struct task_struct *t)
1592 {
1593 }
1594
1595 /*
1596  * this gets called so that we can store coprocessor state into memory and
1597  * copy the current task into the new thread.
1598  */
1599 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1600 {
1601         flush_all_to_thread(src);
1602         /*
1603          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1604          * flush but it removes the checkpointed state from the current CPU and
1605          * transitions the CPU out of TM mode.  Hence we need to call
1606          * tm_recheckpoint_new_task() (on the same task) to restore the
1607          * checkpointed state back and the TM mode.
1608          *
1609          * Can't pass dst because it isn't ready. Doesn't matter, passing
1610          * dst is only important for __switch_to()
1611          */
1612         __switch_to_tm(src, src);
1613
1614         *dst = *src;
1615
1616         clear_task_ebb(dst);
1617
1618         return 0;
1619 }
1620
1621 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1622 {
1623 #ifdef CONFIG_PPC_BOOK3S_64
1624         unsigned long sp_vsid;
1625         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1626
1627         if (radix_enabled())
1628                 return;
1629
1630         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1631                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1632                         << SLB_VSID_SHIFT_1T;
1633         else
1634                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1635                         << SLB_VSID_SHIFT;
1636         sp_vsid |= SLB_VSID_KERNEL | llp;
1637         p->thread.ksp_vsid = sp_vsid;
1638 #endif
1639 }
1640
1641 /*
1642  * Copy a thread..
1643  */
1644
1645 /*
1646  * Copy architecture-specific thread state
1647  */
1648 int copy_thread(unsigned long clone_flags, unsigned long usp,
1649                 unsigned long kthread_arg, struct task_struct *p)
1650 {
1651         struct pt_regs *childregs, *kregs;
1652         extern void ret_from_fork(void);
1653         extern void ret_from_kernel_thread(void);
1654         void (*f)(void);
1655         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1656         struct thread_info *ti = task_thread_info(p);
1657
1658         klp_init_thread_info(ti);
1659
1660         /* Copy registers */
1661         sp -= sizeof(struct pt_regs);
1662         childregs = (struct pt_regs *) sp;
1663         if (unlikely(p->flags & PF_KTHREAD)) {
1664                 /* kernel thread */
1665                 memset(childregs, 0, sizeof(struct pt_regs));
1666                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1667                 /* function */
1668                 if (usp)
1669                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1670 #ifdef CONFIG_PPC64
1671                 clear_tsk_thread_flag(p, TIF_32BIT);
1672                 childregs->softe = 1;
1673 #endif
1674                 childregs->gpr[15] = kthread_arg;
1675                 p->thread.regs = NULL;  /* no user register state */
1676                 ti->flags |= _TIF_RESTOREALL;
1677                 f = ret_from_kernel_thread;
1678         } else {
1679                 /* user thread */
1680                 struct pt_regs *regs = current_pt_regs();
1681                 CHECK_FULL_REGS(regs);
1682                 *childregs = *regs;
1683                 if (usp)
1684                         childregs->gpr[1] = usp;
1685                 p->thread.regs = childregs;
1686                 childregs->gpr[3] = 0;  /* Result from fork() */
1687                 if (clone_flags & CLONE_SETTLS) {
1688 #ifdef CONFIG_PPC64
1689                         if (!is_32bit_task())
1690                                 childregs->gpr[13] = childregs->gpr[6];
1691                         else
1692 #endif
1693                                 childregs->gpr[2] = childregs->gpr[6];
1694                 }
1695
1696                 f = ret_from_fork;
1697         }
1698         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1699         sp -= STACK_FRAME_OVERHEAD;
1700
1701         /*
1702          * The way this works is that at some point in the future
1703          * some task will call _switch to switch to the new task.
1704          * That will pop off the stack frame created below and start
1705          * the new task running at ret_from_fork.  The new task will
1706          * do some house keeping and then return from the fork or clone
1707          * system call, using the stack frame created above.
1708          */
1709         ((unsigned long *)sp)[0] = 0;
1710         sp -= sizeof(struct pt_regs);
1711         kregs = (struct pt_regs *) sp;
1712         sp -= STACK_FRAME_OVERHEAD;
1713         p->thread.ksp = sp;
1714 #ifdef CONFIG_PPC32
1715         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1716                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1717 #endif
1718 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1719         p->thread.ptrace_bps[0] = NULL;
1720 #endif
1721
1722         p->thread.fp_save_area = NULL;
1723 #ifdef CONFIG_ALTIVEC
1724         p->thread.vr_save_area = NULL;
1725 #endif
1726
1727         setup_ksp_vsid(p, sp);
1728
1729 #ifdef CONFIG_PPC64
1730         if (cpu_has_feature(CPU_FTR_DSCR)) {
1731                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1732                 p->thread.dscr = mfspr(SPRN_DSCR);
1733         }
1734         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1735                 p->thread.ppr = INIT_PPR;
1736
1737         p->thread.tidr = 0;
1738 #endif
1739         kregs->nip = ppc_function_entry(f);
1740         return 0;
1741 }
1742
1743 /*
1744  * Set up a thread for executing a new program
1745  */
1746 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1747 {
1748 #ifdef CONFIG_PPC64
1749         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1750 #endif
1751
1752         /*
1753          * If we exec out of a kernel thread then thread.regs will not be
1754          * set.  Do it now.
1755          */
1756         if (!current->thread.regs) {
1757                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1758                 current->thread.regs = regs - 1;
1759         }
1760
1761 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1762         /*
1763          * Clear any transactional state, we're exec()ing. The cause is
1764          * not important as there will never be a recheckpoint so it's not
1765          * user visible.
1766          */
1767         if (MSR_TM_SUSPENDED(mfmsr()))
1768                 tm_reclaim_current(0);
1769 #endif
1770
1771         memset(regs->gpr, 0, sizeof(regs->gpr));
1772         regs->ctr = 0;
1773         regs->link = 0;
1774         regs->xer = 0;
1775         regs->ccr = 0;
1776         regs->gpr[1] = sp;
1777
1778         /*
1779          * We have just cleared all the nonvolatile GPRs, so make
1780          * FULL_REGS(regs) return true.  This is necessary to allow
1781          * ptrace to examine the thread immediately after exec.
1782          */
1783         regs->trap &= ~1UL;
1784
1785 #ifdef CONFIG_PPC32
1786         regs->mq = 0;
1787         regs->nip = start;
1788         regs->msr = MSR_USER;
1789 #else
1790         if (!is_32bit_task()) {
1791                 unsigned long entry;
1792
1793                 if (is_elf2_task()) {
1794                         /* Look ma, no function descriptors! */
1795                         entry = start;
1796
1797                         /*
1798                          * Ulrich says:
1799                          *   The latest iteration of the ABI requires that when
1800                          *   calling a function (at its global entry point),
1801                          *   the caller must ensure r12 holds the entry point
1802                          *   address (so that the function can quickly
1803                          *   establish addressability).
1804                          */
1805                         regs->gpr[12] = start;
1806                         /* Make sure that's restored on entry to userspace. */
1807                         set_thread_flag(TIF_RESTOREALL);
1808                 } else {
1809                         unsigned long toc;
1810
1811                         /* start is a relocated pointer to the function
1812                          * descriptor for the elf _start routine.  The first
1813                          * entry in the function descriptor is the entry
1814                          * address of _start and the second entry is the TOC
1815                          * value we need to use.
1816                          */
1817                         __get_user(entry, (unsigned long __user *)start);
1818                         __get_user(toc, (unsigned long __user *)start+1);
1819
1820                         /* Check whether the e_entry function descriptor entries
1821                          * need to be relocated before we can use them.
1822                          */
1823                         if (load_addr != 0) {
1824                                 entry += load_addr;
1825                                 toc   += load_addr;
1826                         }
1827                         regs->gpr[2] = toc;
1828                 }
1829                 regs->nip = entry;
1830                 regs->msr = MSR_USER64;
1831         } else {
1832                 regs->nip = start;
1833                 regs->gpr[2] = 0;
1834                 regs->msr = MSR_USER32;
1835         }
1836 #endif
1837 #ifdef CONFIG_VSX
1838         current->thread.used_vsr = 0;
1839 #endif
1840         current->thread.load_fp = 0;
1841         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1842         current->thread.fp_save_area = NULL;
1843 #ifdef CONFIG_ALTIVEC
1844         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1845         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1846         current->thread.vr_save_area = NULL;
1847         current->thread.vrsave = 0;
1848         current->thread.used_vr = 0;
1849         current->thread.load_vec = 0;
1850 #endif /* CONFIG_ALTIVEC */
1851 #ifdef CONFIG_SPE
1852         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1853         current->thread.acc = 0;
1854         current->thread.spefscr = 0;
1855         current->thread.used_spe = 0;
1856 #endif /* CONFIG_SPE */
1857 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1858         current->thread.tm_tfhar = 0;
1859         current->thread.tm_texasr = 0;
1860         current->thread.tm_tfiar = 0;
1861         current->thread.load_tm = 0;
1862 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1863 }
1864 EXPORT_SYMBOL(start_thread);
1865
1866 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1867                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1868
1869 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1870 {
1871         struct pt_regs *regs = tsk->thread.regs;
1872
1873         /* This is a bit hairy.  If we are an SPE enabled  processor
1874          * (have embedded fp) we store the IEEE exception enable flags in
1875          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1876          * mode (asyn, precise, disabled) for 'Classic' FP. */
1877         if (val & PR_FP_EXC_SW_ENABLE) {
1878 #ifdef CONFIG_SPE
1879                 if (cpu_has_feature(CPU_FTR_SPE)) {
1880                         /*
1881                          * When the sticky exception bits are set
1882                          * directly by userspace, it must call prctl
1883                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1884                          * in the existing prctl settings) or
1885                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1886                          * the bits being set).  <fenv.h> functions
1887                          * saving and restoring the whole
1888                          * floating-point environment need to do so
1889                          * anyway to restore the prctl settings from
1890                          * the saved environment.
1891                          */
1892                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1893                         tsk->thread.fpexc_mode = val &
1894                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1895                         return 0;
1896                 } else {
1897                         return -EINVAL;
1898                 }
1899 #else
1900                 return -EINVAL;
1901 #endif
1902         }
1903
1904         /* on a CONFIG_SPE this does not hurt us.  The bits that
1905          * __pack_fe01 use do not overlap with bits used for
1906          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1907          * on CONFIG_SPE implementations are reserved so writing to
1908          * them does not change anything */
1909         if (val > PR_FP_EXC_PRECISE)
1910                 return -EINVAL;
1911         tsk->thread.fpexc_mode = __pack_fe01(val);
1912         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1913                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1914                         | tsk->thread.fpexc_mode;
1915         return 0;
1916 }
1917
1918 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1919 {
1920         unsigned int val;
1921
1922         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1923 #ifdef CONFIG_SPE
1924                 if (cpu_has_feature(CPU_FTR_SPE)) {
1925                         /*
1926                          * When the sticky exception bits are set
1927                          * directly by userspace, it must call prctl
1928                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1929                          * in the existing prctl settings) or
1930                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1931                          * the bits being set).  <fenv.h> functions
1932                          * saving and restoring the whole
1933                          * floating-point environment need to do so
1934                          * anyway to restore the prctl settings from
1935                          * the saved environment.
1936                          */
1937                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1938                         val = tsk->thread.fpexc_mode;
1939                 } else
1940                         return -EINVAL;
1941 #else
1942                 return -EINVAL;
1943 #endif
1944         else
1945                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1946         return put_user(val, (unsigned int __user *) adr);
1947 }
1948
1949 int set_endian(struct task_struct *tsk, unsigned int val)
1950 {
1951         struct pt_regs *regs = tsk->thread.regs;
1952
1953         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1954             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1955                 return -EINVAL;
1956
1957         if (regs == NULL)
1958                 return -EINVAL;
1959
1960         if (val == PR_ENDIAN_BIG)
1961                 regs->msr &= ~MSR_LE;
1962         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1963                 regs->msr |= MSR_LE;
1964         else
1965                 return -EINVAL;
1966
1967         return 0;
1968 }
1969
1970 int get_endian(struct task_struct *tsk, unsigned long adr)
1971 {
1972         struct pt_regs *regs = tsk->thread.regs;
1973         unsigned int val;
1974
1975         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1976             !cpu_has_feature(CPU_FTR_REAL_LE))
1977                 return -EINVAL;
1978
1979         if (regs == NULL)
1980                 return -EINVAL;
1981
1982         if (regs->msr & MSR_LE) {
1983                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1984                         val = PR_ENDIAN_LITTLE;
1985                 else
1986                         val = PR_ENDIAN_PPC_LITTLE;
1987         } else
1988                 val = PR_ENDIAN_BIG;
1989
1990         return put_user(val, (unsigned int __user *)adr);
1991 }
1992
1993 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1994 {
1995         tsk->thread.align_ctl = val;
1996         return 0;
1997 }
1998
1999 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
2000 {
2001         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
2002 }
2003
2004 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
2005                                   unsigned long nbytes)
2006 {
2007         unsigned long stack_page;
2008         unsigned long cpu = task_cpu(p);
2009
2010         /*
2011          * Avoid crashing if the stack has overflowed and corrupted
2012          * task_cpu(p), which is in the thread_info struct.
2013          */
2014         if (cpu < NR_CPUS && cpu_possible(cpu)) {
2015                 stack_page = (unsigned long) hardirq_ctx[cpu];
2016                 if (sp >= stack_page + sizeof(struct thread_struct)
2017                     && sp <= stack_page + THREAD_SIZE - nbytes)
2018                         return 1;
2019
2020                 stack_page = (unsigned long) softirq_ctx[cpu];
2021                 if (sp >= stack_page + sizeof(struct thread_struct)
2022                     && sp <= stack_page + THREAD_SIZE - nbytes)
2023                         return 1;
2024         }
2025         return 0;
2026 }
2027
2028 int validate_sp(unsigned long sp, struct task_struct *p,
2029                        unsigned long nbytes)
2030 {
2031         unsigned long stack_page = (unsigned long)task_stack_page(p);
2032
2033         if (sp >= stack_page + sizeof(struct thread_struct)
2034             && sp <= stack_page + THREAD_SIZE - nbytes)
2035                 return 1;
2036
2037         return valid_irq_stack(sp, p, nbytes);
2038 }
2039
2040 EXPORT_SYMBOL(validate_sp);
2041
2042 unsigned long get_wchan(struct task_struct *p)
2043 {
2044         unsigned long ip, sp;
2045         int count = 0;
2046
2047         if (!p || p == current || p->state == TASK_RUNNING)
2048                 return 0;
2049
2050         sp = p->thread.ksp;
2051         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2052                 return 0;
2053
2054         do {
2055                 sp = *(unsigned long *)sp;
2056                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2057                     p->state == TASK_RUNNING)
2058                         return 0;
2059                 if (count > 0) {
2060                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2061                         if (!in_sched_functions(ip))
2062                                 return ip;
2063                 }
2064         } while (count++ < 16);
2065         return 0;
2066 }
2067
2068 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2069
2070 void show_stack(struct task_struct *tsk, unsigned long *stack)
2071 {
2072         unsigned long sp, ip, lr, newsp;
2073         int count = 0;
2074         int firstframe = 1;
2075 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2076         int curr_frame = current->curr_ret_stack;
2077         extern void return_to_handler(void);
2078         unsigned long rth = (unsigned long)return_to_handler;
2079 #endif
2080
2081         sp = (unsigned long) stack;
2082         if (tsk == NULL)
2083                 tsk = current;
2084         if (sp == 0) {
2085                 if (tsk == current)
2086                         sp = current_stack_pointer();
2087                 else
2088                         sp = tsk->thread.ksp;
2089         }
2090
2091         lr = 0;
2092         printk("Call Trace:\n");
2093         do {
2094                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2095                         return;
2096
2097                 stack = (unsigned long *) sp;
2098                 newsp = stack[0];
2099                 ip = stack[STACK_FRAME_LR_SAVE];
2100                 if (!firstframe || ip != lr) {
2101                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2102 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2103                         if ((ip == rth) && curr_frame >= 0) {
2104                                 pr_cont(" (%pS)",
2105                                        (void *)current->ret_stack[curr_frame].ret);
2106                                 curr_frame--;
2107                         }
2108 #endif
2109                         if (firstframe)
2110                                 pr_cont(" (unreliable)");
2111                         pr_cont("\n");
2112                 }
2113                 firstframe = 0;
2114
2115                 /*
2116                  * See if this is an exception frame.
2117                  * We look for the "regshere" marker in the current frame.
2118                  */
2119                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2120                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2121                         struct pt_regs *regs = (struct pt_regs *)
2122                                 (sp + STACK_FRAME_OVERHEAD);
2123                         lr = regs->link;
2124                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
2125                                regs->trap, (void *)regs->nip, (void *)lr);
2126                         firstframe = 1;
2127                 }
2128
2129                 sp = newsp;
2130         } while (count++ < kstack_depth_to_print);
2131 }
2132
2133 #ifdef CONFIG_PPC64
2134 /* Called with hard IRQs off */
2135 void notrace __ppc64_runlatch_on(void)
2136 {
2137         struct thread_info *ti = current_thread_info();
2138
2139         if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2140                 /*
2141                  * Least significant bit (RUN) is the only writable bit of
2142                  * the CTRL register, so we can avoid mfspr. 2.06 is not the
2143                  * earliest ISA where this is the case, but it's convenient.
2144                  */
2145                 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2146         } else {
2147                 unsigned long ctrl;
2148
2149                 /*
2150                  * Some architectures (e.g., Cell) have writable fields other
2151                  * than RUN, so do the read-modify-write.
2152                  */
2153                 ctrl = mfspr(SPRN_CTRLF);
2154                 ctrl |= CTRL_RUNLATCH;
2155                 mtspr(SPRN_CTRLT, ctrl);
2156         }
2157
2158         ti->local_flags |= _TLF_RUNLATCH;
2159 }
2160
2161 /* Called with hard IRQs off */
2162 void notrace __ppc64_runlatch_off(void)
2163 {
2164         struct thread_info *ti = current_thread_info();
2165
2166         ti->local_flags &= ~_TLF_RUNLATCH;
2167
2168         if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2169                 mtspr(SPRN_CTRLT, 0);
2170         } else {
2171                 unsigned long ctrl;
2172
2173                 ctrl = mfspr(SPRN_CTRLF);
2174                 ctrl &= ~CTRL_RUNLATCH;
2175                 mtspr(SPRN_CTRLT, ctrl);
2176         }
2177 }
2178 #endif /* CONFIG_PPC64 */
2179
2180 unsigned long arch_align_stack(unsigned long sp)
2181 {
2182         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2183                 sp -= get_random_int() & ~PAGE_MASK;
2184         return sp & ~0xf;
2185 }
2186
2187 static inline unsigned long brk_rnd(void)
2188 {
2189         unsigned long rnd = 0;
2190
2191         /* 8MB for 32bit, 1GB for 64bit */
2192         if (is_32bit_task())
2193                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2194         else
2195                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2196
2197         return rnd << PAGE_SHIFT;
2198 }
2199
2200 unsigned long arch_randomize_brk(struct mm_struct *mm)
2201 {
2202         unsigned long base = mm->brk;
2203         unsigned long ret;
2204
2205 #ifdef CONFIG_PPC_BOOK3S_64
2206         /*
2207          * If we are using 1TB segments and we are allowed to randomise
2208          * the heap, we can put it above 1TB so it is backed by a 1TB
2209          * segment. Otherwise the heap will be in the bottom 1TB
2210          * which always uses 256MB segments and this may result in a
2211          * performance penalty. We don't need to worry about radix. For
2212          * radix, mmu_highuser_ssize remains unchanged from 256MB.
2213          */
2214         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2215                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2216 #endif
2217
2218         ret = PAGE_ALIGN(base + brk_rnd());
2219
2220         if (ret < mm->brk)
2221                 return mm->brk;
2222
2223         return ret;
2224 }
2225