2 * Machine check exception handling CPU-side for power7 and power8
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright 2013 IBM Corporation
19 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
23 #define pr_fmt(fmt) "mce_power: " fmt
25 #include <linux/types.h>
26 #include <linux/ptrace.h>
29 #include <asm/machdep.h>
30 #include <asm/pgtable.h>
31 #include <asm/pte-walk.h>
32 #include <asm/sstep.h>
33 #include <asm/exception-64s.h>
36 * Convert an address related to an mm to a PFN. NOTE: we are in real
37 * mode, we could potentially race with page table updates.
39 static unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr)
50 local_irq_save(flags);
51 if (mm == current->mm)
52 ptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);
54 ptep = find_init_mm_pte(addr, NULL);
55 local_irq_restore(flags);
56 if (!ptep || pte_special(*ptep))
58 return pte_pfn(*ptep);
61 /* flush SLBs and reload */
62 #ifdef CONFIG_PPC_BOOK3S_64
63 static void flush_and_reload_slb(void)
65 struct slb_shadow *slb;
68 /* Invalidate all SLBs */
69 asm volatile("slbmte %0,%0; slbia" : : "r" (0));
71 #ifdef CONFIG_KVM_BOOK3S_HANDLER
73 * If machine check is hit when in guest or in transition, we will
74 * only flush the SLBs and continue.
76 if (get_paca()->kvm_hstate.in_guest)
80 /* For host kernel, reload the SLBs from shadow SLB buffer. */
81 slb = get_slb_shadow();
85 n = min_t(u32, be32_to_cpu(slb->persistent), SLB_MIN_SIZE);
87 /* Load up the SLB entries from shadow SLB */
88 for (i = 0; i < n; i++) {
89 unsigned long rb = be64_to_cpu(slb->save_area[i].esid);
90 unsigned long rs = be64_to_cpu(slb->save_area[i].vsid);
92 rb = (rb & ~0xFFFul) | i;
93 asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
98 static void flush_erat(void)
100 asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
103 #define MCE_FLUSH_SLB 1
104 #define MCE_FLUSH_TLB 2
105 #define MCE_FLUSH_ERAT 3
107 static int mce_flush(int what)
109 #ifdef CONFIG_PPC_BOOK3S_64
110 if (what == MCE_FLUSH_SLB) {
111 flush_and_reload_slb();
115 if (what == MCE_FLUSH_ERAT) {
119 if (what == MCE_FLUSH_TLB) {
127 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42))
129 struct mce_ierror_table {
130 unsigned long srr1_mask;
131 unsigned long srr1_value;
132 bool nip_valid; /* nip is a valid indicator of faulting address */
133 unsigned int error_type;
134 unsigned int error_subtype;
135 unsigned int initiator;
136 unsigned int severity;
139 static const struct mce_ierror_table mce_p7_ierror_table[] = {
140 { 0x00000000001c0000, 0x0000000000040000, true,
141 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH,
142 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
143 { 0x00000000001c0000, 0x0000000000080000, true,
144 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY,
145 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
146 { 0x00000000001c0000, 0x00000000000c0000, true,
147 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT,
148 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
149 { 0x00000000001c0000, 0x0000000000100000, true,
150 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
151 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
152 { 0x00000000001c0000, 0x0000000000140000, true,
153 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT,
154 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
155 { 0x00000000001c0000, 0x0000000000180000, true,
156 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH,
157 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
158 { 0x00000000001c0000, 0x00000000001c0000, true,
159 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH,
160 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
161 { 0, 0, 0, 0, 0, 0 } };
163 static const struct mce_ierror_table mce_p8_ierror_table[] = {
164 { 0x00000000081c0000, 0x0000000000040000, true,
165 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH,
166 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
167 { 0x00000000081c0000, 0x0000000000080000, true,
168 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY,
169 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
170 { 0x00000000081c0000, 0x00000000000c0000, true,
171 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT,
172 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
173 { 0x00000000081c0000, 0x0000000000100000, true,
174 MCE_ERROR_TYPE_ERAT,MCE_ERAT_ERROR_MULTIHIT,
175 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
176 { 0x00000000081c0000, 0x0000000000140000, true,
177 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT,
178 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
179 { 0x00000000081c0000, 0x0000000000180000, true,
180 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH,
181 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
182 { 0x00000000081c0000, 0x00000000001c0000, true,
183 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH,
184 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
185 { 0x00000000081c0000, 0x0000000008000000, true,
186 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_IFETCH_TIMEOUT,
187 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
188 { 0x00000000081c0000, 0x0000000008040000, true,
189 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
190 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
191 { 0, 0, 0, 0, 0, 0 } };
193 static const struct mce_ierror_table mce_p9_ierror_table[] = {
194 { 0x00000000081c0000, 0x0000000000040000, true,
195 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH,
196 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
197 { 0x00000000081c0000, 0x0000000000080000, true,
198 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY,
199 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
200 { 0x00000000081c0000, 0x00000000000c0000, true,
201 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT,
202 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
203 { 0x00000000081c0000, 0x0000000000100000, true,
204 MCE_ERROR_TYPE_ERAT,MCE_ERAT_ERROR_MULTIHIT,
205 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
206 { 0x00000000081c0000, 0x0000000000140000, true,
207 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT,
208 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
209 { 0x00000000081c0000, 0x0000000000180000, true,
210 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH,
211 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
212 { 0x00000000081c0000, 0x00000000001c0000, true,
213 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN,
214 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
215 { 0x00000000081c0000, 0x0000000008000000, true,
216 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_IFETCH_TIMEOUT,
217 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
218 { 0x00000000081c0000, 0x0000000008040000, true,
219 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
220 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
221 { 0x00000000081c0000, 0x00000000080c0000, true,
222 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH,
223 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
224 { 0x00000000081c0000, 0x0000000008100000, true,
225 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH,
226 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
227 { 0x00000000081c0000, 0x0000000008140000, false,
228 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE,
229 MCE_INITIATOR_CPU, MCE_SEV_FATAL, }, /* ASYNC is fatal */
230 { 0x00000000081c0000, 0x0000000008180000, false,
231 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_STORE_TIMEOUT,
232 MCE_INITIATOR_CPU, MCE_SEV_FATAL, }, /* ASYNC is fatal */
233 { 0x00000000081c0000, 0x00000000081c0000, true,
234 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN,
235 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
236 { 0, 0, 0, 0, 0, 0 } };
238 struct mce_derror_table {
239 unsigned long dsisr_value;
240 bool dar_valid; /* dar is a valid indicator of faulting address */
241 unsigned int error_type;
242 unsigned int error_subtype;
243 unsigned int initiator;
244 unsigned int severity;
247 static const struct mce_derror_table mce_p7_derror_table[] = {
249 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE,
250 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
252 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
253 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
255 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT,
256 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
258 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT,
259 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
261 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY,
262 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
264 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT,
265 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
267 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
268 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
269 { 0, false, 0, 0, 0, 0 } };
271 static const struct mce_derror_table mce_p8_derror_table[] = {
273 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE,
274 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
276 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
277 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
279 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT,
280 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
282 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
283 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
285 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT,
286 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
288 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT,
289 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
291 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, /* SECONDARY ERAT */
292 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
294 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY,
295 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
297 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT,
298 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
299 { 0, false, 0, 0, 0, 0 } };
301 static const struct mce_derror_table mce_p9_derror_table[] = {
303 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE,
304 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
306 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
307 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
309 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT,
310 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
312 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
313 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
315 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT,
316 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
318 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT,
319 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
321 MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE,
322 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
324 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY,
325 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
327 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT,
328 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
330 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD,
331 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
333 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
334 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
336 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN,
337 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
339 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN,
340 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },
341 { 0, false, 0, 0, 0, 0 } };
343 static int mce_find_instr_ea_and_pfn(struct pt_regs *regs, uint64_t *addr,
347 * Carefully look at the NIP to determine
348 * the instruction to analyse. Reading the NIP
349 * in real-mode is tricky and can lead to recursive
353 unsigned long pfn, instr_addr;
354 struct instruction_op op;
355 struct pt_regs tmp = *regs;
357 pfn = addr_to_pfn(regs, regs->nip);
358 if (pfn != ULONG_MAX) {
359 instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
360 instr = *(unsigned int *)(instr_addr);
361 if (!analyse_instr(&op, &tmp, instr)) {
362 pfn = addr_to_pfn(regs, op.ea);
364 *phys_addr = (pfn << PAGE_SHIFT);
368 * analyse_instr() might fail if the instruction
369 * is not a load/store, although this is unexpected
370 * for load/store errors or if we got the NIP
378 static int mce_handle_ierror(struct pt_regs *regs,
379 const struct mce_ierror_table table[],
380 struct mce_error_info *mce_err, uint64_t *addr,
383 uint64_t srr1 = regs->msr;
389 for (i = 0; table[i].srr1_mask; i++) {
390 if ((srr1 & table[i].srr1_mask) != table[i].srr1_value)
393 /* attempt to correct the error */
394 switch (table[i].error_type) {
395 case MCE_ERROR_TYPE_SLB:
396 handled = mce_flush(MCE_FLUSH_SLB);
398 case MCE_ERROR_TYPE_ERAT:
399 handled = mce_flush(MCE_FLUSH_ERAT);
401 case MCE_ERROR_TYPE_TLB:
402 handled = mce_flush(MCE_FLUSH_TLB);
406 /* now fill in mce_error_info */
407 mce_err->error_type = table[i].error_type;
408 switch (table[i].error_type) {
409 case MCE_ERROR_TYPE_UE:
410 mce_err->u.ue_error_type = table[i].error_subtype;
412 case MCE_ERROR_TYPE_SLB:
413 mce_err->u.slb_error_type = table[i].error_subtype;
415 case MCE_ERROR_TYPE_ERAT:
416 mce_err->u.erat_error_type = table[i].error_subtype;
418 case MCE_ERROR_TYPE_TLB:
419 mce_err->u.tlb_error_type = table[i].error_subtype;
421 case MCE_ERROR_TYPE_USER:
422 mce_err->u.user_error_type = table[i].error_subtype;
424 case MCE_ERROR_TYPE_RA:
425 mce_err->u.ra_error_type = table[i].error_subtype;
427 case MCE_ERROR_TYPE_LINK:
428 mce_err->u.link_error_type = table[i].error_subtype;
431 mce_err->severity = table[i].severity;
432 mce_err->initiator = table[i].initiator;
433 if (table[i].nip_valid) {
435 if (mce_err->severity == MCE_SEV_ERROR_SYNC &&
436 table[i].error_type == MCE_ERROR_TYPE_UE) {
439 if (get_paca()->in_mce < MAX_MCE_DEPTH) {
440 pfn = addr_to_pfn(regs, regs->nip);
441 if (pfn != ULONG_MAX) {
451 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
452 mce_err->severity = MCE_SEV_ERROR_SYNC;
453 mce_err->initiator = MCE_INITIATOR_CPU;
458 static int mce_handle_derror(struct pt_regs *regs,
459 const struct mce_derror_table table[],
460 struct mce_error_info *mce_err, uint64_t *addr,
463 uint64_t dsisr = regs->dsisr;
470 for (i = 0; table[i].dsisr_value; i++) {
471 if (!(dsisr & table[i].dsisr_value))
474 /* attempt to correct the error */
475 switch (table[i].error_type) {
476 case MCE_ERROR_TYPE_SLB:
477 if (mce_flush(MCE_FLUSH_SLB))
480 case MCE_ERROR_TYPE_ERAT:
481 if (mce_flush(MCE_FLUSH_ERAT))
484 case MCE_ERROR_TYPE_TLB:
485 if (mce_flush(MCE_FLUSH_TLB))
491 * Attempt to handle multiple conditions, but only return
492 * one. Ensure uncorrectable errors are first in the table
498 /* now fill in mce_error_info */
499 mce_err->error_type = table[i].error_type;
500 switch (table[i].error_type) {
501 case MCE_ERROR_TYPE_UE:
502 mce_err->u.ue_error_type = table[i].error_subtype;
504 case MCE_ERROR_TYPE_SLB:
505 mce_err->u.slb_error_type = table[i].error_subtype;
507 case MCE_ERROR_TYPE_ERAT:
508 mce_err->u.erat_error_type = table[i].error_subtype;
510 case MCE_ERROR_TYPE_TLB:
511 mce_err->u.tlb_error_type = table[i].error_subtype;
513 case MCE_ERROR_TYPE_USER:
514 mce_err->u.user_error_type = table[i].error_subtype;
516 case MCE_ERROR_TYPE_RA:
517 mce_err->u.ra_error_type = table[i].error_subtype;
519 case MCE_ERROR_TYPE_LINK:
520 mce_err->u.link_error_type = table[i].error_subtype;
523 mce_err->severity = table[i].severity;
524 mce_err->initiator = table[i].initiator;
525 if (table[i].dar_valid)
527 else if (mce_err->severity == MCE_SEV_ERROR_SYNC &&
528 table[i].error_type == MCE_ERROR_TYPE_UE) {
530 * We do a maximum of 4 nested MCE calls, see
531 * kernel/exception-64s.h
533 if (get_paca()->in_mce < MAX_MCE_DEPTH)
534 mce_find_instr_ea_and_pfn(regs, addr, phys_addr);
542 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
543 mce_err->severity = MCE_SEV_ERROR_SYNC;
544 mce_err->initiator = MCE_INITIATOR_CPU;
549 static long mce_handle_ue_error(struct pt_regs *regs)
554 * On specific SCOM read via MMIO we may get a machine check
555 * exception with SRR0 pointing inside opal. If that is the
556 * case OPAL may have recovery address to re-read SCOM data in
557 * different way and hence we can recover from this MC.
560 if (ppc_md.mce_check_early_recovery) {
561 if (ppc_md.mce_check_early_recovery(regs))
567 static long mce_handle_error(struct pt_regs *regs,
568 const struct mce_derror_table dtable[],
569 const struct mce_ierror_table itable[])
571 struct mce_error_info mce_err = { 0 };
572 uint64_t addr, phys_addr = ULONG_MAX;
573 uint64_t srr1 = regs->msr;
576 if (SRR1_MC_LOADSTORE(srr1))
577 handled = mce_handle_derror(regs, dtable, &mce_err, &addr,
580 handled = mce_handle_ierror(regs, itable, &mce_err, &addr,
583 if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE)
584 handled = mce_handle_ue_error(regs);
586 save_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr);
591 long __machine_check_early_realmode_p7(struct pt_regs *regs)
593 /* P7 DD1 leaves top bits of DSISR undefined */
594 regs->dsisr &= 0x0000ffff;
596 return mce_handle_error(regs, mce_p7_derror_table, mce_p7_ierror_table);
599 long __machine_check_early_realmode_p8(struct pt_regs *regs)
601 return mce_handle_error(regs, mce_p8_derror_table, mce_p8_ierror_table);
604 long __machine_check_early_realmode_p9(struct pt_regs *regs)
607 * On POWER9 DD2.1 and below, it's possible to get a machine check
608 * caused by a paste instruction where only DSISR bit 25 is set. This
609 * will result in the MCE handler seeing an unknown event and the kernel
610 * crashing. An MCE that occurs like this is spurious, so we don't need
611 * to do anything in terms of servicing it. If there is something that
612 * needs to be serviced, the CPU will raise the MCE again with the
613 * correct DSISR so that it can be serviced properly. So detect this
614 * case and mark it as handled.
616 if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000)
619 return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table);