arch/powerpc/kernel/head_booke.h

   1 #ifndef __HEAD_BOOKE_H__
   2 #define __HEAD_BOOKE_H__
   3
   4 /*
   5  * Macros used for common Book-e exception handling
   6  */
   7
   8 #define SET_IVOR(vector_number, vector_label)           \
   9                 li      r26,vector_label@l;             \
  10                 mtspr   SPRN_IVOR##vector_number,r26;   \
  11                 sync
  12
  13 #if (THREAD_SHIFT < 15)
  14 #define ALLOC_STACK_FRAME(reg, val)                     \
  15         addi reg,reg,val
  16 #else
  17 #define ALLOC_STACK_FRAME(reg, val)                     \
  18         addis   reg,reg,val@ha;                         \
  19         addi    reg,reg,val@l
  20 #endif
  21
  22 #define NORMAL_EXCEPTION_PROLOG                                              \
  23         mtspr   SPRN_SPRG0,r10;         /* save two registers to work with */\
  24         mtspr   SPRN_SPRG1,r11;                                              \
  25         mtspr   SPRN_SPRG4W,r1;                                              \
  26         mfcr    r10;                    /* save CR in r10 for now          */\
  27         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
  28         andi.   r11,r11,MSR_PR;                                              \
  29         beq     1f;                                                          \
  30         mfspr   r1,SPRN_SPRG3;          /* if from user, start at top of   */\
  31         lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
  32         ALLOC_STACK_FRAME(r1, THREAD_SIZE);                                  \
  33 1:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
  34         mr      r11,r1;                                                      \
  35         stw     r10,_CCR(r11);          /* save various registers          */\
  36         stw     r12,GPR12(r11);                                              \
  37         stw     r9,GPR9(r11);                                                \
  38         mfspr   r10,SPRN_SPRG0;                                              \
  39         stw     r10,GPR10(r11);                                              \
  40         mfspr   r12,SPRN_SPRG1;                                              \
  41         stw     r12,GPR11(r11);                                              \
  42         mflr    r10;                                                         \
  43         stw     r10,_LINK(r11);                                              \
  44         mfspr   r10,SPRN_SPRG4R;                                             \
  45         mfspr   r12,SPRN_SRR0;                                               \
  46         stw     r10,GPR1(r11);                                               \
  47         mfspr   r9,SPRN_SRR1;                                                \
  48         stw     r10,0(r11);                                                  \
  49         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
  50         stw     r0,GPR0(r11);                                                \
  51         SAVE_4GPRS(3, r11);                                                  \
  52         SAVE_2GPRS(7, r11)
  53
  54 /* To handle the additional exception priority levels on 40x and Book-E
  55  * processors we allocate a stack per additional priority level.
  56  *
  57  * On 40x critical is the only additional level
  58  * On 44x/e500 we have critical and machine check
  59  * On e200 we have critical and debug (machine check occurs via critical)
  60  *
  61  * Additionally we reserve a SPRG for each priority level so we can free up a
  62  * GPR to use as the base for indirect access to the exception stacks.  This
  63  * is necessary since the MMU is always on, for Book-E parts, and the stacks
  64  * are offset from KERNELBASE.
  65  *
  66  * There is some space optimization to be had here if desired.  However
  67  * to allow for a common kernel with support for debug exceptions either
  68  * going to critical or their own debug level we aren't currently
  69  * providing configurations that micro-optimize space usage.
  70  */
  71
  72 /* CRIT_SPRG only used in critical exception handling */
  73 #define CRIT_SPRG       SPRN_SPRG2
  74 /* MCHECK_SPRG only used in machine check exception handling */
  75 #define MCHECK_SPRG     SPRN_SPRG6W
  76
  77 #define MCHECK_STACK_BASE       mcheckirq_ctx
  78 #define CRIT_STACK_BASE         critirq_ctx
  79
  80 /* only on e500mc/e200 */
  81 #define DEBUG_STACK_BASE        dbgirq_ctx
  82 #ifdef CONFIG_E200
  83 #define DEBUG_SPRG              SPRN_SPRG6W
  84 #else
  85 #define DEBUG_SPRG              SPRN_SPRG9
  86 #endif
  87
  88 #define EXC_LVL_FRAME_OVERHEAD  (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
  89
  90 #ifdef CONFIG_SMP
  91 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
  92         mfspr   r8,SPRN_PIR;                            \
  93         slwi    r8,r8,2;                                \
  94         addis   r8,r8,level##_STACK_BASE@ha;            \
  95         lwz     r8,level##_STACK_BASE@l(r8);            \
  96         addi    r8,r8,EXC_LVL_FRAME_OVERHEAD;
  97 #else
  98 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
  99         lis     r8,level##_STACK_BASE@ha;               \
 100         lwz     r8,level##_STACK_BASE@l(r8);            \
 101         addi    r8,r8,EXC_LVL_FRAME_OVERHEAD;
 102 #endif
 103
 104 /*
 105  * Exception prolog for critical/machine check exceptions.  This is a
 106  * little different from the normal exception prolog above since a
 107  * critical/machine check exception can potentially occur at any point
 108  * during normal exception processing. Thus we cannot use the same SPRG
 109  * registers as the normal prolog above. Instead we use a portion of the
 110  * critical/machine check exception stack at low physical addresses.
 111  */
 112 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
 113         mtspr   exc_level##_SPRG,r8;                                         \
 114         BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
 115         stw     r9,GPR9(r8);            /* save various registers          */\
 116         mfcr    r9;                     /* save CR in r9 for now           */\
 117         stw     r10,GPR10(r8);                                               \
 118         stw     r11,GPR11(r8);                                               \
 119         stw     r9,_CCR(r8);            /* save CR on stack                */\
 120         mfspr   r10,exc_level_srr1;     /* check whether user or kernel    */\
 121         andi.   r10,r10,MSR_PR;                                              \
 122         mfspr   r11,SPRN_SPRG3;         /* if from user, start at top of   */\
 123         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
 124         addi    r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame    */\
 125         beq     1f;                                                          \
 126         /* COMING FROM USER MODE */                                          \
 127         stw     r9,_CCR(r11);           /* save CR                         */\
 128         lwz     r10,GPR10(r8);          /* copy regs from exception stack  */\
 129         lwz     r9,GPR9(r8);                                                 \
 130         stw     r10,GPR10(r11);                                              \
 131         lwz     r10,GPR11(r8);                                               \
 132         stw     r9,GPR9(r11);                                                \
 133         stw     r10,GPR11(r11);                                              \
 134         b       2f;                                                          \
 135         /* COMING FROM PRIV MODE */                                          \
 136 1:      lwz     r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11);                     \
 137         lwz     r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11);                  \
 138         stw     r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8);                      \
 139         stw     r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8);                   \
 140         lwz     r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11);                      \
 141         stw     r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8);                       \
 142         mr      r11,r8;                                                      \
 143 2:      mfspr   r8,exc_level##_SPRG;                                         \
 144         stw     r12,GPR12(r11);         /* save various registers          */\
 145         mflr    r10;                                                         \
 146         stw     r10,_LINK(r11);                                              \
 147         mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
 148         stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
 149         mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
 150         stw     r9,_ESR(r11);           /* exception was taken             */\
 151         mfspr   r12,exc_level_srr0;                                          \
 152         stw     r1,GPR1(r11);                                                \
 153         mfspr   r9,exc_level_srr1;                                           \
 154         stw     r1,0(r11);                                                   \
 155         mr      r1,r11;                                                      \
 156         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 157         stw     r0,GPR0(r11);                                                \
 158         SAVE_4GPRS(3, r11);                                                  \
 159         SAVE_2GPRS(7, r11)
 160
 161 #define CRITICAL_EXCEPTION_PROLOG \
 162                 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
 163 #define DEBUG_EXCEPTION_PROLOG \
 164                 EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
 165 #define MCHECK_EXCEPTION_PROLOG \
 166                 EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)
 167
 168 /*
 169  * Exception vectors.
 170  */
 171 #define START_EXCEPTION(label)                                               \
 172         .align 5;                                                            \
 173 label:
 174
 175 #define FINISH_EXCEPTION(func)                                  \
 176         bl      transfer_to_handler_full;                       \
 177         .long   func;                                           \
 178         .long   ret_from_except_full
 179
 180 #define EXCEPTION(n, label, hdlr, xfer)                         \
 181         START_EXCEPTION(label);                                 \
 182         NORMAL_EXCEPTION_PROLOG;                                \
 183         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 184         xfer(n, hdlr)
 185
 186 #define CRITICAL_EXCEPTION(n, label, hdlr)                      \
 187         START_EXCEPTION(label);                                 \
 188         CRITICAL_EXCEPTION_PROLOG;                              \
 189         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 190         EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 191                           NOCOPY, crit_transfer_to_handler, \
 192                           ret_from_crit_exc)
 193
 194 #define MCHECK_EXCEPTION(n, label, hdlr)                        \
 195         START_EXCEPTION(label);                                 \
 196         MCHECK_EXCEPTION_PROLOG;                                \
 197         mfspr   r5,SPRN_ESR;                                    \
 198         stw     r5,_ESR(r11);                                   \
 199         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 200         EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 201                           NOCOPY, mcheck_transfer_to_handler,   \
 202                           ret_from_mcheck_exc)
 203
 204 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)   \
 205         li      r10,trap;                                       \
 206         stw     r10,_TRAP(r11);                                 \
 207         lis     r10,msr@h;                                      \
 208         ori     r10,r10,msr@l;                                  \
 209         copyee(r10, r9);                                        \
 210         bl      tfer;                                           \
 211         .long   hdlr;                                           \
 212         .long   ret
 213
 214 #define COPY_EE(d, s)           rlwimi d,s,0,16,16
 215 #define NOCOPY(d, s)
 216
 217 #define EXC_XFER_STD(n, hdlr)           \
 218         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
 219                           ret_from_except_full)
 220
 221 #define EXC_XFER_LITE(n, hdlr)          \
 222         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
 223                           ret_from_except)
 224
 225 #define EXC_XFER_EE(n, hdlr)            \
 226         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
 227                           ret_from_except_full)
 228
 229 #define EXC_XFER_EE_LITE(n, hdlr)       \
 230         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
 231                           ret_from_except)
 232
 233 /* Check for a single step debug exception while in an exception
 234  * handler before state has been saved.  This is to catch the case
 235  * where an instruction that we are trying to single step causes
 236  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 237  * the exception handler generates a single step debug exception.
 238  *
 239  * If we get a debug trap on the first instruction of an exception handler,
 240  * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 241  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 242  * The exception handler was handling a non-critical interrupt, so it will
 243  * save (and later restore) the MSR via SPRN_CSRR1, which will still have
 244  * the MSR_DE bit set.
 245  */
 246 #define DEBUG_DEBUG_EXCEPTION                                                 \
 247         START_EXCEPTION(DebugDebug);                                          \
 248         DEBUG_EXCEPTION_PROLOG;                                               \
 249                                                                               \
 250         /*                                                                    \
 251          * If there is a single step or branch-taken exception in an          \
 252          * exception entry sequence, it was probably meant to apply to        \
 253          * the code where the exception occurred (since exception entry       \
 254          * doesn't turn off DE automatically).  We simulate the effect        \
 255          * of turning off DE on entry to an exception handler by turning      \
 256          * off DE in the DSRR1 value and clearing the debug status.           \
 257          */                                                                   \
 258         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
 259         andis.  r10,r10,DBSR_IC@h;                                            \
 260         beq+    2f;                                                           \
 261                                                                               \
 262         lis     r10,KERNELBASE@h;       /* check if exception in vectors */   \
 263         ori     r10,r10,KERNELBASE@l;                                         \
 264         cmplw   r12,r10;                                                      \
 265         blt+    2f;                     /* addr below exception vectors */    \
 266                                                                               \
 267         lis     r10,DebugDebug@h;                                             \
 268         ori     r10,r10,DebugDebug@l;                                         \
 269         cmplw   r12,r10;                                                      \
 270         bgt+    2f;                     /* addr above exception vectors */    \
 271                                                                               \
 272         /* here it looks like we got an inappropriate debug exception. */     \
 273 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CDRR1 value */     \
 274         lis     r10,DBSR_IC@h;          /* clear the IC event */              \
 275         mtspr   SPRN_DBSR,r10;                                                \
 276         /* restore state and get out */                                       \
 277         lwz     r10,_CCR(r11);                                                \
 278         lwz     r0,GPR0(r11);                                                 \
 279         lwz     r1,GPR1(r11);                                                 \
 280         mtcrf   0x80,r10;                                                     \
 281         mtspr   SPRN_DSRR0,r12;                                               \
 282         mtspr   SPRN_DSRR1,r9;                                                \
 283         lwz     r9,GPR9(r11);                                                 \
 284         lwz     r12,GPR12(r11);                                               \
 285         mtspr   DEBUG_SPRG,r8;                                                \
 286         BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
 287         lwz     r10,GPR10(r8);                                                \
 288         lwz     r11,GPR11(r8);                                                \
 289         mfspr   r8,DEBUG_SPRG;                                                \
 290                                                                               \
 291         PPC_RFDI;                                                                     \
 292         b       .;                                                            \
 293                                                                               \
 294         /* continue normal handling for a debug exception... */               \
 295 2:      mfspr   r4,SPRN_DBSR;                                                 \
 296         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 297         EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
 298
 299 #define DEBUG_CRIT_EXCEPTION                                                  \
 300         START_EXCEPTION(DebugCrit);                                           \
 301         CRITICAL_EXCEPTION_PROLOG;                                            \
 302                                                                               \
 303         /*                                                                    \
 304          * If there is a single step or branch-taken exception in an          \
 305          * exception entry sequence, it was probably meant to apply to        \
 306          * the code where the exception occurred (since exception entry       \
 307          * doesn't turn off DE automatically).  We simulate the effect        \
 308          * of turning off DE on entry to an exception handler by turning      \
 309          * off DE in the CSRR1 value and clearing the debug status.           \
 310          */                                                                   \
 311         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
 312         andis.  r10,r10,DBSR_IC@h;                                            \
 313         beq+    2f;                                                           \
 314                                                                               \
 315         lis     r10,KERNELBASE@h;       /* check if exception in vectors */   \
 316         ori     r10,r10,KERNELBASE@l;                                         \
 317         cmplw   r12,r10;                                                      \
 318         blt+    2f;                     /* addr below exception vectors */    \
 319                                                                               \
 320         lis     r10,DebugCrit@h;                                                      \
 321         ori     r10,r10,DebugCrit@l;                                          \
 322         cmplw   r12,r10;                                                      \
 323         bgt+    2f;                     /* addr above exception vectors */    \
 324                                                                               \
 325         /* here it looks like we got an inappropriate debug exception. */     \
 326 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CSRR1 value */     \
 327         lis     r10,DBSR_IC@h;          /* clear the IC event */              \
 328         mtspr   SPRN_DBSR,r10;                                                \
 329         /* restore state and get out */                                       \
 330         lwz     r10,_CCR(r11);                                                \
 331         lwz     r0,GPR0(r11);                                                 \
 332         lwz     r1,GPR1(r11);                                                 \
 333         mtcrf   0x80,r10;                                                     \
 334         mtspr   SPRN_CSRR0,r12;                                               \
 335         mtspr   SPRN_CSRR1,r9;                                                \
 336         lwz     r9,GPR9(r11);                                                 \
 337         lwz     r12,GPR12(r11);                                               \
 338         mtspr   CRIT_SPRG,r8;                                                 \
 339         BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
 340         lwz     r10,GPR10(r8);                                                \
 341         lwz     r11,GPR11(r8);                                                \
 342         mfspr   r8,CRIT_SPRG;                                                 \
 343                                                                               \
 344         rfci;                                                                 \
 345         b       .;                                                            \
 346                                                                               \
 347         /* continue normal handling for a critical exception... */            \
 348 2:      mfspr   r4,SPRN_DBSR;                                                 \
 349         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 350         EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
 351
 352 #define DATA_STORAGE_EXCEPTION                                                \
 353         START_EXCEPTION(DataStorage)                                          \
 354         NORMAL_EXCEPTION_PROLOG;                                              \
 355         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
 356         stw     r5,_ESR(r11);                                                 \
 357         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR */                   \
 358         EXC_XFER_EE_LITE(0x0300, handle_page_fault)
 359
 360 #define INSTRUCTION_STORAGE_EXCEPTION                                         \
 361         START_EXCEPTION(InstructionStorage)                                   \
 362         NORMAL_EXCEPTION_PROLOG;                                              \
 363         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
 364         stw     r5,_ESR(r11);                                                 \
 365         mr      r4,r12;                 /* Pass SRR0 as arg2 */               \
 366         li      r5,0;                   /* Pass zero as arg3 */               \
 367         EXC_XFER_EE_LITE(0x0400, handle_page_fault)
 368
 369 #define ALIGNMENT_EXCEPTION                                                   \
 370         START_EXCEPTION(Alignment)                                            \
 371         NORMAL_EXCEPTION_PROLOG;                                              \
 372         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR and save it */       \
 373         stw     r4,_DEAR(r11);                                                \
 374         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 375         EXC_XFER_EE(0x0600, alignment_exception)
 376
 377 #define PROGRAM_EXCEPTION                                                     \
 378         START_EXCEPTION(Program)                                              \
 379         NORMAL_EXCEPTION_PROLOG;                                              \
 380         mfspr   r4,SPRN_ESR;            /* Grab the ESR and save it */        \
 381         stw     r4,_ESR(r11);                                                 \
 382         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 383         EXC_XFER_STD(0x0700, program_check_exception)
 384
 385 #define DECREMENTER_EXCEPTION                                                 \
 386         START_EXCEPTION(Decrementer)                                          \
 387         NORMAL_EXCEPTION_PROLOG;                                              \
 388         lis     r0,TSR_DIS@h;           /* Setup the DEC interrupt mask */    \
 389         mtspr   SPRN_TSR,r0;            /* Clear the DEC interrupt */         \
 390         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 391         EXC_XFER_LITE(0x0900, timer_interrupt)
 392
 393 #define FP_UNAVAILABLE_EXCEPTION                                              \
 394         START_EXCEPTION(FloatingPointUnavailable)                             \
 395         NORMAL_EXCEPTION_PROLOG;                                              \
 396         beq     1f;                                                           \
 397         bl      load_up_fpu;            /* if from user, just load it up */   \
 398         b       fast_exception_return;                                        \
 399 1:      addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 400         EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
 401
 402 #ifndef __ASSEMBLY__
 403 struct exception_regs {
 404         unsigned long mas0;
 405         unsigned long mas1;
 406         unsigned long mas2;
 407         unsigned long mas3;
 408         unsigned long mas6;
 409         unsigned long mas7;
 410         unsigned long srr0;
 411         unsigned long srr1;
 412         unsigned long csrr0;
 413         unsigned long csrr1;
 414         unsigned long dsrr0;
 415         unsigned long dsrr1;
 416         unsigned long saved_ksp_limit;
 417 };
 418
 419 /* ensure this structure is always sized to a multiple of the stack alignment */
 420 #define STACK_EXC_LVL_FRAME_SIZE        _ALIGN_UP(sizeof (struct exception_regs), 16)
 421
 422 #endif /* __ASSEMBLY__ */
 423 #endif /* __HEAD_BOOKE_H__ */