arch/powerpc/include/asm/opal.h

   1 /*
   2  * PowerNV OPAL definitions.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_H
  13 #define __OPAL_H
  14
  15 #ifndef __ASSEMBLY__
  16 /*
  17  * SG entry
  18  *
  19  * WARNING: The current implementation requires each entry
  20  * to represent a block that is 4k aligned *and* each block
  21  * size except the last one in the list to be as well.
  22  */
  23 struct opal_sg_entry {
  24         __be64 data;
  25         __be64 length;
  26 };
  27
  28 /* SG list */
  29 struct opal_sg_list {
  30         __be64 length;
  31         __be64 next;
  32         struct opal_sg_entry entry[];
  33 };
  34
  35 /* We calculate number of sg entries based on PAGE_SIZE */
  36 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
  37
  38 #endif /* __ASSEMBLY__ */
  39
  40 /****** OPAL APIs ******/
  41
  42 /* Return codes */
  43 #define OPAL_SUCCESS            0
  44 #define OPAL_PARAMETER          -1
  45 #define OPAL_BUSY               -2
  46 #define OPAL_PARTIAL            -3
  47 #define OPAL_CONSTRAINED        -4
  48 #define OPAL_CLOSED             -5
  49 #define OPAL_HARDWARE           -6
  50 #define OPAL_UNSUPPORTED        -7
  51 #define OPAL_PERMISSION         -8
  52 #define OPAL_NO_MEM             -9
  53 #define OPAL_RESOURCE           -10
  54 #define OPAL_INTERNAL_ERROR     -11
  55 #define OPAL_BUSY_EVENT         -12
  56 #define OPAL_HARDWARE_FROZEN    -13
  57 #define OPAL_WRONG_STATE        -14
  58 #define OPAL_ASYNC_COMPLETION   -15
  59
  60 /* API Tokens (in r0) */
  61 #define OPAL_INVALID_CALL                       -1
  62 #define OPAL_CONSOLE_WRITE                      1
  63 #define OPAL_CONSOLE_READ                       2
  64 #define OPAL_RTC_READ                           3
  65 #define OPAL_RTC_WRITE                          4
  66 #define OPAL_CEC_POWER_DOWN                     5
  67 #define OPAL_CEC_REBOOT                         6
  68 #define OPAL_READ_NVRAM                         7
  69 #define OPAL_WRITE_NVRAM                        8
  70 #define OPAL_HANDLE_INTERRUPT                   9
  71 #define OPAL_POLL_EVENTS                        10
  72 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  73 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  74 #define OPAL_PCI_CONFIG_READ_BYTE               13
  75 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  76 #define OPAL_PCI_CONFIG_READ_WORD               15
  77 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  78 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  79 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  80 #define OPAL_SET_XIVE                           19
  81 #define OPAL_GET_XIVE                           20
  82 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  83 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  84 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  85 #define OPAL_PCI_SHPC                           24
  86 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  87 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  88 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  89 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  90 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  91 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  92 #define OPAL_PCI_SET_PE                         31
  93 #define OPAL_PCI_SET_PELTV                      32
  94 #define OPAL_PCI_SET_MVE                        33
  95 #define OPAL_PCI_SET_MVE_ENABLE                 34
  96 #define OPAL_PCI_GET_XIVE_REISSUE               35
  97 #define OPAL_PCI_SET_XIVE_REISSUE               36
  98 #define OPAL_PCI_SET_XIVE_PE                    37
  99 #define OPAL_GET_XIVE_SOURCE                    38
 100 #define OPAL_GET_MSI_32                         39
 101 #define OPAL_GET_MSI_64                         40
 102 #define OPAL_START_CPU                          41
 103 #define OPAL_QUERY_CPU_STATUS                   42
 104 #define OPAL_WRITE_OPPANEL                      43
 105 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 106 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 107 #define OPAL_PCI_RESET                          49
 108 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
 109 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
 110 #define OPAL_PCI_FENCE_PHB                      52
 111 #define OPAL_PCI_REINIT                         53
 112 #define OPAL_PCI_MASK_PE_ERROR                  54
 113 #define OPAL_SET_SLOT_LED_STATUS                55
 114 #define OPAL_GET_EPOW_STATUS                    56
 115 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 116 #define OPAL_RESERVED1                          58
 117 #define OPAL_RESERVED2                          59
 118 #define OPAL_PCI_NEXT_ERROR                     60
 119 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 120 #define OPAL_PCI_POLL                           62
 121 #define OPAL_PCI_MSI_EOI                        63
 122 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 123 #define OPAL_XSCOM_READ                         65
 124 #define OPAL_XSCOM_WRITE                        66
 125 #define OPAL_LPC_READ                           67
 126 #define OPAL_LPC_WRITE                          68
 127 #define OPAL_RETURN_CPU                         69
 128 #define OPAL_REINIT_CPUS                        70
 129 #define OPAL_ELOG_READ                          71
 130 #define OPAL_ELOG_WRITE                         72
 131 #define OPAL_ELOG_ACK                           73
 132 #define OPAL_ELOG_RESEND                        74
 133 #define OPAL_ELOG_SIZE                          75
 134 #define OPAL_FLASH_VALIDATE                     76
 135 #define OPAL_FLASH_MANAGE                       77
 136 #define OPAL_FLASH_UPDATE                       78
 137 #define OPAL_RESYNC_TIMEBASE                    79
 138 #define OPAL_CHECK_TOKEN                        80
 139 #define OPAL_DUMP_INIT                          81
 140 #define OPAL_DUMP_INFO                          82
 141 #define OPAL_DUMP_READ                          83
 142 #define OPAL_DUMP_ACK                           84
 143 #define OPAL_GET_MSG                            85
 144 #define OPAL_CHECK_ASYNC_COMPLETION             86
 145 #define OPAL_SYNC_HOST_REBOOT                   87
 146 #define OPAL_SENSOR_READ                        88
 147 #define OPAL_GET_PARAM                          89
 148 #define OPAL_SET_PARAM                          90
 149 #define OPAL_DUMP_RESEND                        91
 150 #define OPAL_PCI_SET_PHB_CXL_MODE               93
 151 #define OPAL_DUMP_INFO2                         94
 152 #define OPAL_PCI_ERR_INJECT                     96
 153 #define OPAL_PCI_EEH_FREEZE_SET                 97
 154 #define OPAL_HANDLE_HMI                         98
 155 #define OPAL_REGISTER_DUMP_REGION               101
 156 #define OPAL_UNREGISTER_DUMP_REGION             102
 157
 158 #ifndef __ASSEMBLY__
 159
 160 #include <linux/notifier.h>
 161
 162 /* Other enums */
 163 enum OpalVendorApiTokens {
 164         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 165 };
 166
 167 enum OpalFreezeState {
 168         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 169         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 170         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 171         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 172         OPAL_EEH_STOPPED_RESET = 4,
 173         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 174         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 175 };
 176
 177 enum OpalEehFreezeActionToken {
 178         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 179         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 180         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
 181
 182         OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
 183         OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
 184         OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
 185 };
 186
 187 enum OpalPciStatusToken {
 188         OPAL_EEH_NO_ERROR       = 0,
 189         OPAL_EEH_IOC_ERROR      = 1,
 190         OPAL_EEH_PHB_ERROR      = 2,
 191         OPAL_EEH_PE_ERROR       = 3,
 192         OPAL_EEH_PE_MMIO_ERROR  = 4,
 193         OPAL_EEH_PE_DMA_ERROR   = 5
 194 };
 195
 196 enum OpalPciErrorSeverity {
 197         OPAL_EEH_SEV_NO_ERROR   = 0,
 198         OPAL_EEH_SEV_IOC_DEAD   = 1,
 199         OPAL_EEH_SEV_PHB_DEAD   = 2,
 200         OPAL_EEH_SEV_PHB_FENCED = 3,
 201         OPAL_EEH_SEV_PE_ER      = 4,
 202         OPAL_EEH_SEV_INF        = 5
 203 };
 204
 205 enum OpalErrinjectType {
 206         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
 207         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
 208 };
 209
 210 enum OpalErrinjectFunc {
 211         /* IOA bus specific errors */
 212         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
 213         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
 214         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
 215         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
 216         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
 217         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
 218         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
 219         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
 220         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
 221         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
 222         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
 223         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
 224         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
 225         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
 226         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
 227         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
 228         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
 229         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
 230         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
 231         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
 232 };
 233
 234 enum OpalShpcAction {
 235         OPAL_SHPC_GET_LINK_STATE = 0,
 236         OPAL_SHPC_GET_SLOT_STATE = 1
 237 };
 238
 239 enum OpalShpcLinkState {
 240         OPAL_SHPC_LINK_DOWN = 0,
 241         OPAL_SHPC_LINK_UP = 1
 242 };
 243
 244 enum OpalMmioWindowType {
 245         OPAL_M32_WINDOW_TYPE = 1,
 246         OPAL_M64_WINDOW_TYPE = 2,
 247         OPAL_IO_WINDOW_TYPE = 3
 248 };
 249
 250 enum OpalShpcSlotState {
 251         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 252         OPAL_SHPC_DEV_PRESENT = 1
 253 };
 254
 255 enum OpalExceptionHandler {
 256         OPAL_MACHINE_CHECK_HANDLER = 1,
 257         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 258         OPAL_SOFTPATCH_HANDLER = 3
 259 };
 260
 261 enum OpalPendingState {
 262         OPAL_EVENT_OPAL_INTERNAL        = 0x1,
 263         OPAL_EVENT_NVRAM                = 0x2,
 264         OPAL_EVENT_RTC                  = 0x4,
 265         OPAL_EVENT_CONSOLE_OUTPUT       = 0x8,
 266         OPAL_EVENT_CONSOLE_INPUT        = 0x10,
 267         OPAL_EVENT_ERROR_LOG_AVAIL      = 0x20,
 268         OPAL_EVENT_ERROR_LOG            = 0x40,
 269         OPAL_EVENT_EPOW                 = 0x80,
 270         OPAL_EVENT_LED_STATUS           = 0x100,
 271         OPAL_EVENT_PCI_ERROR            = 0x200,
 272         OPAL_EVENT_DUMP_AVAIL           = 0x400,
 273         OPAL_EVENT_MSG_PENDING          = 0x800,
 274 };
 275
 276 enum OpalMessageType {
 277         OPAL_MSG_ASYNC_COMP = 0,        /* params[0] = token, params[1] = rc,
 278                                          * additional params function-specific
 279                                          */
 280         OPAL_MSG_MEM_ERR,
 281         OPAL_MSG_EPOW,
 282         OPAL_MSG_SHUTDOWN,
 283         OPAL_MSG_HMI_EVT,
 284         OPAL_MSG_TYPE_MAX,
 285 };
 286
 287 /* Machine check related definitions */
 288 enum OpalMCE_Version {
 289         OpalMCE_V1 = 1,
 290 };
 291
 292 enum OpalMCE_Severity {
 293         OpalMCE_SEV_NO_ERROR = 0,
 294         OpalMCE_SEV_WARNING = 1,
 295         OpalMCE_SEV_ERROR_SYNC = 2,
 296         OpalMCE_SEV_FATAL = 3,
 297 };
 298
 299 enum OpalMCE_Disposition {
 300         OpalMCE_DISPOSITION_RECOVERED = 0,
 301         OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
 302 };
 303
 304 enum OpalMCE_Initiator {
 305         OpalMCE_INITIATOR_UNKNOWN = 0,
 306         OpalMCE_INITIATOR_CPU = 1,
 307 };
 308
 309 enum OpalMCE_ErrorType {
 310         OpalMCE_ERROR_TYPE_UNKNOWN = 0,
 311         OpalMCE_ERROR_TYPE_UE = 1,
 312         OpalMCE_ERROR_TYPE_SLB = 2,
 313         OpalMCE_ERROR_TYPE_ERAT = 3,
 314         OpalMCE_ERROR_TYPE_TLB = 4,
 315 };
 316
 317 enum OpalMCE_UeErrorType {
 318         OpalMCE_UE_ERROR_INDETERMINATE = 0,
 319         OpalMCE_UE_ERROR_IFETCH = 1,
 320         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
 321         OpalMCE_UE_ERROR_LOAD_STORE = 3,
 322         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
 323 };
 324
 325 enum OpalMCE_SlbErrorType {
 326         OpalMCE_SLB_ERROR_INDETERMINATE = 0,
 327         OpalMCE_SLB_ERROR_PARITY = 1,
 328         OpalMCE_SLB_ERROR_MULTIHIT = 2,
 329 };
 330
 331 enum OpalMCE_EratErrorType {
 332         OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
 333         OpalMCE_ERAT_ERROR_PARITY = 1,
 334         OpalMCE_ERAT_ERROR_MULTIHIT = 2,
 335 };
 336
 337 enum OpalMCE_TlbErrorType {
 338         OpalMCE_TLB_ERROR_INDETERMINATE = 0,
 339         OpalMCE_TLB_ERROR_PARITY = 1,
 340         OpalMCE_TLB_ERROR_MULTIHIT = 2,
 341 };
 342
 343 enum OpalThreadStatus {
 344         OPAL_THREAD_INACTIVE = 0x0,
 345         OPAL_THREAD_STARTED = 0x1,
 346         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 347 };
 348
 349 enum OpalPciBusCompare {
 350         OpalPciBusAny   = 0,    /* Any bus number match */
 351         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 352         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 353         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 354         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 355         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 356         OpalPciBusAll   = 7,    /* Match bus number exactly */
 357 };
 358
 359 enum OpalDeviceCompare {
 360         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 361         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 362 };
 363
 364 enum OpalFuncCompare {
 365         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 366         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 367 };
 368
 369 enum OpalPeAction {
 370         OPAL_UNMAP_PE = 0,
 371         OPAL_MAP_PE = 1
 372 };
 373
 374 enum OpalPeltvAction {
 375         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 376         OPAL_ADD_PE_TO_DOMAIN = 1
 377 };
 378
 379 enum OpalMveEnableAction {
 380         OPAL_DISABLE_MVE = 0,
 381         OPAL_ENABLE_MVE = 1
 382 };
 383
 384 enum OpalM64EnableAction {
 385         OPAL_DISABLE_M64 = 0,
 386         OPAL_ENABLE_M64_SPLIT = 1,
 387         OPAL_ENABLE_M64_NON_SPLIT = 2
 388 };
 389
 390 enum OpalPciResetScope {
 391         OPAL_RESET_PHB_COMPLETE         = 1,
 392         OPAL_RESET_PCI_LINK             = 2,
 393         OPAL_RESET_PHB_ERROR            = 3,
 394         OPAL_RESET_PCI_HOT              = 4,
 395         OPAL_RESET_PCI_FUNDAMENTAL      = 5,
 396         OPAL_RESET_PCI_IODA_TABLE       = 6
 397 };
 398
 399 enum OpalPciReinitScope {
 400         OPAL_REINIT_PCI_DEV = 1000
 401 };
 402
 403 enum OpalPciResetState {
 404         OPAL_DEASSERT_RESET = 0,
 405         OPAL_ASSERT_RESET = 1
 406 };
 407
 408 enum OpalPciMaskAction {
 409         OPAL_UNMASK_ERROR_TYPE = 0,
 410         OPAL_MASK_ERROR_TYPE = 1
 411 };
 412
 413 enum OpalSlotLedType {
 414         OPAL_SLOT_LED_ID_TYPE = 0,
 415         OPAL_SLOT_LED_FAULT_TYPE = 1
 416 };
 417
 418 enum OpalLedAction {
 419         OPAL_TURN_OFF_LED = 0,
 420         OPAL_TURN_ON_LED = 1,
 421         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 422 };
 423
 424 enum OpalEpowStatus {
 425         OPAL_EPOW_NONE = 0,
 426         OPAL_EPOW_UPS = 1,
 427         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 428         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 429 };
 430
 431 /*
 432  * Address cycle types for LPC accesses. These also correspond
 433  * to the content of the first cell of the "reg" property for
 434  * device nodes on the LPC bus
 435  */
 436 enum OpalLPCAddressType {
 437         OPAL_LPC_MEM    = 0,
 438         OPAL_LPC_IO     = 1,
 439         OPAL_LPC_FW     = 2,
 440 };
 441
 442 /* System parameter permission */
 443 enum OpalSysparamPerm {
 444         OPAL_SYSPARAM_READ      = 0x1,
 445         OPAL_SYSPARAM_WRITE     = 0x2,
 446         OPAL_SYSPARAM_RW        = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 447 };
 448
 449 struct opal_msg {
 450         __be32 msg_type;
 451         __be32 reserved;
 452         __be64 params[8];
 453 };
 454
 455 struct opal_machine_check_event {
 456         enum OpalMCE_Version    version:8;      /* 0x00 */
 457         uint8_t                 in_use;         /* 0x01 */
 458         enum OpalMCE_Severity   severity:8;     /* 0x02 */
 459         enum OpalMCE_Initiator  initiator:8;    /* 0x03 */
 460         enum OpalMCE_ErrorType  error_type:8;   /* 0x04 */
 461         enum OpalMCE_Disposition disposition:8; /* 0x05 */
 462         uint8_t                 reserved_1[2];  /* 0x06 */
 463         uint64_t                gpr3;           /* 0x08 */
 464         uint64_t                srr0;           /* 0x10 */
 465         uint64_t                srr1;           /* 0x18 */
 466         union {                                 /* 0x20 */
 467                 struct {
 468                         enum OpalMCE_UeErrorType ue_error_type:8;
 469                         uint8_t         effective_address_provided;
 470                         uint8_t         physical_address_provided;
 471                         uint8_t         reserved_1[5];
 472                         uint64_t        effective_address;
 473                         uint64_t        physical_address;
 474                         uint8_t         reserved_2[8];
 475                 } ue_error;
 476
 477                 struct {
 478                         enum OpalMCE_SlbErrorType slb_error_type:8;
 479                         uint8_t         effective_address_provided;
 480                         uint8_t         reserved_1[6];
 481                         uint64_t        effective_address;
 482                         uint8_t         reserved_2[16];
 483                 } slb_error;
 484
 485                 struct {
 486                         enum OpalMCE_EratErrorType erat_error_type:8;
 487                         uint8_t         effective_address_provided;
 488                         uint8_t         reserved_1[6];
 489                         uint64_t        effective_address;
 490                         uint8_t         reserved_2[16];
 491                 } erat_error;
 492
 493                 struct {
 494                         enum OpalMCE_TlbErrorType tlb_error_type:8;
 495                         uint8_t         effective_address_provided;
 496                         uint8_t         reserved_1[6];
 497                         uint64_t        effective_address;
 498                         uint8_t         reserved_2[16];
 499                 } tlb_error;
 500         } u;
 501 };
 502
 503 /* FSP memory errors handling */
 504 enum OpalMemErr_Version {
 505         OpalMemErr_V1 = 1,
 506 };
 507
 508 enum OpalMemErrType {
 509         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 510         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 511         OPAL_MEM_ERR_TYPE_SCRUB,
 512 };
 513
 514 /* Memory Reilience error type */
 515 enum OpalMemErr_ResilErrType {
 516         OPAL_MEM_RESILIENCE_CE          = 0,
 517         OPAL_MEM_RESILIENCE_UE,
 518         OPAL_MEM_RESILIENCE_UE_SCRUB,
 519 };
 520
 521 /* Dynamic Memory Deallocation type */
 522 enum OpalMemErr_DynErrType {
 523         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 524 };
 525
 526 /* OpalMemoryErrorData->flags */
 527 #define OPAL_MEM_CORRECTED_ERROR        0x0001
 528 #define OPAL_MEM_THRESHOLD_EXCEEDED     0x0002
 529 #define OPAL_MEM_ACK_REQUIRED           0x8000
 530
 531 struct OpalMemoryErrorData {
 532         enum OpalMemErr_Version version:8;      /* 0x00 */
 533         enum OpalMemErrType     type:8;         /* 0x01 */
 534         __be16                  flags;          /* 0x02 */
 535         uint8_t                 reserved_1[4];  /* 0x04 */
 536
 537         union {
 538                 /* Memory Resilience corrected/uncorrected error info */
 539                 struct {
 540                         enum OpalMemErr_ResilErrType resil_err_type:8;
 541                         uint8_t         reserved_1[7];
 542                         __be64          physical_address_start;
 543                         __be64          physical_address_end;
 544                 } resilience;
 545                 /* Dynamic memory deallocation error info */
 546                 struct {
 547                         enum OpalMemErr_DynErrType dyn_err_type:8;
 548                         uint8_t         reserved_1[7];
 549                         __be64          physical_address_start;
 550                         __be64          physical_address_end;
 551                 } dyn_dealloc;
 552         } u;
 553 };
 554
 555 /* HMI interrupt event */
 556 enum OpalHMI_Version {
 557         OpalHMIEvt_V1 = 1,
 558 };
 559
 560 enum OpalHMI_Severity {
 561         OpalHMI_SEV_NO_ERROR = 0,
 562         OpalHMI_SEV_WARNING = 1,
 563         OpalHMI_SEV_ERROR_SYNC = 2,
 564         OpalHMI_SEV_FATAL = 3,
 565 };
 566
 567 enum OpalHMI_Disposition {
 568         OpalHMI_DISPOSITION_RECOVERED = 0,
 569         OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
 570 };
 571
 572 enum OpalHMI_ErrType {
 573         OpalHMI_ERROR_MALFUNC_ALERT     = 0,
 574         OpalHMI_ERROR_PROC_RECOV_DONE,
 575         OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
 576         OpalHMI_ERROR_PROC_RECOV_MASKED,
 577         OpalHMI_ERROR_TFAC,
 578         OpalHMI_ERROR_TFMR_PARITY,
 579         OpalHMI_ERROR_HA_OVERFLOW_WARN,
 580         OpalHMI_ERROR_XSCOM_FAIL,
 581         OpalHMI_ERROR_XSCOM_DONE,
 582         OpalHMI_ERROR_SCOM_FIR,
 583         OpalHMI_ERROR_DEBUG_TRIG_FIR,
 584         OpalHMI_ERROR_HYP_RESOURCE,
 585 };
 586
 587 struct OpalHMIEvent {
 588         uint8_t         version;        /* 0x00 */
 589         uint8_t         severity;       /* 0x01 */
 590         uint8_t         type;           /* 0x02 */
 591         uint8_t         disposition;    /* 0x03 */
 592         uint8_t         reserved_1[4];  /* 0x04 */
 593
 594         __be64          hmer;
 595         /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
 596         __be64          tfmr;
 597 };
 598
 599 enum {
 600         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 601         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 602         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 603         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 604         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 605         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 606         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 607 };
 608
 609 struct OpalIoP7IOCErrorData {
 610         __be16 type;
 611
 612         /* GEM */
 613         __be64 gemXfir;
 614         __be64 gemRfir;
 615         __be64 gemRirqfir;
 616         __be64 gemMask;
 617         __be64 gemRwof;
 618
 619         /* LEM */
 620         __be64 lemFir;
 621         __be64 lemErrMask;
 622         __be64 lemAction0;
 623         __be64 lemAction1;
 624         __be64 lemWof;
 625
 626         union {
 627                 struct OpalIoP7IOCRgcErrorData {
 628                         __be64 rgcStatus;       /* 3E1C10 */
 629                         __be64 rgcLdcp;         /* 3E1C18 */
 630                 }rgc;
 631                 struct OpalIoP7IOCBiErrorData {
 632                         __be64 biLdcp0;         /* 3C0100, 3C0118 */
 633                         __be64 biLdcp1;         /* 3C0108, 3C0120 */
 634                         __be64 biLdcp2;         /* 3C0110, 3C0128 */
 635                         __be64 biFenceStatus;   /* 3C0130, 3C0130 */
 636
 637                             u8 biDownbound;     /* BI Downbound or Upbound */
 638                 }bi;
 639                 struct OpalIoP7IOCCiErrorData {
 640                         __be64 ciPortStatus;    /* 3Dn008 */
 641                         __be64 ciPortLdcp;      /* 3Dn010 */
 642
 643                             u8 ciPort;          /* Index of CI port: 0/1 */
 644                 }ci;
 645         };
 646 };
 647
 648 /**
 649  * This structure defines the overlay which will be used to store PHB error
 650  * data upon request.
 651  */
 652 enum {
 653         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 654 };
 655
 656 enum {
 657         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 658         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 659 };
 660
 661 enum {
 662         OPAL_P7IOC_NUM_PEST_REGS = 128,
 663         OPAL_PHB3_NUM_PEST_REGS = 256
 664 };
 665
 666 struct OpalIoPhbErrorCommon {
 667         __be32 version;
 668         __be32 ioType;
 669         __be32 len;
 670 };
 671
 672 struct OpalIoP7IOCPhbErrorData {
 673         struct OpalIoPhbErrorCommon common;
 674
 675         __be32 brdgCtl;
 676
 677         // P7IOC utl regs
 678         __be32 portStatusReg;
 679         __be32 rootCmplxStatus;
 680         __be32 busAgentStatus;
 681
 682         // P7IOC cfg regs
 683         __be32 deviceStatus;
 684         __be32 slotStatus;
 685         __be32 linkStatus;
 686         __be32 devCmdStatus;
 687         __be32 devSecStatus;
 688
 689         // cfg AER regs
 690         __be32 rootErrorStatus;
 691         __be32 uncorrErrorStatus;
 692         __be32 corrErrorStatus;
 693         __be32 tlpHdr1;
 694         __be32 tlpHdr2;
 695         __be32 tlpHdr3;
 696         __be32 tlpHdr4;
 697         __be32 sourceId;
 698
 699         __be32 rsv3;
 700
 701         // Record data about the call to allocate a buffer.
 702         __be64 errorClass;
 703         __be64 correlator;
 704
 705         //P7IOC MMIO Error Regs
 706         __be64 p7iocPlssr;                // n120
 707         __be64 p7iocCsr;                  // n110
 708         __be64 lemFir;                    // nC00
 709         __be64 lemErrorMask;              // nC18
 710         __be64 lemWOF;                    // nC40
 711         __be64 phbErrorStatus;            // nC80
 712         __be64 phbFirstErrorStatus;       // nC88
 713         __be64 phbErrorLog0;              // nCC0
 714         __be64 phbErrorLog1;              // nCC8
 715         __be64 mmioErrorStatus;           // nD00
 716         __be64 mmioFirstErrorStatus;      // nD08
 717         __be64 mmioErrorLog0;             // nD40
 718         __be64 mmioErrorLog1;             // nD48
 719         __be64 dma0ErrorStatus;           // nD80
 720         __be64 dma0FirstErrorStatus;      // nD88
 721         __be64 dma0ErrorLog0;             // nDC0
 722         __be64 dma0ErrorLog1;             // nDC8
 723         __be64 dma1ErrorStatus;           // nE00
 724         __be64 dma1FirstErrorStatus;      // nE08
 725         __be64 dma1ErrorLog0;             // nE40
 726         __be64 dma1ErrorLog1;             // nE48
 727         __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
 728         __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
 729 };
 730
 731 struct OpalIoPhb3ErrorData {
 732         struct OpalIoPhbErrorCommon common;
 733
 734         __be32 brdgCtl;
 735
 736         /* PHB3 UTL regs */
 737         __be32 portStatusReg;
 738         __be32 rootCmplxStatus;
 739         __be32 busAgentStatus;
 740
 741         /* PHB3 cfg regs */
 742         __be32 deviceStatus;
 743         __be32 slotStatus;
 744         __be32 linkStatus;
 745         __be32 devCmdStatus;
 746         __be32 devSecStatus;
 747
 748         /* cfg AER regs */
 749         __be32 rootErrorStatus;
 750         __be32 uncorrErrorStatus;
 751         __be32 corrErrorStatus;
 752         __be32 tlpHdr1;
 753         __be32 tlpHdr2;
 754         __be32 tlpHdr3;
 755         __be32 tlpHdr4;
 756         __be32 sourceId;
 757
 758         __be32 rsv3;
 759
 760         /* Record data about the call to allocate a buffer */
 761         __be64 errorClass;
 762         __be64 correlator;
 763
 764         __be64 nFir;                    /* 000 */
 765         __be64 nFirMask;                /* 003 */
 766         __be64 nFirWOF;         /* 008 */
 767
 768         /* PHB3 MMIO Error Regs */
 769         __be64 phbPlssr;                /* 120 */
 770         __be64 phbCsr;          /* 110 */
 771         __be64 lemFir;          /* C00 */
 772         __be64 lemErrorMask;            /* C18 */
 773         __be64 lemWOF;          /* C40 */
 774         __be64 phbErrorStatus;  /* C80 */
 775         __be64 phbFirstErrorStatus;     /* C88 */
 776         __be64 phbErrorLog0;            /* CC0 */
 777         __be64 phbErrorLog1;            /* CC8 */
 778         __be64 mmioErrorStatus; /* D00 */
 779         __be64 mmioFirstErrorStatus;    /* D08 */
 780         __be64 mmioErrorLog0;           /* D40 */
 781         __be64 mmioErrorLog1;           /* D48 */
 782         __be64 dma0ErrorStatus; /* D80 */
 783         __be64 dma0FirstErrorStatus;    /* D88 */
 784         __be64 dma0ErrorLog0;           /* DC0 */
 785         __be64 dma0ErrorLog1;           /* DC8 */
 786         __be64 dma1ErrorStatus; /* E00 */
 787         __be64 dma1FirstErrorStatus;    /* E08 */
 788         __be64 dma1ErrorLog0;           /* E40 */
 789         __be64 dma1ErrorLog1;           /* E48 */
 790         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 791         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 792 };
 793
 794 enum {
 795         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 796         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 797 };
 798
 799 typedef struct oppanel_line {
 800         const char *    line;
 801         uint64_t        line_len;
 802 } oppanel_line_t;
 803
 804 /* /sys/firmware/opal */
 805 extern struct kobject *opal_kobj;
 806
 807 /* /ibm,opal */
 808 extern struct device_node *opal_node;
 809
 810 /* API functions */
 811 int64_t opal_invalid_call(void);
 812 int64_t opal_console_write(int64_t term_number, __be64 *length,
 813                            const uint8_t *buffer);
 814 int64_t opal_console_read(int64_t term_number, __be64 *length,
 815                           uint8_t *buffer);
 816 int64_t opal_console_write_buffer_space(int64_t term_number,
 817                                         __be64 *length);
 818 int64_t opal_rtc_read(__be32 *year_month_day,
 819                       __be64 *hour_minute_second_millisecond);
 820 int64_t opal_rtc_write(uint32_t year_month_day,
 821                        uint64_t hour_minute_second_millisecond);
 822 int64_t opal_cec_power_down(uint64_t request);
 823 int64_t opal_cec_reboot(void);
 824 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 825 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 826 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
 827 int64_t opal_poll_events(__be64 *outstanding_event_mask);
 828 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
 829                                     uint64_t tce_mem_size);
 830 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
 831                                     uint64_t tce_mem_size);
 832 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
 833                                   uint64_t offset, uint8_t *data);
 834 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 835                                        uint64_t offset, __be16 *data);
 836 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
 837                                   uint64_t offset, __be32 *data);
 838 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
 839                                    uint64_t offset, uint8_t data);
 840 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 841                                         uint64_t offset, uint16_t data);
 842 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
 843                                    uint64_t offset, uint32_t data);
 844 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
 845 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
 846 int64_t opal_register_exception_handler(uint64_t opal_exception,
 847                                         uint64_t handler_address,
 848                                         uint64_t glue_cache_line);
 849 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 850                                    uint8_t *freeze_state,
 851                                    __be16 *pci_error_type,
 852                                    __be64 *phb_status);
 853 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 854                                   uint64_t eeh_action_token);
 855 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
 856                                 uint64_t eeh_action_token);
 857 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
 858                             uint32_t func, uint64_t addr, uint64_t mask);
 859 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 860
 861
 862
 863 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
 864                                  uint16_t window_num, uint16_t enable);
 865 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
 866                                     uint16_t window_num,
 867                                     uint64_t starting_real_address,
 868                                     uint64_t starting_pci_address,
 869                                     uint64_t size);
 870 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 871                                     uint16_t window_type, uint16_t window_num,
 872                                     uint16_t segment_num);
 873 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
 874                                       uint64_t ivt_addr, uint64_t ivt_len,
 875                                       uint64_t reject_array_addr,
 876                                       uint64_t peltv_addr);
 877 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
 878                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
 879                         uint8_t pe_action);
 880 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
 881                            uint8_t state);
 882 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
 883 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 884                                 uint32_t state);
 885 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 886                                   uint8_t *p_bit, uint8_t *q_bit);
 887 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 888                                   uint8_t p_bit, uint8_t q_bit);
 889 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 890 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 891                              uint32_t xive_num);
 892 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 893                              __be32 *interrupt_source_number);
 894 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
 895                         uint8_t msi_range, __be32 *msi_address,
 896                         __be32 *message_data);
 897 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 898                         uint32_t xive_num, uint8_t msi_range,
 899                         __be64 *msi_address, __be32 *message_data);
 900 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
 901 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
 902 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
 903 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
 904                                    uint16_t tce_levels, uint64_t tce_table_addr,
 905                                    uint64_t tce_table_size, uint64_t tce_page_size);
 906 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
 907                                         uint16_t dma_window_number, uint64_t pci_start_addr,
 908                                         uint64_t pci_mem_size);
 909 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 910
 911 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
 912                                    uint64_t diag_buffer_len);
 913 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
 914                                    uint64_t diag_buffer_len);
 915 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
 916                                     uint64_t diag_buffer_len);
 917 int64_t opal_pci_fence_phb(uint64_t phb_id);
 918 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
 919 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 920 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 921 int64_t opal_get_epow_status(__be64 *status);
 922 int64_t opal_set_system_attention_led(uint8_t led_action);
 923 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
 924                             __be16 *pci_error_type, __be16 *severity);
 925 int64_t opal_pci_poll(uint64_t phb_id);
 926 int64_t opal_return_cpu(void);
 927 int64_t opal_check_token(uint64_t token);
 928 int64_t opal_reinit_cpus(uint64_t flags);
 929
 930 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
 931 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
 932
 933 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 934                        uint32_t addr, uint32_t data, uint32_t sz);
 935 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 936                       uint32_t addr, __be32 *data, uint32_t sz);
 937
 938 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
 939 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
 940 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
 941 int64_t opal_send_ack_elog(uint64_t log_id);
 942 void opal_resend_pending_logs(void);
 943
 944 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
 945 int64_t opal_manage_flash(uint8_t op);
 946 int64_t opal_update_flash(uint64_t blk_list);
 947 int64_t opal_dump_init(uint8_t dump_type);
 948 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
 949 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
 950 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
 951 int64_t opal_dump_ack(uint32_t dump_id);
 952 int64_t opal_dump_resend_notification(void);
 953
 954 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
 955 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
 956 int64_t opal_sync_host_reboot(void);
 957 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 958                 uint64_t length);
 959 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 960                 uint64_t length);
 961 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
 962 int64_t opal_handle_hmi(void);
 963 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
 964 int64_t opal_unregister_dump_region(uint32_t id);
 965 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
 966
 967 /* Internal functions */
 968 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
 969                                    int depth, void *data);
 970 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
 971                                  const char *uname, int depth, void *data);
 972
 973 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 974 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 975
 976 extern void hvc_opal_init_early(void);
 977
 978 extern int opal_notifier_register(struct notifier_block *nb);
 979 extern int opal_notifier_unregister(struct notifier_block *nb);
 980
 981 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
 982                                                 struct notifier_block *nb);
 983 extern void opal_notifier_enable(void);
 984 extern void opal_notifier_disable(void);
 985 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
 986
 987 extern int __opal_async_get_token(void);
 988 extern int opal_async_get_token_interruptible(void);
 989 extern int __opal_async_release_token(int token);
 990 extern int opal_async_release_token(int token);
 991 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
 992 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
 993
 994 struct rtc_time;
 995 extern int opal_set_rtc_time(struct rtc_time *tm);
 996 extern void opal_get_rtc_time(struct rtc_time *tm);
 997 extern unsigned long opal_get_boot_time(void);
 998 extern void opal_nvram_init(void);
 999 extern void opal_flash_init(void);
1000 extern void opal_flash_term_callback(void);
1001 extern int opal_elog_init(void);
1002 extern void opal_platform_dump_init(void);
1003 extern void opal_sys_param_init(void);
1004 extern void opal_msglog_init(void);
1005
1006 extern int opal_machine_check(struct pt_regs *regs);
1007 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
1008 extern int opal_hmi_exception_early(struct pt_regs *regs);
1009 extern int opal_handle_hmi_exception(struct pt_regs *regs);
1010
1011 extern void opal_shutdown(void);
1012 extern int opal_resync_timebase(void);
1013
1014 extern void opal_lpc_init(void);
1015
1016 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
1017                                              unsigned long vmalloc_size);
1018 void opal_free_sg_list(struct opal_sg_list *sg);
1019
1020 /*
1021  * Dump region ID range usable by the OS
1022  */
1023 #define OPAL_DUMP_REGION_HOST_START             0x80
1024 #define OPAL_DUMP_REGION_LOG_BUF                0x80
1025 #define OPAL_DUMP_REGION_HOST_END               0xFF
1026
1027 #endif /* __ASSEMBLY__ */
1028
1029 #endif /* __OPAL_H */