1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
3 #define _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
6 * 32-bit hash table MMU support
15 /* Block size masks */
29 /* BAT Access Protection */
30 #define BPP_XX 0x00 /* No access */
31 #define BPP_RX 0x01 /* Read only */
32 #define BPP_RW 0x02 /* Read/write */
35 /* Contort a phys_addr_t into the right format/bits for a BAT */
36 #ifdef CONFIG_PHYS_64BIT
37 #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
38 ((x & 0x0000000e00000000ULL) >> 24) | \
39 ((x & 0x0000000100000000ULL) >> 30)))
40 #define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \
41 (((u64)(x) << 24) & 0x0000000e00000000ULL) | \
42 (((u64)(x) << 30) & 0x0000000100000000ULL))
44 #define BAT_PHYS_ADDR(x) (x)
45 #define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000)
53 typedef pte_t *pgtable_t;
54 #endif /* !__ASSEMBLY__ */
60 /* Values for PP (assumes Ks=0, Kp=1) */
61 #define PP_RWXX 0 /* Supervisor read/write, User none */
62 #define PP_RWRX 1 /* Supervisor read/write, User read */
63 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
64 #define PP_RXRX 3 /* Supervisor read, User read */
69 * Hardware Page Table Entry
70 * Note that the xpn and x bitfields are used only by processors that
71 * support extended addressing; otherwise, those bits are reserved.
74 unsigned long v:1; /* Entry is valid */
75 unsigned long vsid:24; /* Virtual segment identifier */
76 unsigned long h:1; /* Hash algorithm indicator */
77 unsigned long api:6; /* Abbreviated page index */
78 unsigned long rpn:20; /* Real (physical) page number */
79 unsigned long xpn:3; /* Real page number bits 0-2, optional */
80 unsigned long r:1; /* Referenced */
81 unsigned long c:1; /* Changed */
82 unsigned long w:1; /* Write-thru cache mode */
83 unsigned long i:1; /* Cache inhibited */
84 unsigned long m:1; /* Memory coherence */
85 unsigned long g:1; /* Guarded */
86 unsigned long x:1; /* Real page number bit 3, optional */
87 unsigned long pp:2; /* Page protection */
92 unsigned long vdso_base;
95 void update_bats(void);
98 extern s32 patch__hash_page_A0, patch__hash_page_A1, patch__hash_page_A2;
99 extern s32 patch__hash_page_B, patch__hash_page_C;
100 extern s32 patch__flush_hash_A0, patch__flush_hash_A1, patch__flush_hash_A2;
101 extern s32 patch__flush_hash_B;
103 #endif /* !__ASSEMBLY__ */
105 /* We happily ignore the smaller BATs on 601, we don't actually use
106 * those definitions on hash32 at the moment anyway
108 #define mmu_virtual_psize MMU_PAGE_4K
109 #define mmu_linear_psize MMU_PAGE_256M
111 #endif /* _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ */