arch/powerpc/boot/dts/tqm8548.dts

   1 /*
   2  * TQM8548 Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 /dts-v1/;
  14
  15 / {
  16         model = "tqc,tqm8548";
  17         compatible = "tqc,tqm8548";
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         aliases {
  22                 ethernet0 = &enet0;
  23                 ethernet1 = &enet1;
  24                 ethernet2 = &enet2;
  25                 ethernet3 = &enet3;
  26
  27                 serial0 = &serial0;
  28                 serial1 = &serial1;
  29                 pci0 = &pci0;
  30                 pci1 = &pci1;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 PowerPC,8548@0 {
  38                         device_type = "cpu";
  39                         reg = <0>;
  40                         d-cache-line-size = <32>;       // 32 bytes
  41                         i-cache-line-size = <32>;       // 32 bytes
  42                         d-cache-size = <0x8000>;        // L1, 32K
  43                         i-cache-size = <0x8000>;        // L1, 32K
  44                         next-level-cache = <&L2>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x00000000 0x00000000>;  // Filled in by U-Boot
  51         };
  52
  53         soc8548@e0000000 {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 device_type = "soc";
  57                 ranges = <0x0 0xe0000000 0x100000>;
  58                 reg = <0xe0000000 0x1000>;      // CCSRBAR
  59                 bus-frequency = <0>;
  60
  61                 memory-controller@2000 {
  62                         compatible = "fsl,mpc8548-memory-controller";
  63                         reg = <0x2000 0x1000>;
  64                         interrupt-parent = <&mpic>;
  65                         interrupts = <18 2>;
  66                 };
  67
  68                 L2: l2-cache-controller@20000 {
  69                         compatible = "fsl,mpc8548-l2-cache-controller";
  70                         reg = <0x20000 0x1000>;
  71                         cache-line-size = <32>; // 32 bytes
  72                         cache-size = <0x80000>; // L2, 512K
  73                         interrupt-parent = <&mpic>;
  74                         interrupts = <16 2>;
  75                 };
  76
  77                 i2c@3000 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         cell-index = <0>;
  81                         compatible = "fsl-i2c";
  82                         reg = <0x3000 0x100>;
  83                         interrupts = <43 2>;
  84                         interrupt-parent = <&mpic>;
  85                         dfsrr;
  86
  87                         rtc@68 {
  88                                 compatible = "dallas,ds1337";
  89                                 reg = <0x68>;
  90                         };
  91                 };
  92
  93                 i2c@3100 {
  94                         #address-cells = <1>;
  95                         #size-cells = <0>;
  96                         cell-index = <1>;
  97                         compatible = "fsl-i2c";
  98                         reg = <0x3100 0x100>;
  99                         interrupts = <43 2>;
 100                         interrupt-parent = <&mpic>;
 101                         dfsrr;
 102                 };
 103
 104                 dma@21300 {
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
 108                         reg = <0x21300 0x4>;
 109                         ranges = <0x0 0x21100 0x200>;
 110                         cell-index = <0>;
 111                         dma-channel@0 {
 112                                 compatible = "fsl,mpc8548-dma-channel",
 113                                                 "fsl,eloplus-dma-channel";
 114                                 reg = <0x0 0x80>;
 115                                 cell-index = <0>;
 116                                 interrupt-parent = <&mpic>;
 117                                 interrupts = <20 2>;
 118                         };
 119                         dma-channel@80 {
 120                                 compatible = "fsl,mpc8548-dma-channel",
 121                                                 "fsl,eloplus-dma-channel";
 122                                 reg = <0x80 0x80>;
 123                                 cell-index = <1>;
 124                                 interrupt-parent = <&mpic>;
 125                                 interrupts = <21 2>;
 126                         };
 127                         dma-channel@100 {
 128                                 compatible = "fsl,mpc8548-dma-channel",
 129                                                 "fsl,eloplus-dma-channel";
 130                                 reg = <0x100 0x80>;
 131                                 cell-index = <2>;
 132                                 interrupt-parent = <&mpic>;
 133                                 interrupts = <22 2>;
 134                         };
 135                         dma-channel@180 {
 136                                 compatible = "fsl,mpc8548-dma-channel",
 137                                                 "fsl,eloplus-dma-channel";
 138                                 reg = <0x180 0x80>;
 139                                 cell-index = <3>;
 140                                 interrupt-parent = <&mpic>;
 141                                 interrupts = <23 2>;
 142                         };
 143                 };
 144
 145                 mdio@24520 {
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         compatible = "fsl,gianfar-mdio";
 149                         reg = <0x24520 0x20>;
 150
 151                         phy1: ethernet-phy@0 {
 152                                 interrupt-parent = <&mpic>;
 153                                 interrupts = <8 1>;
 154                                 reg = <1>;
 155                                 device_type = "ethernet-phy";
 156                         };
 157                         phy2: ethernet-phy@1 {
 158                                 interrupt-parent = <&mpic>;
 159                                 interrupts = <8 1>;
 160                                 reg = <2>;
 161                                 device_type = "ethernet-phy";
 162                         };
 163                         phy3: ethernet-phy@3 {
 164                                 interrupt-parent = <&mpic>;
 165                                 interrupts = <8 1>;
 166                                 reg = <3>;
 167                                 device_type = "ethernet-phy";
 168                         };
 169                         phy4: ethernet-phy@4 {
 170                                 interrupt-parent = <&mpic>;
 171                                 interrupts = <8 1>;
 172                                 reg = <4>;
 173                                 device_type = "ethernet-phy";
 174                         };
 175                         phy5: ethernet-phy@5 {
 176                                 interrupt-parent = <&mpic>;
 177                                 interrupts = <8 1>;
 178                                 reg = <5>;
 179                                 device_type = "ethernet-phy";
 180                         };
 181                 };
 182
 183                 enet0: ethernet@24000 {
 184                         cell-index = <0>;
 185                         device_type = "network";
 186                         model = "eTSEC";
 187                         compatible = "gianfar";
 188                         reg = <0x24000 0x1000>;
 189                         local-mac-address = [ 00 00 00 00 00 00 ];
 190                         interrupts = <29 2 30 2 34 2>;
 191                         interrupt-parent = <&mpic>;
 192                         phy-handle = <&phy2>;
 193                 };
 194
 195                 enet1: ethernet@25000 {
 196                         cell-index = <1>;
 197                         device_type = "network";
 198                         model = "eTSEC";
 199                         compatible = "gianfar";
 200                         reg = <0x25000 0x1000>;
 201                         local-mac-address = [ 00 00 00 00 00 00 ];
 202                         interrupts = <35 2 36 2 40 2>;
 203                         interrupt-parent = <&mpic>;
 204                         phy-handle = <&phy1>;
 205                 };
 206
 207                 enet2: ethernet@26000 {
 208                         cell-index = <2>;
 209                         device_type = "network";
 210                         model = "eTSEC";
 211                         compatible = "gianfar";
 212                         reg = <0x26000 0x1000>;
 213                         local-mac-address = [ 00 00 00 00 00 00 ];
 214                         interrupts = <31 2 32 2 33 2>;
 215                         interrupt-parent = <&mpic>;
 216                         phy-handle = <&phy3>;
 217                 };
 218
 219                 enet3: ethernet@27000 {
 220                         cell-index = <3>;
 221                         device_type = "network";
 222                         model = "eTSEC";
 223                         compatible = "gianfar";
 224                         reg = <0x27000 0x1000>;
 225                         local-mac-address = [ 00 00 00 00 00 00 ];
 226                         interrupts = <37 2 38 2 39 2>;
 227                         interrupt-parent = <&mpic>;
 228                         phy-handle = <&phy4>;
 229                 };
 230
 231                 serial0: serial@4500 {
 232                         cell-index = <0>;
 233                         device_type = "serial";
 234                         compatible = "ns16550";
 235                         reg = <0x4500 0x100>;   // reg base, size
 236                         clock-frequency = <0>;  // should we fill in in uboot?
 237                         current-speed = <115200>;
 238                         interrupts = <42 2>;
 239                         interrupt-parent = <&mpic>;
 240                 };
 241
 242                 serial1: serial@4600 {
 243                         cell-index = <1>;
 244                         device_type = "serial";
 245                         compatible = "ns16550";
 246                         reg = <0x4600 0x100>;   // reg base, size
 247                         clock-frequency = <0>;  // should we fill in in uboot?
 248                         current-speed = <115200>;
 249                         interrupts = <42 2>;
 250                         interrupt-parent = <&mpic>;
 251                 };
 252
 253                 global-utilities@e0000 {        // global utilities reg
 254                         compatible = "fsl,mpc8548-guts";
 255                         reg = <0xe0000 0x1000>;
 256                         fsl,has-rstcr;
 257                 };
 258
 259                 mpic: pic@40000 {
 260                         interrupt-controller;
 261                         #address-cells = <0>;
 262                         #interrupt-cells = <2>;
 263                         reg = <0x40000 0x40000>;
 264                         compatible = "chrp,open-pic";
 265                         device_type = "open-pic";
 266                 };
 267         };
 268
 269         localbus@e0005000 {
 270                 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
 271                              "simple-bus";
 272                 #address-cells = <2>;
 273                 #size-cells = <1>;
 274                 reg = <0xe0005000 0x100>;       // BRx, ORx, etc.
 275
 276                 ranges = <
 277                         0 0x0 0xfc000000 0x04000000     // NOR FLASH bank 1
 278                         1 0x0 0xf8000000 0x08000000     // NOR FLASH bank 0
 279                         2 0x0 0xe3000000 0x00008000     // CAN (2 x i82527)
 280                         3 0x0 0xe3010000 0x00008000     // NAND FLASH
 281
 282                 >;
 283
 284                 flash@1,0 {
 285                         #address-cells = <1>;
 286                         #size-cells = <1>;
 287                         compatible = "cfi-flash";
 288                         reg = <1 0x0 0x8000000>;
 289                         bank-width = <4>;
 290                         device-width = <1>;
 291
 292                         partition@0 {
 293                                 label = "kernel";
 294                                 reg = <0x00000000 0x00200000>;
 295                         };
 296                         partition@200000 {
 297                                 label = "root";
 298                                 reg = <0x00200000 0x00300000>;
 299                         };
 300                         partition@500000 {
 301                                 label = "user";
 302                                 reg = <0x00500000 0x07a00000>;
 303                         };
 304                         partition@7f00000 {
 305                                 label = "env1";
 306                                 reg = <0x07f00000 0x00040000>;
 307                         };
 308                         partition@7f40000 {
 309                                 label = "env2";
 310                                 reg = <0x07f40000 0x00040000>;
 311                         };
 312                         partition@7f80000 {
 313                                 label = "u-boot";
 314                                 reg = <0x07f80000 0x00080000>;
 315                                 read-only;
 316                         };
 317                 };
 318
 319                 /* Note: CAN support needs be enabled in U-Boot */
 320                 can0@2,0 {
 321                         compatible = "intel,82527"; // Bosch CC770
 322                         reg = <2 0x0 0x100>;
 323                         interrupts = <4 0>;
 324                         interrupt-parent = <&mpic>;
 325                 };
 326
 327                 can1@2,100 {
 328                         compatible = "intel,82527"; // Bosch CC770
 329                         reg = <2 0x100 0x100>;
 330                         interrupts = <4 0>;
 331                         interrupt-parent = <&mpic>;
 332                 };
 333
 334                 /* Note: NAND support needs to be enabled in U-Boot */
 335                 upm@3,0 {
 336                         #address-cells = <0>;
 337                         #size-cells = <0>;
 338                         compatible = "fsl,upm-nand";
 339                         reg = <3 0x0 0x800>;
 340                         fsl,upm-addr-offset = <0x10>;
 341                         fsl,upm-cmd-offset = <0x08>;
 342                         chip-delay = <25>; // in micro-seconds
 343
 344                         nand@0 {
 345                                 #address-cells = <1>;
 346                                 #size-cells = <1>;
 347
 348                                 partition@0 {
 349                                             label = "fs";
 350                                             reg = <0x00000000 0x01000000>;
 351                                 };
 352                         };
 353                 };
 354         };
 355
 356         pci0: pci@e0008000 {
 357                 cell-index = <0>;
 358                 #interrupt-cells = <1>;
 359                 #size-cells = <2>;
 360                 #address-cells = <3>;
 361                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 362                 device_type = "pci";
 363                 reg = <0xe0008000 0x1000>;
 364                 clock-frequency = <33333333>;
 365                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 366                 interrupt-map = <
 367                                 /* IDSEL 28 */
 368                                  0xe000 0 0 1 &mpic 2 1
 369                                  0xe000 0 0 2 &mpic 3 1>;
 370
 371                 interrupt-parent = <&mpic>;
 372                 interrupts = <24 2>;
 373                 bus-range = <0 0>;
 374                 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
 375                           0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
 376         };
 377
 378         pci1: pcie@e000a000 {
 379                 cell-index = <2>;
 380                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 381                 interrupt-map = <
 382                         /* IDSEL 0x0 (PEX) */
 383                         0x00000 0 0 1 &mpic 0 1
 384                         0x00000 0 0 2 &mpic 1 1
 385                         0x00000 0 0 3 &mpic 2 1
 386                         0x00000 0 0 4 &mpic 3 1>;
 387
 388                 interrupt-parent = <&mpic>;
 389                 interrupts = <26 2>;
 390                 bus-range = <0 0xff>;
 391                 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
 392                           0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
 393                 clock-frequency = <33333333>;
 394                 #interrupt-cells = <1>;
 395                 #size-cells = <2>;
 396                 #address-cells = <3>;
 397                 reg = <0xe000a000 0x1000>;
 398                 compatible = "fsl,mpc8548-pcie";
 399                 device_type = "pci";
 400                 pcie@0 {
 401                         reg = <0 0 0 0 0>;
 402                         #size-cells = <2>;
 403                         #address-cells = <3>;
 404                         device_type = "pci";
 405                         ranges = <0x02000000 0 0xc0000000 0x02000000 0
 406                                   0xc0000000 0 0x20000000
 407                                   0x01000000 0 0x00000000 0x01000000 0
 408                                   0x00000000 0 0x08000000>;
 409                 };
 410         };
 411 };