arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts

   1 /*
   2  * MPC8572 DS Core1 Device Tree Source in CAMP mode.
   3  *
   4  * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
   5  * can be shared, all the other devices must be assigned to one core only.
   6  * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
   7  *
   8  * Please note to add "-b 1" for core1's dts compiling.
   9  *
  10  * Copyright 2007-2009 Freescale Semiconductor Inc.
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 /dts-v1/;
  19 / {
  20         model = "fsl,MPC8572DS";
  21         compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
  22         #address-cells = <1>;
  23         #size-cells = <1>;
  24
  25         aliases {
  26                 ethernet2 = &enet2;
  27                 ethernet3 = &enet3;
  28                 serial0 = &serial0;
  29                 pci2 = &pci2;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 PowerPC,8572@1 {
  37                         device_type = "cpu";
  38                         reg = <0x1>;
  39                         d-cache-line-size = <32>;       // 32 bytes
  40                         i-cache-line-size = <32>;       // 32 bytes
  41                         d-cache-size = <0x8000>;                // L1, 32K
  42                         i-cache-size = <0x8000>;                // L1, 32K
  43                         timebase-frequency = <0>;
  44                         bus-frequency = <0>;
  45                         clock-frequency = <0>;
  46                         next-level-cache = <&L2>;
  47                 };
  48         };
  49
  50         memory {
  51                 device_type = "memory";
  52                 reg = <0x0 0x0>;        // Filled by U-Boot
  53         };
  54
  55         soc8572@ffe00000 {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 device_type = "soc";
  59                 compatible = "simple-bus";
  60                 ranges = <0x0 0xffe00000 0x100000>;
  61                 reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
  62                 bus-frequency = <0>;            // Filled out by uboot.
  63
  64                 L2: l2-cache-controller@20000 {
  65                         compatible = "fsl,mpc8572-l2-cache-controller";
  66                         reg = <0x20000 0x1000>;
  67                         cache-line-size = <32>; // 32 bytes
  68                         cache-size = <0x80000>; // L2, 512K
  69                         interrupt-parent = <&mpic>;
  70                 };
  71
  72                 dma@c300 {
  73                         #address-cells = <1>;
  74                         #size-cells = <1>;
  75                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
  76                         reg = <0xc300 0x4>;
  77                         ranges = <0x0 0xc100 0x200>;
  78                         cell-index = <0>;
  79                         dma-channel@0 {
  80                                 compatible = "fsl,mpc8572-dma-channel",
  81                                                 "fsl,eloplus-dma-channel";
  82                                 reg = <0x0 0x80>;
  83                                 cell-index = <0>;
  84                                 interrupt-parent = <&mpic>;
  85                                 interrupts = <76 2>;
  86                         };
  87                         dma-channel@80 {
  88                                 compatible = "fsl,mpc8572-dma-channel",
  89                                                 "fsl,eloplus-dma-channel";
  90                                 reg = <0x80 0x80>;
  91                                 cell-index = <1>;
  92                                 interrupt-parent = <&mpic>;
  93                                 interrupts = <77 2>;
  94                         };
  95                         dma-channel@100 {
  96                                 compatible = "fsl,mpc8572-dma-channel",
  97                                                 "fsl,eloplus-dma-channel";
  98                                 reg = <0x100 0x80>;
  99                                 cell-index = <2>;
 100                                 interrupt-parent = <&mpic>;
 101                                 interrupts = <78 2>;
 102                         };
 103                         dma-channel@180 {
 104                                 compatible = "fsl,mpc8572-dma-channel",
 105                                                 "fsl,eloplus-dma-channel";
 106                                 reg = <0x180 0x80>;
 107                                 cell-index = <3>;
 108                                 interrupt-parent = <&mpic>;
 109                                 interrupts = <79 2>;
 110                         };
 111                 };
 112
 113                 mdio@24520 {
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                         compatible = "fsl,gianfar-mdio";
 117                         reg = <0x24520 0x20>;
 118
 119                         phy2: ethernet-phy@2 {
 120                                 interrupt-parent = <&mpic>;
 121                                 reg = <0x2>;
 122                         };
 123                         phy3: ethernet-phy@3 {
 124                                 interrupt-parent = <&mpic>;
 125                                 reg = <0x3>;
 126                         };
 127                 };
 128
 129                 enet2: ethernet@26000 {
 130                         cell-index = <2>;
 131                         device_type = "network";
 132                         model = "eTSEC";
 133                         compatible = "gianfar";
 134                         reg = <0x26000 0x1000>;
 135                         local-mac-address = [ 00 00 00 00 00 00 ];
 136                         interrupts = <31 2 32 2 33 2>;
 137                         interrupt-parent = <&mpic>;
 138                         phy-handle = <&phy2>;
 139                         phy-connection-type = "rgmii-id";
 140                 };
 141
 142                 enet3: ethernet@27000 {
 143                         cell-index = <3>;
 144                         device_type = "network";
 145                         model = "eTSEC";
 146                         compatible = "gianfar";
 147                         reg = <0x27000 0x1000>;
 148                         local-mac-address = [ 00 00 00 00 00 00 ];
 149                         interrupts = <37 2 38 2 39 2>;
 150                         interrupt-parent = <&mpic>;
 151                         phy-handle = <&phy3>;
 152                         phy-connection-type = "rgmii-id";
 153                 };
 154
 155                 msi@41600 {
 156                         compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
 157                         reg = <0x41600 0x80>;
 158                         msi-available-ranges = <0 0x100>;
 159                         interrupts = <
 160                                 0xe0 0
 161                                 0xe1 0
 162                                 0xe2 0
 163                                 0xe3 0
 164                                 0xe4 0
 165                                 0xe5 0
 166                                 0xe6 0
 167                                 0xe7 0>;
 168                         interrupt-parent = <&mpic>;
 169                 };
 170
 171                 serial0: serial@4600 {
 172                         cell-index = <1>;
 173                         device_type = "serial";
 174                         compatible = "ns16550";
 175                         reg = <0x4600 0x100>;
 176                         clock-frequency = <0>;
 177                 };
 178
 179                 mpic: pic@40000 {
 180                         interrupt-controller;
 181                         #address-cells = <0>;
 182                         #interrupt-cells = <2>;
 183                         reg = <0x40000 0x40000>;
 184                         compatible = "chrp,open-pic";
 185                         device_type = "open-pic";
 186                         protected-sources = <
 187                         18 16 10 42 45 58       /* MEM L2 mdio serial crypto */
 188                         29 30 34 35 36 40       /* enet0 enet1 */
 189                         24 25 20 21 22 23       /* pci0 pci1 dma1 */
 190                         43                      /* i2c */
 191                         0x1 0x2 0x3 0x4         /* pci slot */
 192                         0x9 0xa 0xb 0xc         /* usb */
 193                         0x6 0x7 0xe 0x5         /* Audio elgacy SATA */
 194                         >;
 195                 };
 196         };
 197
 198         pci2: pcie@ffe0a000 {
 199                 cell-index = <2>;
 200                 compatible = "fsl,mpc8548-pcie";
 201                 device_type = "pci";
 202                 #interrupt-cells = <1>;
 203                 #size-cells = <2>;
 204                 #address-cells = <3>;
 205                 reg = <0xffe0a000 0x1000>;
 206                 bus-range = <0 255>;
 207                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 208                           0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
 209                 clock-frequency = <33333333>;
 210                 interrupt-parent = <&mpic>;
 211                 interrupts = <26 2>;
 212                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 213                 interrupt-map = <
 214                         /* IDSEL 0x0 */
 215                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 216                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 217                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 218                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 219                         >;
 220                 pcie@0 {
 221                         reg = <0x0 0x0 0x0 0x0 0x0>;
 222                         #size-cells = <2>;
 223                         #address-cells = <3>;
 224                         device_type = "pci";
 225                         ranges = <0x2000000 0x0 0xc0000000
 226                                   0x2000000 0x0 0xc0000000
 227                                   0x0 0x20000000
 228
 229                                   0x1000000 0x0 0x0
 230                                   0x1000000 0x0 0x0
 231                                   0x0 0x10000>;
 232                 };
 233         };
 234 };