arch/powerpc/boot/dts/mpc8572ds.dts

   1 /*
   2  * MPC8572 DS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "fsl,MPC8572DS";
  14         compatible = "fsl,MPC8572DS";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         aliases {
  19                 ethernet0 = &enet0;
  20                 ethernet1 = &enet1;
  21                 ethernet2 = &enet2;
  22                 ethernet3 = &enet3;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27                 pci2 = &pci2;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8572@0 {
  35                         device_type = "cpu";
  36                         reg = <0>;
  37                         d-cache-line-size = <20>;       // 32 bytes
  38                         i-cache-line-size = <20>;       // 32 bytes
  39                         d-cache-size = <8000>;          // L1, 32K
  40                         i-cache-size = <8000>;          // L1, 32K
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                 };
  45
  46                 PowerPC,8572@1 {
  47                         device_type = "cpu";
  48                         reg = <1>;
  49                         d-cache-line-size = <20>;       // 32 bytes
  50                         i-cache-line-size = <20>;       // 32 bytes
  51                         d-cache-size = <8000>;          // L1, 32K
  52                         i-cache-size = <8000>;          // L1, 32K
  53                         timebase-frequency = <0>;
  54                         bus-frequency = <0>;
  55                         clock-frequency = <0>;
  56                 };
  57         };
  58
  59         memory {
  60                 device_type = "memory";
  61                 reg = <00000000 00000000>;      // Filled by U-Boot
  62         };
  63
  64         soc8572@ffe00000 {
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 device_type = "soc";
  68                 ranges = <00000000 ffe00000 00100000>;
  69                 reg = <ffe00000 00001000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
  70                 bus-frequency = <0>;            // Filled out by uboot.
  71
  72                 memory-controller@2000 {
  73                         compatible = "fsl,mpc8572-memory-controller";
  74                         reg = <2000 1000>;
  75                         interrupt-parent = <&mpic>;
  76                         interrupts = <12 2>;
  77                 };
  78
  79                 memory-controller@6000 {
  80                         compatible = "fsl,mpc8572-memory-controller";
  81                         reg = <6000 1000>;
  82                         interrupt-parent = <&mpic>;
  83                         interrupts = <12 2>;
  84                 };
  85
  86                 l2-cache-controller@20000 {
  87                         compatible = "fsl,mpc8572-l2-cache-controller";
  88                         reg = <20000 1000>;
  89                         cache-line-size = <20>; // 32 bytes
  90                         cache-size = <80000>;   // L2, 512K
  91                         interrupt-parent = <&mpic>;
  92                         interrupts = <10 2>;
  93                 };
  94
  95                 i2c@3000 {
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                         cell-index = <0>;
  99                         compatible = "fsl-i2c";
 100                         reg = <3000 100>;
 101                         interrupts = <2b 2>;
 102                         interrupt-parent = <&mpic>;
 103                         dfsrr;
 104                 };
 105
 106                 i2c@3100 {
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109                         cell-index = <1>;
 110                         compatible = "fsl-i2c";
 111                         reg = <3100 100>;
 112                         interrupts = <2b 2>;
 113                         interrupt-parent = <&mpic>;
 114                         dfsrr;
 115                 };
 116
 117                 mdio@24520 {
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         compatible = "fsl,gianfar-mdio";
 121                         reg = <24520 20>;
 122
 123                         phy0: ethernet-phy@0 {
 124                                 interrupt-parent = <&mpic>;
 125                                 interrupts = <a 1>;
 126                                 reg = <0>;
 127                         };
 128                         phy1: ethernet-phy@1 {
 129                                 interrupt-parent = <&mpic>;
 130                                 interrupts = <a 1>;
 131                                 reg = <1>;
 132                         };
 133                         phy2: ethernet-phy@2 {
 134                                 interrupt-parent = <&mpic>;
 135                                 interrupts = <a 1>;
 136                                 reg = <2>;
 137                         };
 138                         phy3: ethernet-phy@3 {
 139                                 interrupt-parent = <&mpic>;
 140                                 interrupts = <a 1>;
 141                                 reg = <3>;
 142                         };
 143                 };
 144
 145                 enet0: ethernet@24000 {
 146                         cell-index = <0>;
 147                         device_type = "network";
 148                         model = "eTSEC";
 149                         compatible = "gianfar";
 150                         reg = <24000 1000>;
 151                         local-mac-address = [ 00 00 00 00 00 00 ];
 152                         interrupts = <1d 2 1e 2 22 2>;
 153                         interrupt-parent = <&mpic>;
 154                         phy-handle = <&phy0>;
 155                         phy-connection-type = "rgmii-id";
 156                 };
 157
 158                 enet1: ethernet@25000 {
 159                         cell-index = <1>;
 160                         device_type = "network";
 161                         model = "eTSEC";
 162                         compatible = "gianfar";
 163                         reg = <25000 1000>;
 164                         local-mac-address = [ 00 00 00 00 00 00 ];
 165                         interrupts = <23 2 24 2 28 2>;
 166                         interrupt-parent = <&mpic>;
 167                         phy-handle = <&phy1>;
 168                         phy-connection-type = "rgmii-id";
 169                 };
 170
 171                 enet2: ethernet@26000 {
 172                         cell-index = <2>;
 173                         device_type = "network";
 174                         model = "eTSEC";
 175                         compatible = "gianfar";
 176                         reg = <26000 1000>;
 177                         local-mac-address = [ 00 00 00 00 00 00 ];
 178                         interrupts = <1f 2 20 2 21 2>;
 179                         interrupt-parent = <&mpic>;
 180                         phy-handle = <&phy2>;
 181                         phy-connection-type = "rgmii-id";
 182                 };
 183
 184                 enet3: ethernet@27000 {
 185                         cell-index = <3>;
 186                         device_type = "network";
 187                         model = "eTSEC";
 188                         compatible = "gianfar";
 189                         reg = <27000 1000>;
 190                         local-mac-address = [ 00 00 00 00 00 00 ];
 191                         interrupts = <25 2 26 2 27 2>;
 192                         interrupt-parent = <&mpic>;
 193                         phy-handle = <&phy3>;
 194                         phy-connection-type = "rgmii-id";
 195                 };
 196
 197                 serial0: serial@4500 {
 198                         cell-index = <0>;
 199                         device_type = "serial";
 200                         compatible = "ns16550";
 201                         reg = <4500 100>;
 202                         clock-frequency = <0>;
 203                         interrupts = <2a 2>;
 204                         interrupt-parent = <&mpic>;
 205                 };
 206
 207                 serial1: serial@4600 {
 208                         cell-index = <1>;
 209                         device_type = "serial";
 210                         compatible = "ns16550";
 211                         reg = <4600 100>;
 212                         clock-frequency = <0>;
 213                         interrupts = <2a 2>;
 214                         interrupt-parent = <&mpic>;
 215                 };
 216
 217                 global-utilities@e0000 {        //global utilities block
 218                         compatible = "fsl,mpc8572-guts";
 219                         reg = <e0000 1000>;
 220                         fsl,has-rstcr;
 221                 };
 222
 223                 mpic: pic@40000 {
 224                         clock-frequency = <0>;
 225                         interrupt-controller;
 226                         #address-cells = <0>;
 227                         #interrupt-cells = <2>;
 228                         reg = <40000 40000>;
 229                         compatible = "chrp,open-pic";
 230                         device_type = "open-pic";
 231                         big-endian;
 232                 };
 233         };
 234
 235         pci0: pcie@ffe08000 {
 236                 cell-index = <0>;
 237                 compatible = "fsl,mpc8548-pcie";
 238                 device_type = "pci";
 239                 #interrupt-cells = <1>;
 240                 #size-cells = <2>;
 241                 #address-cells = <3>;
 242                 reg = <ffe08000 1000>;
 243                 bus-range = <0 ff>;
 244                 ranges = <02000000 0 80000000 80000000 0 20000000
 245                           01000000 0 00000000 ffc00000 0 00010000>;
 246                 clock-frequency = <1fca055>;
 247                 interrupt-parent = <&mpic>;
 248                 interrupts = <18 2>;
 249                 interrupt-map-mask = <ff00 0 0 7>;
 250                 interrupt-map = <
 251                         /* IDSEL 0x11 func 0 - PCI slot 1 */
 252                         8800 0 0 1 &mpic 2 1
 253                         8800 0 0 2 &mpic 3 1
 254                         8800 0 0 3 &mpic 4 1
 255                         8800 0 0 4 &mpic 1 1
 256
 257                         /* IDSEL 0x11 func 1 - PCI slot 1 */
 258                         8900 0 0 1 &mpic 2 1
 259                         8900 0 0 2 &mpic 3 1
 260                         8900 0 0 3 &mpic 4 1
 261                         8900 0 0 4 &mpic 1 1
 262
 263                         /* IDSEL 0x11 func 2 - PCI slot 1 */
 264                         8a00 0 0 1 &mpic 2 1
 265                         8a00 0 0 2 &mpic 3 1
 266                         8a00 0 0 3 &mpic 4 1
 267                         8a00 0 0 4 &mpic 1 1
 268
 269                         /* IDSEL 0x11 func 3 - PCI slot 1 */
 270                         8b00 0 0 1 &mpic 2 1
 271                         8b00 0 0 2 &mpic 3 1
 272                         8b00 0 0 3 &mpic 4 1
 273                         8b00 0 0 4 &mpic 1 1
 274
 275                         /* IDSEL 0x11 func 4 - PCI slot 1 */
 276                         8c00 0 0 1 &mpic 2 1
 277                         8c00 0 0 2 &mpic 3 1
 278                         8c00 0 0 3 &mpic 4 1
 279                         8c00 0 0 4 &mpic 1 1
 280
 281                         /* IDSEL 0x11 func 5 - PCI slot 1 */
 282                         8d00 0 0 1 &mpic 2 1
 283                         8d00 0 0 2 &mpic 3 1
 284                         8d00 0 0 3 &mpic 4 1
 285                         8d00 0 0 4 &mpic 1 1
 286
 287                         /* IDSEL 0x11 func 6 - PCI slot 1 */
 288                         8e00 0 0 1 &mpic 2 1
 289                         8e00 0 0 2 &mpic 3 1
 290                         8e00 0 0 3 &mpic 4 1
 291                         8e00 0 0 4 &mpic 1 1
 292
 293                         /* IDSEL 0x11 func 7 - PCI slot 1 */
 294                         8f00 0 0 1 &mpic 2 1
 295                         8f00 0 0 2 &mpic 3 1
 296                         8f00 0 0 3 &mpic 4 1
 297                         8f00 0 0 4 &mpic 1 1
 298
 299                         /* IDSEL 0x12 func 0 - PCI slot 2 */
 300                         9000 0 0 1 &mpic 3 1
 301                         9000 0 0 2 &mpic 4 1
 302                         9000 0 0 3 &mpic 1 1
 303                         9000 0 0 4 &mpic 2 1
 304
 305                         /* IDSEL 0x12 func 1 - PCI slot 2 */
 306                         9100 0 0 1 &mpic 3 1
 307                         9100 0 0 2 &mpic 4 1
 308                         9100 0 0 3 &mpic 1 1
 309                         9100 0 0 4 &mpic 2 1
 310
 311                         /* IDSEL 0x12 func 2 - PCI slot 2 */
 312                         9200 0 0 1 &mpic 3 1
 313                         9200 0 0 2 &mpic 4 1
 314                         9200 0 0 3 &mpic 1 1
 315                         9200 0 0 4 &mpic 2 1
 316
 317                         /* IDSEL 0x12 func 3 - PCI slot 2 */
 318                         9300 0 0 1 &mpic 3 1
 319                         9300 0 0 2 &mpic 4 1
 320                         9300 0 0 3 &mpic 1 1
 321                         9300 0 0 4 &mpic 2 1
 322
 323                         /* IDSEL 0x12 func 4 - PCI slot 2 */
 324                         9400 0 0 1 &mpic 3 1
 325                         9400 0 0 2 &mpic 4 1
 326                         9400 0 0 3 &mpic 1 1
 327                         9400 0 0 4 &mpic 2 1
 328
 329                         /* IDSEL 0x12 func 5 - PCI slot 2 */
 330                         9500 0 0 1 &mpic 3 1
 331                         9500 0 0 2 &mpic 4 1
 332                         9500 0 0 3 &mpic 1 1
 333                         9500 0 0 4 &mpic 2 1
 334
 335                         /* IDSEL 0x12 func 6 - PCI slot 2 */
 336                         9600 0 0 1 &mpic 3 1
 337                         9600 0 0 2 &mpic 4 1
 338                         9600 0 0 3 &mpic 1 1
 339                         9600 0 0 4 &mpic 2 1
 340
 341                         /* IDSEL 0x12 func 7 - PCI slot 2 */
 342                         9700 0 0 1 &mpic 3 1
 343                         9700 0 0 2 &mpic 4 1
 344                         9700 0 0 3 &mpic 1 1
 345                         9700 0 0 4 &mpic 2 1
 346
 347                         // IDSEL 0x1c  USB
 348                         e000 0 0 1 &i8259 c 2
 349                         e100 0 0 2 &i8259 9 2
 350                         e200 0 0 3 &i8259 a 2
 351                         e300 0 0 4 &i8259 b 2
 352
 353                         // IDSEL 0x1d  Audio
 354                         e800 0 0 1 &i8259 6 2
 355
 356                         // IDSEL 0x1e Legacy
 357                         f000 0 0 1 &i8259 7 2
 358                         f100 0 0 1 &i8259 7 2
 359
 360                         // IDSEL 0x1f IDE/SATA
 361                         f800 0 0 1 &i8259 e 2
 362                         f900 0 0 1 &i8259 5 2
 363
 364                         >;
 365
 366                 pcie@0 {
 367                         reg = <0 0 0 0 0>;
 368                         #size-cells = <2>;
 369                         #address-cells = <3>;
 370                         device_type = "pci";
 371                         ranges = <02000000 0 80000000
 372                                   02000000 0 80000000
 373                                   0 20000000
 374
 375                                   01000000 0 00000000
 376                                   01000000 0 00000000
 377                                   0 00100000>;
 378                         uli1575@0 {
 379                                 reg = <0 0 0 0 0>;
 380                                 #size-cells = <2>;
 381                                 #address-cells = <3>;
 382                                 ranges = <02000000 0 80000000
 383                                           02000000 0 80000000
 384                                           0 20000000
 385
 386                                           01000000 0 00000000
 387                                           01000000 0 00000000
 388                                           0 00100000>;
 389                                 isa@1e {
 390                                         device_type = "isa";
 391                                         #interrupt-cells = <2>;
 392                                         #size-cells = <1>;
 393                                         #address-cells = <2>;
 394                                         reg = <f000 0 0 0 0>;
 395                                         ranges = <1 0 01000000 0 0
 396                                                   00001000>;
 397                                         interrupt-parent = <&i8259>;
 398
 399                                         i8259: interrupt-controller@20 {
 400                                                 reg = <1 20 2
 401                                                        1 a0 2
 402                                                        1 4d0 2>;
 403                                                 interrupt-controller;
 404                                                 device_type = "interrupt-controller";
 405                                                 #address-cells = <0>;
 406                                                 #interrupt-cells = <2>;
 407                                                 compatible = "chrp,iic";
 408                                                 interrupts = <9 2>;
 409                                                 interrupt-parent = <&mpic>;
 410                                         };
 411
 412                                         i8042@60 {
 413                                                 #size-cells = <0>;
 414                                                 #address-cells = <1>;
 415                                                 reg = <1 60 1 1 64 1>;
 416                                                 interrupts = <1 3 c 3>;
 417                                                 interrupt-parent =
 418                                                         <&i8259>;
 419
 420                                                 keyboard@0 {
 421                                                         reg = <0>;
 422                                                         compatible = "pnpPNP,303";
 423                                                 };
 424
 425                                                 mouse@1 {
 426                                                         reg = <1>;
 427                                                         compatible = "pnpPNP,f03";
 428                                                 };
 429                                         };
 430
 431                                         rtc@70 {
 432                                                 compatible = "pnpPNP,b00";
 433                                                 reg = <1 70 2>;
 434                                         };
 435
 436                                         gpio@400 {
 437                                                 reg = <1 400 80>;
 438                                         };
 439                                 };
 440                         };
 441                 };
 442
 443         };
 444
 445         pci1: pcie@ffe09000 {
 446                 cell-index = <1>;
 447                 compatible = "fsl,mpc8548-pcie";
 448                 device_type = "pci";
 449                 #interrupt-cells = <1>;
 450                 #size-cells = <2>;
 451                 #address-cells = <3>;
 452                 reg = <ffe09000 1000>;
 453                 bus-range = <0 ff>;
 454                 ranges = <02000000 0 a0000000 a0000000 0 20000000
 455                           01000000 0 00000000 ffc10000 0 00010000>;
 456                 clock-frequency = <1fca055>;
 457                 interrupt-parent = <&mpic>;
 458                 interrupts = <1a 2>;
 459                 interrupt-map-mask = <f800 0 0 7>;
 460                 interrupt-map = <
 461                         /* IDSEL 0x0 */
 462                         0000 0 0 1 &mpic 4 1
 463                         0000 0 0 2 &mpic 5 1
 464                         0000 0 0 3 &mpic 6 1
 465                         0000 0 0 4 &mpic 7 1
 466                         >;
 467                 pcie@0 {
 468                         reg = <0 0 0 0 0>;
 469                         #size-cells = <2>;
 470                         #address-cells = <3>;
 471                         device_type = "pci";
 472                         ranges = <02000000 0 a0000000
 473                                   02000000 0 a0000000
 474                                   0 20000000
 475
 476                                   01000000 0 00000000
 477                                   01000000 0 00000000
 478                                   0 00100000>;
 479                 };
 480         };
 481
 482         pci2: pcie@ffe0a000 {
 483                 cell-index = <2>;
 484                 compatible = "fsl,mpc8548-pcie";
 485                 device_type = "pci";
 486                 #interrupt-cells = <1>;
 487                 #size-cells = <2>;
 488                 #address-cells = <3>;
 489                 reg = <ffe0a000 1000>;
 490                 bus-range = <0 ff>;
 491                 ranges = <02000000 0 c0000000 c0000000 0 20000000
 492                           01000000 0 00000000 ffc20000 0 00010000>;
 493                 clock-frequency = <1fca055>;
 494                 interrupt-parent = <&mpic>;
 495                 interrupts = <1b 2>;
 496                 interrupt-map-mask = <f800 0 0 7>;
 497                 interrupt-map = <
 498                         /* IDSEL 0x0 */
 499                         0000 0 0 1 &mpic 0 1
 500                         0000 0 0 2 &mpic 1 1
 501                         0000 0 0 3 &mpic 2 1
 502                         0000 0 0 4 &mpic 3 1
 503                         >;
 504                 pcie@0 {
 505                         reg = <0 0 0 0 0>;
 506                         #size-cells = <2>;
 507                         #address-cells = <3>;
 508                         device_type = "pci";
 509                         ranges = <02000000 0 c0000000
 510                                   02000000 0 c0000000
 511                                   0 20000000
 512
 513                                   01000000 0 00000000
 514                                   01000000 0 00000000
 515                                   0 00100000>;
 516                 };
 517         };
 518 };