arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 /*
  14 /memreserve/    00000000 1000000;
  15 */
  16
  17 / {
  18         model = "MPC8568EMDS";
  19         compatible = "MPC8568EMDS", "MPC85xxMDS";
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         cpus {
  24                 #cpus = <1>;
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 PowerPC,8568@0 {
  29                         device_type = "cpu";
  30                         reg = <0>;
  31                         d-cache-line-size = <20>;       // 32 bytes
  32                         i-cache-line-size = <20>;       // 32 bytes
  33                         d-cache-size = <8000>;          // L1, 32K
  34                         i-cache-size = <8000>;          // L1, 32K
  35                         timebase-frequency = <0>;
  36                         bus-frequency = <0>;
  37                         clock-frequency = <0>;
  38                         32-bit;
  39                 };
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44                 reg = <00000000 10000000>;
  45         };
  46
  47         bcsr@f8000000 {
  48                 device_type = "board-control";
  49                 reg = <f8000000 8000>;
  50         };
  51
  52         soc8568@e0000000 {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 #interrupt-cells = <2>;
  56                 device_type = "soc";
  57                 ranges = <0 e0000000 00100000>;
  58                 reg = <e0000000 00100000>;
  59                 bus-frequency = <0>;
  60
  61                 i2c@3000 {
  62                         device_type = "i2c";
  63                         compatible = "fsl-i2c";
  64                         reg = <3000 100>;
  65                         interrupts = <1b 2>;
  66                         interrupt-parent = <&mpic>;
  67                         dfsrr;
  68                 };
  69
  70                 i2c@3100 {
  71                         device_type = "i2c";
  72                         compatible = "fsl-i2c";
  73                         reg = <3100 100>;
  74                         interrupts = <1b 2>;
  75                         interrupt-parent = <&mpic>;
  76                         dfsrr;
  77                 };
  78
  79                 mdio@24520 {
  80                         #address-cells = <1>;
  81                         #size-cells = <0>;
  82                         device_type = "mdio";
  83                         compatible = "gianfar";
  84                         reg = <24520 20>;
  85                         phy0: ethernet-phy@0 {
  86                                 interrupt-parent = <&mpic>;
  87                                 interrupts = <31 1>;
  88                                 reg = <0>;
  89                                 device_type = "ethernet-phy";
  90                         };
  91                         phy1: ethernet-phy@1 {
  92                                 interrupt-parent = <&mpic>;
  93                                 interrupts = <32 1>;
  94                                 reg = <1>;
  95                                 device_type = "ethernet-phy";
  96                         };
  97                         phy2: ethernet-phy@2 {
  98                                 interrupt-parent = <&mpic>;
  99                                 interrupts = <31 1>;
 100                                 reg = <2>;
 101                                 device_type = "ethernet-phy";
 102                         };
 103                         phy3: ethernet-phy@3 {
 104                                 interrupt-parent = <&mpic>;
 105                                 interrupts = <32 1>;
 106                                 reg = <3>;
 107                                 device_type = "ethernet-phy";
 108                         };
 109                 };
 110
 111                 ethernet@24000 {
 112                         #address-cells = <1>;
 113                         #size-cells = <0>;
 114                         device_type = "network";
 115                         model = "eTSEC";
 116                         compatible = "gianfar";
 117                         reg = <24000 1000>;
 118                         mac-address = [ 00 00 00 00 00 00 ];
 119                         interrupts = <d 2 e 2 12 2>;
 120                         interrupt-parent = <&mpic>;
 121                         phy-handle = <&phy2>;
 122                 };
 123
 124                 ethernet@25000 {
 125                         #address-cells = <1>;
 126                         #size-cells = <0>;
 127                         device_type = "network";
 128                         model = "eTSEC";
 129                         compatible = "gianfar";
 130                         reg = <25000 1000>;
 131                         mac-address = [ 00 00 00 00 00 00];
 132                         interrupts = <13 2 14 2 18 2>;
 133                         interrupt-parent = <&mpic>;
 134                         phy-handle = <&phy3>;
 135                 };
 136
 137                 serial@4500 {
 138                         device_type = "serial";
 139                         compatible = "ns16550";
 140                         reg = <4500 100>;
 141                         clock-frequency = <0>;
 142                         interrupts = <1a 2>;
 143                         interrupt-parent = <&mpic>;
 144                 };
 145
 146                 serial@4600 {
 147                         device_type = "serial";
 148                         compatible = "ns16550";
 149                         reg = <4600 100>;
 150                         clock-frequency = <0>;
 151                         interrupts = <1a 2>;
 152                         interrupt-parent = <&mpic>;
 153                 };
 154
 155                 crypto@30000 {
 156                         device_type = "crypto";
 157                         model = "SEC2";
 158                         compatible = "talitos";
 159                         reg = <30000 f000>;
 160                         interrupts = <1d 2>;
 161                         interrupt-parent = <&mpic>;
 162                         num-channels = <4>;
 163                         channel-fifo-len = <18>;
 164                         exec-units-mask = <000000fe>;
 165                         descriptor-types-mask = <012b0ebf>;
 166                 };
 167
 168                 mpic: pic@40000 {
 169                         clock-frequency = <0>;
 170                         interrupt-controller;
 171                         #address-cells = <0>;
 172                         #interrupt-cells = <2>;
 173                         reg = <40000 40000>;
 174                         built-in;
 175                         compatible = "chrp,open-pic";
 176                         device_type = "open-pic";
 177                         big-endian;
 178                 };
 179                 par_io@e0100 {
 180                         reg = <e0100 100>;
 181                         device_type = "par_io";
 182                         num-ports = <7>;
 183
 184                         pio1: ucc_pin@01 {
 185                                 pio-map = <
 186                         /* port  pin  dir  open_drain  assignment  has_irq */
 187                                         4  0a  1  0  2  0       /* TxD0 */
 188                                         4  09  1  0  2  0       /* TxD1 */
 189                                         4  08  1  0  2  0       /* TxD2 */
 190                                         4  07  1  0  2  0       /* TxD3 */
 191                                         4  17  1  0  2  0       /* TxD4 */
 192                                         4  16  1  0  2  0       /* TxD5 */
 193                                         4  15  1  0  2  0       /* TxD6 */
 194                                         4  14  1  0  2  0       /* TxD7 */
 195                                         4  0f  2  0  2  0       /* RxD0 */
 196                                         4  0e  2  0  2  0       /* RxD1 */
 197                                         4  0d  2  0  2  0       /* RxD2 */
 198                                         4  0c  2  0  2  0       /* RxD3 */
 199                                         4  1d  2  0  2  0       /* RxD4 */
 200                                         4  1c  2  0  2  0       /* RxD5 */
 201                                         4  1b  2  0  2  0       /* RxD6 */
 202                                         4  1a  2  0  2  0       /* RxD7 */
 203                                         4  0b  1  0  2  0       /* TX_EN */
 204                                         4  18  1  0  2  0       /* TX_ER */
 205                                         4  0f  2  0  2  0       /* RX_DV */
 206                                         4  1e  2  0  2  0       /* RX_ER */
 207                                         4  11  2  0  2  0       /* RX_CLK */
 208                                         4  13  1  0  2  0       /* GTX_CLK */
 209                                         1  1f  2  0  3  0>;     /* GTX125 */
 210                         };
 211                         pio2: ucc_pin@02 {
 212                                 pio-map = <
 213                         /* port  pin  dir  open_drain  assignment  has_irq */
 214                                         5  0a 1  0  2  0   /* TxD0 */
 215                                         5  09 1  0  2  0   /* TxD1 */
 216                                         5  08 1  0  2  0   /* TxD2 */
 217                                         5  07 1  0  2  0   /* TxD3 */
 218                                         5  17 1  0  2  0   /* TxD4 */
 219                                         5  16 1  0  2  0   /* TxD5 */
 220                                         5  15 1  0  2  0   /* TxD6 */
 221                                         5  14 1  0  2  0   /* TxD7 */
 222                                         5  0f 2  0  2  0   /* RxD0 */
 223                                         5  0e 2  0  2  0   /* RxD1 */
 224                                         5  0d 2  0  2  0   /* RxD2 */
 225                                         5  0c 2  0  2  0   /* RxD3 */
 226                                         5  1d 2  0  2  0   /* RxD4 */
 227                                         5  1c 2  0  2  0   /* RxD5 */
 228                                         5  1b 2  0  2  0   /* RxD6 */
 229                                         5  1a 2  0  2  0   /* RxD7 */
 230                                         5  0b 1  0  2  0   /* TX_EN */
 231                                         5  18 1  0  2  0   /* TX_ER */
 232                                         5  10 2  0  2  0   /* RX_DV */
 233                                         5  1e 2  0  2  0   /* RX_ER */
 234                                         5  11 2  0  2  0   /* RX_CLK */
 235                                         5  13 1  0  2  0   /* GTX_CLK */
 236                                         1  1f 2  0  3  0   /* GTX125 */
 237                                         4  06 3  0  2  0   /* MDIO */
 238                                         4  05 1  0  2  0>; /* MDC */
 239                         };
 240                 };
 241         };
 242
 243         qe@e0080000 {
 244                 #address-cells = <1>;
 245                 #size-cells = <1>;
 246                 device_type = "qe";
 247                 model = "QE";
 248                 ranges = <0 e0080000 00040000>;
 249                 reg = <e0080000 480>;
 250                 brg-frequency = <0>;
 251                 bus-frequency = <179A7B00>;
 252
 253                 muram@10000 {
 254                         device_type = "muram";
 255                         ranges = <0 00010000 0000c000>;
 256
 257                         data-only@0{
 258                                 reg = <0 c000>;
 259                         };
 260                 };
 261
 262                 spi@4c0 {
 263                         device_type = "spi";
 264                         compatible = "fsl_spi";
 265                         reg = <4c0 40>;
 266                         interrupts = <2>;
 267                         interrupt-parent = <&qeic>;
 268                         mode = "cpu";
 269                 };
 270
 271                 spi@500 {
 272                         device_type = "spi";
 273                         compatible = "fsl_spi";
 274                         reg = <500 40>;
 275                         interrupts = <1>;
 276                         interrupt-parent = <&qeic>;
 277                         mode = "cpu";
 278                 };
 279
 280                 ucc@2000 {
 281                         device_type = "network";
 282                         compatible = "ucc_geth";
 283                         model = "UCC";
 284                         device-id = <1>;
 285                         reg = <2000 200>;
 286                         interrupts = <20>;
 287                         interrupt-parent = <&qeic>;
 288                         mac-address = [ 00 04 9f 00 23 23 ];
 289                         rx-clock = <0>;
 290                         tx-clock = <19>;
 291                         phy-handle = <&qe_phy0>;
 292                         pio-handle = <&pio1>;
 293                 };
 294
 295                 ucc@3000 {
 296                         device_type = "network";
 297                         compatible = "ucc_geth";
 298                         model = "UCC";
 299                         device-id = <2>;
 300                         reg = <3000 200>;
 301                         interrupts = <21>;
 302                         interrupt-parent = <&qeic>;
 303                         mac-address = [ 00 11 22 33 44 55 ];
 304                         rx-clock = <0>;
 305                         tx-clock = <14>;
 306                         phy-handle = <&qe_phy1>;
 307                         pio-handle = <&pio2>;
 308                 };
 309
 310                 mdio@2120 {
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         reg = <2120 18>;
 314                         device_type = "mdio";
 315                         compatible = "ucc_geth_phy";
 316
 317                         /* These are the same PHYs as on
 318                          * gianfar's MDIO bus */
 319                         qe_phy0: ethernet-phy@00 {
 320                                 interrupt-parent = <&mpic>;
 321                                 interrupts = <31 1>;
 322                                 reg = <0>;
 323                                 device_type = "ethernet-phy";
 324                                 interface = <6>; //ENET_1000_GMII
 325                         };
 326                         qe_phy1: ethernet-phy@01 {
 327                                 interrupt-parent = <&mpic>;
 328                                 interrupts = <32 1>;
 329                                 reg = <1>;
 330                                 device_type = "ethernet-phy";
 331                                 interface = <6>;
 332                         };
 333                         qe_phy2: ethernet-phy@02 {
 334                                 interrupt-parent = <&mpic>;
 335                                 interrupts = <31 1>;
 336                                 reg = <2>;
 337                                 device_type = "ethernet-phy";
 338                                 interface = <6>; //ENET_1000_GMII
 339                         };
 340                         qe_phy3: ethernet-phy@03 {
 341                                 interrupt-parent = <&mpic>;
 342                                 interrupts = <32 1>;
 343                                 reg = <3>;
 344                                 device_type = "ethernet-phy";
 345                                 interface = <6>; //ENET_1000_GMII
 346                         };
 347                 };
 348
 349                 qeic: qeic@80 {
 350                         interrupt-controller;
 351                         device_type = "qeic";
 352                         #address-cells = <0>;
 353                         #interrupt-cells = <1>;
 354                         reg = <80 80>;
 355                         built-in;
 356                         big-endian;
 357                         interrupts = <1e 2 1e 2>; //high:30 low:30
 358                         interrupt-parent = <&mpic>;
 359                 };
 360
 361         };
 362 };