arch/powerpc/boot/dts/mpc832x_rdb.dts

   1 /*
   2  * MPC832x RDB Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "MPC8323ERDB";
  14         compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 PowerPC,8323@0 {
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         d-cache-line-size = <20>;       // 32 bytes
  26                         i-cache-line-size = <20>;       // 32 bytes
  27                         d-cache-size = <4000>;          // L1, 16K
  28                         i-cache-size = <4000>;          // L1, 16K
  29                         timebase-frequency = <0>;
  30                         bus-frequency = <0>;
  31                         clock-frequency = <0>;
  32                         32-bit;
  33                 };
  34         };
  35
  36         memory {
  37                 device_type = "memory";
  38                 reg = <00000000 04000000>;
  39         };
  40
  41         soc8323@e0000000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 #interrupt-cells = <2>;
  45                 device_type = "soc";
  46                 ranges = <0 e0000000 00100000>;
  47                 reg = <e0000000 00000200>;
  48                 bus-frequency = <0>;
  49
  50                 wdt@200 {
  51                         device_type = "watchdog";
  52                         compatible = "mpc83xx_wdt";
  53                         reg = <200 100>;
  54                 };
  55
  56                 i2c@3000 {
  57                         device_type = "i2c";
  58                         compatible = "fsl-i2c";
  59                         reg = <3000 100>;
  60                         interrupts = <e 8>;
  61                         interrupt-parent = <&pic>;
  62                         dfsrr;
  63                 };
  64
  65                 serial@4500 {
  66                         device_type = "serial";
  67                         compatible = "ns16550";
  68                         reg = <4500 100>;
  69                         clock-frequency = <0>;
  70                         interrupts = <9 8>;
  71                         interrupt-parent = <&pic>;
  72                 };
  73
  74                 serial@4600 {
  75                         device_type = "serial";
  76                         compatible = "ns16550";
  77                         reg = <4600 100>;
  78                         clock-frequency = <0>;
  79                         interrupts = <a 8>;
  80                         interrupt-parent = <&pic>;
  81                 };
  82
  83                 crypto@30000 {
  84                         device_type = "crypto";
  85                         model = "SEC2";
  86                         compatible = "talitos";
  87                         reg = <30000 7000>;
  88                         interrupts = <b 8>;
  89                         interrupt-parent = <&pic>;
  90                         /* Rev. 2.2 */
  91                         num-channels = <1>;
  92                         channel-fifo-len = <18>;
  93                         exec-units-mask = <0000004c>;
  94                         descriptor-types-mask = <0122003f>;
  95                 };
  96
  97                 pci@8500 {
  98                         interrupt-map-mask = <f800 0 0 7>;
  99                         interrupt-map = <
 100                                         /* IDSEL 0x10 AD16 (USB) */
 101                                          8000 0 0 1 &pic 11 8
 102
 103                                         /* IDSEL 0x11 AD17 (Mini1)*/
 104                                          8800 0 0 1 &pic 12 8
 105                                          8800 0 0 2 &pic 13 8
 106                                          8800 0 0 3 &pic 14 8
 107                                          8800 0 0 4 &pic 30 8
 108
 109                                         /* IDSEL 0x12 AD18 (PCI/Mini2) */
 110                                          9000 0 0 1 &pic 13 8
 111                                          9000 0 0 2 &pic 14 8
 112                                          9000 0 0 3 &pic 30 8
 113                                          9000 0 0 4 &pic 11 8>;
 114
 115                         interrupt-parent = <&pic>;
 116                         interrupts = <42 8>;
 117                         bus-range = <0 0>;
 118                         ranges = <42000000 0 80000000 80000000 0 10000000
 119                                   02000000 0 90000000 90000000 0 10000000
 120                                   01000000 0 d0000000 d0000000 0 04000000>;
 121                         clock-frequency = <0>;
 122                         #interrupt-cells = <1>;
 123                         #size-cells = <2>;
 124                         #address-cells = <3>;
 125                         reg = <8500 100>;
 126                         compatible = "83xx";
 127                         device_type = "pci";
 128                 };
 129
 130                 pic:pic@700 {
 131                         interrupt-controller;
 132                         #address-cells = <0>;
 133                         #interrupt-cells = <2>;
 134                         reg = <700 100>;
 135                         built-in;
 136                         device_type = "ipic";
 137                 };
 138
 139                 par_io@1400 {
 140                         reg = <1400 100>;
 141                         device_type = "par_io";
 142                         num-ports = <7>;
 143
 144                         ucc2pio:ucc_pin@02 {
 145                                 pio-map = <
 146                         /* port  pin  dir  open_drain  assignment  has_irq */
 147                                         3  4  3  0  2  0        /* MDIO */
 148                                         3  5  1  0  2  0        /* MDC */
 149                                         3 15  2  0  1  0        /* RX_CLK (CLK16) */
 150                                         3 17  2  0  1  0        /* TX_CLK (CLK3) */
 151                                         0 12  1  0  1  0        /* TxD0 */
 152                                         0 13  1  0  1  0        /* TxD1 */
 153                                         0 14  1  0  1  0        /* TxD2 */
 154                                         0 15  1  0  1  0        /* TxD3 */
 155                                         0 16  2  0  1  0        /* RxD0 */
 156                                         0 17  2  0  1  0        /* RxD1 */
 157                                         0 18  2  0  1  0        /* RxD2 */
 158                                         0 19  2  0  1  0        /* RxD3 */
 159                                         0 1a  2  0  1  0        /* RX_ER */
 160                                         0 1b  1  0  1  0        /* TX_ER */
 161                                         0 1c  2  0  1  0        /* RX_DV */
 162                                         0 1d  2  0  1  0        /* COL */
 163                                         0 1e  1  0  1  0        /* TX_EN */
 164                                         0 1f  2  0  1  0>;      /* CRS */
 165                         };
 166                         ucc3pio:ucc_pin@03 {
 167                                 pio-map = <
 168                         /* port  pin  dir  open_drain  assignment  has_irq */
 169                                         0  d  2  0  1  0        /* RX_CLK (CLK9) */
 170                                         3 18  2  0  1  0        /* TX_CLK (CLK10) */
 171                                         1  0  1  0  1  0        /* TxD0 */
 172                                         1  1  1  0  1  0        /* TxD1 */
 173                                         1  2  1  0  1  0        /* TxD2 */
 174                                         1  3  1  0  1  0        /* TxD3 */
 175                                         1  4  2  0  1  0        /* RxD0 */
 176                                         1  5  2  0  1  0        /* RxD1 */
 177                                         1  6  2  0  1  0        /* RxD2 */
 178                                         1  7  2  0  1  0        /* RxD3 */
 179                                         1  8  2  0  1  0        /* RX_ER */
 180                                         1  9  1  0  1  0        /* TX_ER */
 181                                         1  a  2  0  1  0        /* RX_DV */
 182                                         1  b  2  0  1  0        /* COL */
 183                                         1  c  1  0  1  0        /* TX_EN */
 184                                         1  d  2  0  1  0>;      /* CRS */
 185                         };
 186                 };
 187         };
 188
 189         qe@e0100000 {
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192                 device_type = "qe";
 193                 model = "QE";
 194                 ranges = <0 e0100000 00100000>;
 195                 reg = <e0100000 480>;
 196                 brg-frequency = <0>;
 197                 bus-frequency = <BCD3D80>;
 198
 199                 muram@10000 {
 200                         device_type = "muram";
 201                         ranges = <0 00010000 00004000>;
 202
 203                         data-only@0 {
 204                                 reg = <0 4000>;
 205                         };
 206                 };
 207
 208                 spi@4c0 {
 209                         device_type = "spi";
 210                         compatible = "fsl_spi";
 211                         reg = <4c0 40>;
 212                         interrupts = <2>;
 213                         interrupt-parent = <&qeic>;
 214                         mode = "cpu";
 215                 };
 216
 217                 spi@500 {
 218                         device_type = "spi";
 219                         compatible = "fsl_spi";
 220                         reg = <500 40>;
 221                         interrupts = <1>;
 222                         interrupt-parent = <&qeic>;
 223                         mode = "cpu";
 224                 };
 225
 226                 ucc@3000 {
 227                         device_type = "network";
 228                         compatible = "ucc_geth";
 229                         model = "UCC";
 230                         device-id = <2>;
 231                         reg = <3000 200>;
 232                         interrupts = <21>;
 233                         interrupt-parent = <&qeic>;
 234                         mac-address = [ 00 04 9f ef 03 02 ];
 235                         rx-clock = <20>;
 236                         tx-clock = <13>;
 237                         phy-handle = <&phy00>;
 238                         pio-handle = <&ucc2pio>;
 239                 };
 240
 241                 ucc@2200 {
 242                         device_type = "network";
 243                         compatible = "ucc_geth";
 244                         model = "UCC";
 245                         device-id = <3>;
 246                         reg = <2200 200>;
 247                         interrupts = <22>;
 248                         interrupt-parent = <&qeic>;
 249                         mac-address = [ 00 04 9f ef 03 01 ];
 250                         rx-clock = <19>;
 251                         tx-clock = <1a>;
 252                         phy-handle = <&phy04>;
 253                         pio-handle = <&ucc3pio>;
 254                 };
 255
 256                 mdio@3120 {
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         reg = <3120 18>;
 260                         device_type = "mdio";
 261                         compatible = "ucc_geth_phy";
 262
 263                         phy00:ethernet-phy@00 {
 264                                 interrupt-parent = <&pic>;
 265                                 interrupts = <0>;
 266                                 reg = <0>;
 267                                 device_type = "ethernet-phy";
 268                                 interface = <3>; //ENET_100_MII
 269                         };
 270                         phy04:ethernet-phy@04 {
 271                                 interrupt-parent = <&pic>;
 272                                 interrupts = <0>;
 273                                 reg = <4>;
 274                                 device_type = "ethernet-phy";
 275                                 interface = <3>;
 276                         };
 277                 };
 278
 279                 qeic:qeic@80 {
 280                         interrupt-controller;
 281                         device_type = "qeic";
 282                         #address-cells = <0>;
 283                         #interrupt-cells = <1>;
 284                         reg = <80 80>;
 285                         built-in;
 286                         big-endian;
 287                         interrupts = <20 8 21 8>; //high:32 low:33
 288                         interrupt-parent = <&pic>;
 289                 };
 290         };
 291 };