arch/powerpc/boot/dts/mpc832x_mds.dts

   1 /*
   2  * MPC8323E EMDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10
  11  * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
  12  * this:
  13  *
  14  * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
  15  * 2) Solder a wire from U61-21 to P19A-23.  P19 is a grid of pins on the board
  16  *    next to the serial ports.
  17  * 3) Solder a wire from U61-22 to P19K-22.
  18  *
  19  * Note that there's a typo in the schematic.  The board labels the last column
  20  * of pins "P19K", but in the schematic, that column is called "P19J".  So if
  21  * you're going by the schematic, the pin is called "P19J-K22".
  22  */
  23
  24 /dts-v1/;
  25
  26 / {
  27         model = "MPC8323EMDS";
  28         compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
  29         #address-cells = <1>;
  30         #size-cells = <1>;
  31
  32         aliases {
  33                 ethernet0 = &enet0;
  34                 ethernet1 = &enet1;
  35                 serial0 = &serial0;
  36                 serial1 = &serial1;
  37                 pci0 = &pci0;
  38         };
  39
  40         cpus {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 PowerPC,8323@0 {
  45                         device_type = "cpu";
  46                         reg = <0x0>;
  47                         d-cache-line-size = <32>;       // 32 bytes
  48                         i-cache-line-size = <32>;       // 32 bytes
  49                         d-cache-size = <16384>;         // L1, 16K
  50                         i-cache-size = <16384>;         // L1, 16K
  51                         timebase-frequency = <0>;
  52                         bus-frequency = <0>;
  53                         clock-frequency = <0>;
  54                 };
  55         };
  56
  57         memory {
  58                 device_type = "memory";
  59                 reg = <0x00000000 0x08000000>;
  60         };
  61
  62         bcsr@f8000000 {
  63                 device_type = "board-control";
  64                 reg = <0xf8000000 0x8000>;
  65         };
  66
  67         soc8323@e0000000 {
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 device_type = "soc";
  71                 ranges = <0x0 0xe0000000 0x00100000>;
  72                 reg = <0xe0000000 0x00000200>;
  73                 bus-frequency = <132000000>;
  74
  75                 wdt@200 {
  76                         device_type = "watchdog";
  77                         compatible = "mpc83xx_wdt";
  78                         reg = <0x200 0x100>;
  79                 };
  80
  81                 i2c@3000 {
  82                         #address-cells = <1>;
  83                         #size-cells = <0>;
  84                         cell-index = <0>;
  85                         compatible = "fsl-i2c";
  86                         reg = <0x3000 0x100>;
  87                         interrupts = <14 0x8>;
  88                         interrupt-parent = <&ipic>;
  89                         dfsrr;
  90
  91                         rtc@68 {
  92                                 compatible = "dallas,ds1374";
  93                                 reg = <0x68>;
  94                         };
  95                 };
  96
  97                 serial0: serial@4500 {
  98                         cell-index = <0>;
  99                         device_type = "serial";
 100                         compatible = "ns16550";
 101                         reg = <0x4500 0x100>;
 102                         clock-frequency = <0>;
 103                         interrupts = <9 0x8>;
 104                         interrupt-parent = <&ipic>;
 105                 };
 106
 107                 serial1: serial@4600 {
 108                         cell-index = <1>;
 109                         device_type = "serial";
 110                         compatible = "ns16550";
 111                         reg = <0x4600 0x100>;
 112                         clock-frequency = <0>;
 113                         interrupts = <10 0x8>;
 114                         interrupt-parent = <&ipic>;
 115                 };
 116
 117                 dma@82a8 {
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120                         compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
 121                         reg = <0x82a8 4>;
 122                         ranges = <0 0x8100 0x1a8>;
 123                         interrupt-parent = <&ipic>;
 124                         interrupts = <71 8>;
 125                         cell-index = <0>;
 126                         dma-channel@0 {
 127                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 128                                 reg = <0 0x80>;
 129                                 interrupt-parent = <&ipic>;
 130                                 interrupts = <71 8>;
 131                         };
 132                         dma-channel@80 {
 133                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 134                                 reg = <0x80 0x80>;
 135                                 interrupt-parent = <&ipic>;
 136                                 interrupts = <71 8>;
 137                         };
 138                         dma-channel@100 {
 139                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 140                                 reg = <0x100 0x80>;
 141                                 interrupt-parent = <&ipic>;
 142                                 interrupts = <71 8>;
 143                         };
 144                         dma-channel@180 {
 145                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 146                                 reg = <0x180 0x28>;
 147                                 interrupt-parent = <&ipic>;
 148                                 interrupts = <71 8>;
 149                         };
 150                 };
 151
 152                 crypto@30000 {
 153                         compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 154                         reg = <0x30000 0x10000>;
 155                         interrupts = <11 0x8>;
 156                         interrupt-parent = <&ipic>;
 157                         fsl,num-channels = <1>;
 158                         fsl,channel-fifo-len = <24>;
 159                         fsl,exec-units-mask = <0x4c>;
 160                         fsl,descriptor-types-mask = <0x0122003f>;
 161                 };
 162
 163                 ipic: pic@700 {
 164                         interrupt-controller;
 165                         #address-cells = <0>;
 166                         #interrupt-cells = <2>;
 167                         reg = <0x700 0x100>;
 168                         device_type = "ipic";
 169                 };
 170
 171                 par_io@1400 {
 172                         reg = <0x1400 0x100>;
 173                         device_type = "par_io";
 174                         num-ports = <7>;
 175
 176                         pio3: ucc_pin@03 {
 177                                 pio-map = <
 178                         /* port  pin  dir  open_drain  assignment  has_irq */
 179                                         3  4  3  0  2  0  /* MDIO */
 180                                         3  5  1  0  2  0  /* MDC */
 181                                         0 13  2  0  1  0        /* RX_CLK (CLK9) */
 182                                         3 24  2  0  1  0        /* TX_CLK (CLK10) */
 183                                         1  0  1  0  1  0        /* TxD0 */
 184                                         1  1  1  0  1  0        /* TxD1 */
 185                                         1  2  1  0  1  0        /* TxD2 */
 186                                         1  3  1  0  1  0        /* TxD3 */
 187                                         1  4  2  0  1  0        /* RxD0 */
 188                                         1  5  2  0  1  0        /* RxD1 */
 189                                         1  6  2  0  1  0        /* RxD2 */
 190                                         1  7  2  0  1  0        /* RxD3 */
 191                                         1  8  2  0  1  0        /* RX_ER */
 192                                         1  9  1  0  1  0        /* TX_ER */
 193                                         1 10  2  0  1  0        /* RX_DV */
 194                                         1 11  2  0  1  0        /* COL */
 195                                         1 12  1  0  1  0        /* TX_EN */
 196                                         1 13  2  0  1  0>;      /* CRS */
 197                         };
 198                         pio4: ucc_pin@04 {
 199                                 pio-map = <
 200                         /* port  pin  dir  open_drain  assignment  has_irq */
 201                                         3 31  2  0  1  0        /* RX_CLK (CLK7) */
 202                                         3  6  2  0  1  0        /* TX_CLK (CLK8) */
 203                                         1 18  1  0  1  0        /* TxD0 */
 204                                         1 19  1  0  1  0        /* TxD1 */
 205                                         1 20  1  0  1  0        /* TxD2 */
 206                                         1 21  1  0  1  0        /* TxD3 */
 207                                         1 22  2  0  1  0        /* RxD0 */
 208                                         1 23  2  0  1  0        /* RxD1 */
 209                                         1 24  2  0  1  0        /* RxD2 */
 210                                         1 25  2  0  1  0        /* RxD3 */
 211                                         1 26  2  0  1  0        /* RX_ER */
 212                                         1 27  1  0  1  0        /* TX_ER */
 213                                         1 28  2  0  1  0        /* RX_DV */
 214                                         1 29  2  0  1  0        /* COL */
 215                                         1 30  1  0  1  0        /* TX_EN */
 216                                         1 31  2  0  1  0>;      /* CRS */
 217                         };
 218                         pio5: ucc_pin@05 {
 219                                 pio-map = <
 220                                 /*
 221                                  *                    open       has
 222                                  *   port  pin  dir  drain  sel  irq
 223                                  */
 224                                         2    0    1      0    2    0  /* TxD5 */
 225                                         2    8    2      0    2    0  /* RxD5 */
 226
 227                                         2   29    2      0    0    0  /* CTS5 */
 228                                         2   31    1      0    2    0  /* RTS5 */
 229
 230                                         2   24    2      0    0    0  /* CD */
 231
 232                                 >;
 233                         };
 234
 235                 };
 236         };
 237
 238         qe@e0100000 {
 239                 #address-cells = <1>;
 240                 #size-cells = <1>;
 241                 device_type = "qe";
 242                 compatible = "fsl,qe";
 243                 ranges = <0x0 0xe0100000 0x00100000>;
 244                 reg = <0xe0100000 0x480>;
 245                 brg-frequency = <0>;
 246                 bus-frequency = <198000000>;
 247
 248                 muram@10000 {
 249                         #address-cells = <1>;
 250                         #size-cells = <1>;
 251                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 252                         ranges = <0x0 0x00010000 0x00004000>;
 253
 254                         data-only@0 {
 255                                 compatible = "fsl,qe-muram-data",
 256                                              "fsl,cpm-muram-data";
 257                                 reg = <0x0 0x4000>;
 258                         };
 259                 };
 260
 261                 spi@4c0 {
 262                         cell-index = <0>;
 263                         compatible = "fsl,spi";
 264                         reg = <0x4c0 0x40>;
 265                         interrupts = <2>;
 266                         interrupt-parent = <&qeic>;
 267                         mode = "cpu";
 268                 };
 269
 270                 spi@500 {
 271                         cell-index = <1>;
 272                         compatible = "fsl,spi";
 273                         reg = <0x500 0x40>;
 274                         interrupts = <1>;
 275                         interrupt-parent = <&qeic>;
 276                         mode = "cpu";
 277                 };
 278
 279                 usb@6c0 {
 280                         compatible = "qe_udc";
 281                         reg = <0x6c0 0x40 0x8b00 0x100>;
 282                         interrupts = <11>;
 283                         interrupt-parent = <&qeic>;
 284                         mode = "slave";
 285                 };
 286
 287                 enet0: ucc@2200 {
 288                         device_type = "network";
 289                         compatible = "ucc_geth";
 290                         cell-index = <3>;
 291                         reg = <0x2200 0x200>;
 292                         interrupts = <34>;
 293                         interrupt-parent = <&qeic>;
 294                         local-mac-address = [ 00 00 00 00 00 00 ];
 295                         rx-clock-name = "clk9";
 296                         tx-clock-name = "clk10";
 297                         phy-handle = <&phy3>;
 298                         pio-handle = <&pio3>;
 299                 };
 300
 301                 enet1: ucc@3200 {
 302                         device_type = "network";
 303                         compatible = "ucc_geth";
 304                         cell-index = <4>;
 305                         reg = <0x3200 0x200>;
 306                         interrupts = <35>;
 307                         interrupt-parent = <&qeic>;
 308                         local-mac-address = [ 00 00 00 00 00 00 ];
 309                         rx-clock-name = "clk7";
 310                         tx-clock-name = "clk8";
 311                         phy-handle = <&phy4>;
 312                         pio-handle = <&pio4>;
 313                 };
 314
 315                 ucc@2400 {
 316                         device_type = "serial";
 317                         compatible = "ucc_uart";
 318                         cell-index = <5>;       /* The UCC number, 1-7*/
 319                         port-number = <0>;      /* Which ttyQEx device */
 320                         soft-uart;              /* We need Soft-UART */
 321                         reg = <0x2400 0x200>;
 322                         interrupts = <40>;      /* From Table 18-12 */
 323                         interrupt-parent = < &qeic >;
 324                         /*
 325                          * For Soft-UART, we need to set TX to 1X, which
 326                          * means specifying separate clock sources.
 327                          */
 328                         rx-clock-name = "brg5";
 329                         tx-clock-name = "brg6";
 330                         pio-handle = < &pio5 >;
 331                 };
 332
 333
 334                 mdio@2320 {
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         reg = <0x2320 0x18>;
 338                         compatible = "fsl,ucc-mdio";
 339
 340                         phy3: ethernet-phy@03 {
 341                                 interrupt-parent = <&ipic>;
 342                                 interrupts = <17 0x8>;
 343                                 reg = <0x3>;
 344                                 device_type = "ethernet-phy";
 345                         };
 346                         phy4: ethernet-phy@04 {
 347                                 interrupt-parent = <&ipic>;
 348                                 interrupts = <18 0x8>;
 349                                 reg = <0x4>;
 350                                 device_type = "ethernet-phy";
 351                         };
 352                 };
 353
 354                 qeic: interrupt-controller@80 {
 355                         interrupt-controller;
 356                         compatible = "fsl,qe-ic";
 357                         #address-cells = <0>;
 358                         #interrupt-cells = <1>;
 359                         reg = <0x80 0x80>;
 360                         big-endian;
 361                         interrupts = <32 0x8 33 0x8>; //high:32 low:33
 362                         interrupt-parent = <&ipic>;
 363                 };
 364         };
 365
 366         pci0: pci@e0008500 {
 367                 cell-index = <1>;
 368                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 369                 interrupt-map = <
 370                                 /* IDSEL 0x11 AD17 */
 371                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 372                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 373                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 374                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 375
 376                                 /* IDSEL 0x12 AD18 */
 377                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 378                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 379                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 380                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 381
 382                                 /* IDSEL 0x13 AD19 */
 383                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 384                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 385                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 386                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 387
 388                                 /* IDSEL 0x15 AD21*/
 389                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 390                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 391                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 392                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 393
 394                                 /* IDSEL 0x16 AD22*/
 395                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 396                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 397                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 398                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 399
 400                                 /* IDSEL 0x17 AD23*/
 401                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 402                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 403                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 404                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 405
 406                                 /* IDSEL 0x18 AD24*/
 407                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 408                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 409                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 410                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 411                 interrupt-parent = <&ipic>;
 412                 interrupts = <66 0x8>;
 413                 bus-range = <0x0 0x0>;
 414                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 415                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 416                           0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
 417                 clock-frequency = <0>;
 418                 #interrupt-cells = <1>;
 419                 #size-cells = <2>;
 420                 #address-cells = <3>;
 421                 reg = <0xe0008500 0x100>;
 422                 compatible = "fsl,mpc8349-pci";
 423                 device_type = "pci";
 424         };
 425 };