arch/powerpc/boot/dts/gef_sbc310.dts

   1 /*
   2  * GE Fanuc SBC310 Device Tree Source
   3  *
   4  * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Based on: SBS CM6 Device Tree Source
  12  * Copyright 2007 SBS Technologies GmbH & Co. KG
  13  * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
  14  * Copyright 2006 Freescale Semiconductor Inc.
  15  */
  16
  17 /*
  18  * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
  19  */
  20
  21 /dts-v1/;
  22
  23 / {
  24         model = "GEF_SBC310";
  25         compatible = "gef,sbc310";
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         aliases {
  30                 ethernet0 = &enet0;
  31                 ethernet1 = &enet1;
  32                 serial0 = &serial0;
  33                 serial1 = &serial1;
  34                 pci0 = &pci0;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 PowerPC,8641@0 {
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                         d-cache-line-size = <32>;       // 32 bytes
  45                         i-cache-line-size = <32>;       // 32 bytes
  46                         d-cache-size = <32768>;         // L1, 32K
  47                         i-cache-size = <32768>;         // L1, 32K
  48                         timebase-frequency = <0>;       // From uboot
  49                         bus-frequency = <0>;            // From uboot
  50                         clock-frequency = <0>;          // From uboot
  51                 };
  52                 PowerPC,8641@1 {
  53                         device_type = "cpu";
  54                         reg = <1>;
  55                         d-cache-line-size = <32>;       // 32 bytes
  56                         i-cache-line-size = <32>;       // 32 bytes
  57                         d-cache-size = <32768>;         // L1, 32K
  58                         i-cache-size = <32768>;         // L1, 32K
  59                         timebase-frequency = <0>;       // From uboot
  60                         bus-frequency = <0>;            // From uboot
  61                         clock-frequency = <0>;          // From uboot
  62                 };
  63         };
  64
  65         memory {
  66                 device_type = "memory";
  67                 reg = <0x0 0x40000000>; // set by uboot
  68         };
  69
  70         localbus@fef05000 {
  71                 #address-cells = <2>;
  72                 #size-cells = <1>;
  73                 compatible = "fsl,mpc8641-localbus", "simple-bus";
  74                 reg = <0xfef05000 0x1000>;
  75                 interrupts = <19 2>;
  76                 interrupt-parent = <&mpic>;
  77
  78                 ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
  79                           1 0 0xe0000000 0x08000000     // Paged Flash 0
  80                           2 0 0xe8000000 0x08000000     // Paged Flash 1
  81                           3 0 0xfc100000 0x00020000     // NVRAM
  82                           4 0 0xfc000000 0x00010000>;   // FPGA
  83
  84                 /* flash@0,0 is a mirror of part of the memory in flash@1,0
  85                 flash@0,0 {
  86                         compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
  87                         reg = <0x0 0x0 0x01000000>;
  88                         bank-width = <2>;
  89                         device-width = <2>;
  90                         #address-cells = <1>;
  91                         #size-cells = <1>;
  92                         partition@0 {
  93                                 label = "firmware";
  94                                 reg = <0x0 0x01000000>;
  95                                 read-only;
  96                         };
  97                 };
  98                 */
  99
 100                 flash@1,0 {
 101                         compatible = "gef,sbc310-paged-flash", "cfi-flash";
 102                         reg = <0x1 0x0 0x8000000>;
 103                         bank-width = <2>;
 104                         device-width = <2>;
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         partition@0 {
 108                                 label = "user";
 109                                 reg = <0x0 0x7800000>;
 110                         };
 111                         partition@7800000 {
 112                                 label = "firmware";
 113                                 reg = <0x7800000 0x800000>;
 114                                 read-only;
 115                         };
 116                 };
 117
 118                 nvram@3,0 {
 119                         device_type = "nvram";
 120                         compatible = "simtek,stk14ca8";
 121                         reg = <0x3 0x0 0x20000>;
 122                 };
 123
 124                 fpga@4,0 {
 125                         compatible = "gef,fpga-regs";
 126                         reg = <0x4 0x0 0x40>;
 127                 };
 128
 129                 wdt@4,2000 {
 130                         compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
 131                                 "gef,fpga-wdt";
 132                         reg = <0x4 0x2000 0x8>;
 133                         interrupts = <0x1a 0x4>;
 134                         interrupt-parent = <&gef_pic>;
 135                 };
 136 /*
 137                 wdt@4,2010 {
 138                         compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
 139                                 "gef,fpga-wdt";
 140                         reg = <0x4 0x2010 0x8>;
 141                         interrupts = <0x1b 0x4>;
 142                         interrupt-parent = <&gef_pic>;
 143                 };
 144 */
 145                 gef_pic: pic@4,4000 {
 146                         #interrupt-cells = <1>;
 147                         interrupt-controller;
 148                         compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
 149                         reg = <0x4 0x4000 0x20>;
 150                         interrupts = <0x8
 151                                       0x9>;
 152                         interrupt-parent = <&mpic>;
 153
 154                 };
 155                 gef_gpio: gpio@4,8000 {
 156                         #gpio-cells = <2>;
 157                         compatible = "gef,sbc310-gpio";
 158                         reg = <0x4 0x8000 0x24>;
 159                         gpio-controller;
 160                 };
 161         };
 162
 163         soc@fef00000 {
 164                 #address-cells = <1>;
 165                 #size-cells = <1>;
 166                 #interrupt-cells = <2>;
 167                 device_type = "soc";
 168                 compatible = "fsl,mpc8641-soc", "simple-bus";
 169                 ranges = <0x0 0xfef00000 0x00100000>;
 170                 bus-frequency = <33333333>;
 171
 172                 mcm-law@0 {
 173                         compatible = "fsl,mcm-law";
 174                         reg = <0x0 0x1000>;
 175                         fsl,num-laws = <10>;
 176                 };
 177
 178                 mcm@1000 {
 179                         compatible = "fsl,mpc8641-mcm", "fsl,mcm";
 180                         reg = <0x1000 0x1000>;
 181                         interrupts = <17 2>;
 182                         interrupt-parent = <&mpic>;
 183                 };
 184
 185                 i2c1: i2c@3000 {
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                         compatible = "fsl-i2c";
 189                         reg = <0x3000 0x100>;
 190                         interrupts = <0x2b 0x2>;
 191                         interrupt-parent = <&mpic>;
 192                         dfsrr;
 193
 194                         rtc@51 {
 195                                 compatible = "epson,rx8581";
 196                                 reg = <0x00000051>;
 197                         };
 198                 };
 199
 200                 i2c2: i2c@3100 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         compatible = "fsl-i2c";
 204                         reg = <0x3100 0x100>;
 205                         interrupts = <0x2b 0x2>;
 206                         interrupt-parent = <&mpic>;
 207                         dfsrr;
 208
 209                         hwmon@48 {
 210                                 compatible = "national,lm92";
 211                                 reg = <0x48>;
 212                         };
 213
 214                         hwmon@4c {
 215                                 compatible = "adi,adt7461";
 216                                 reg = <0x4c>;
 217                         };
 218
 219                         eti@6b {
 220                                 compatible = "dallas,ds1682";
 221                                 reg = <0x6b>;
 222                         };
 223                 };
 224
 225                 dma@21300 {
 226                         #address-cells = <1>;
 227                         #size-cells = <1>;
 228                         compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
 229                         reg = <0x21300 0x4>;
 230                         ranges = <0x0 0x21100 0x200>;
 231                         cell-index = <0>;
 232                         dma-channel@0 {
 233                                 compatible = "fsl,mpc8641-dma-channel",
 234                                            "fsl,eloplus-dma-channel";
 235                                 reg = <0x0 0x80>;
 236                                 cell-index = <0>;
 237                                 interrupt-parent = <&mpic>;
 238                                 interrupts = <20 2>;
 239                         };
 240                         dma-channel@80 {
 241                                 compatible = "fsl,mpc8641-dma-channel",
 242                                            "fsl,eloplus-dma-channel";
 243                                 reg = <0x80 0x80>;
 244                                 cell-index = <1>;
 245                                 interrupt-parent = <&mpic>;
 246                                 interrupts = <21 2>;
 247                         };
 248                         dma-channel@100 {
 249                                 compatible = "fsl,mpc8641-dma-channel",
 250                                            "fsl,eloplus-dma-channel";
 251                                 reg = <0x100 0x80>;
 252                                 cell-index = <2>;
 253                                 interrupt-parent = <&mpic>;
 254                                 interrupts = <22 2>;
 255                         };
 256                         dma-channel@180 {
 257                                 compatible = "fsl,mpc8641-dma-channel",
 258                                            "fsl,eloplus-dma-channel";
 259                                 reg = <0x180 0x80>;
 260                                 cell-index = <3>;
 261                                 interrupt-parent = <&mpic>;
 262                                 interrupts = <23 2>;
 263                         };
 264                 };
 265
 266                 enet0: ethernet@24000 {
 267                         #address-cells = <1>;
 268                         #size-cells = <1>;
 269                         device_type = "network";
 270                         model = "eTSEC";
 271                         compatible = "gianfar";
 272                         reg = <0x24000 0x1000>;
 273                         ranges = <0x0 0x24000 0x1000>;
 274                         local-mac-address = [ 00 00 00 00 00 00 ];
 275                         interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
 276                         interrupt-parent = <&mpic>;
 277                         phy-handle = <&phy0>;
 278                         phy-connection-type = "gmii";
 279
 280                         mdio@520 {
 281                                 #address-cells = <1>;
 282                                 #size-cells = <0>;
 283                                 compatible = "fsl,gianfar-mdio";
 284                                 reg = <0x520 0x20>;
 285
 286                                 phy0: ethernet-phy@0 {
 287                                         interrupt-parent = <&gef_pic>;
 288                                         interrupts = <0x9 0x4>;
 289                                         reg = <1>;
 290                                 };
 291                                 phy2: ethernet-phy@2 {
 292                                         interrupt-parent = <&gef_pic>;
 293                                         interrupts = <0x8 0x4>;
 294                                         reg = <3>;
 295                                 };
 296                         };
 297                 };
 298
 299                 enet1: ethernet@26000 {
 300                         device_type = "network";
 301                         model = "eTSEC";
 302                         compatible = "gianfar";
 303                         reg = <0x26000 0x1000>;
 304                         local-mac-address = [ 00 00 00 00 00 00 ];
 305                         interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
 306                         interrupt-parent = <&mpic>;
 307                         phy-handle = <&phy2>;
 308                         phy-connection-type = "gmii";
 309                 };
 310
 311                 serial0: serial@4500 {
 312                         cell-index = <0>;
 313                         device_type = "serial";
 314                         compatible = "ns16550";
 315                         reg = <0x4500 0x100>;
 316                         clock-frequency = <0>;
 317                         interrupts = <0x2a 0x2>;
 318                         interrupt-parent = <&mpic>;
 319                 };
 320
 321                 serial1: serial@4600 {
 322                         cell-index = <1>;
 323                         device_type = "serial";
 324                         compatible = "ns16550";
 325                         reg = <0x4600 0x100>;
 326                         clock-frequency = <0>;
 327                         interrupts = <0x1c 0x2>;
 328                         interrupt-parent = <&mpic>;
 329                 };
 330
 331                 mpic: pic@40000 {
 332                         clock-frequency = <0>;
 333                         interrupt-controller;
 334                         #address-cells = <0>;
 335                         #interrupt-cells = <2>;
 336                         reg = <0x40000 0x40000>;
 337                         compatible = "chrp,open-pic";
 338                         device_type = "open-pic";
 339                 };
 340
 341                 global-utilities@e0000 {
 342                         compatible = "fsl,mpc8641-guts";
 343                         reg = <0xe0000 0x1000>;
 344                         fsl,has-rstcr;
 345                 };
 346         };
 347
 348         pci0: pcie@fef08000 {
 349                 compatible = "fsl,mpc8641-pcie";
 350                 device_type = "pci";
 351                 #interrupt-cells = <1>;
 352                 #size-cells = <2>;
 353                 #address-cells = <3>;
 354                 reg = <0xfef08000 0x1000>;
 355                 bus-range = <0x0 0xff>;
 356                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
 357                           0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
 358                 clock-frequency = <33333333>;
 359                 interrupt-parent = <&mpic>;
 360                 interrupts = <0x18 0x2>;
 361                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 362                 interrupt-map = <
 363                         0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
 364                         0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
 365                         0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
 366                         0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
 367                 >;
 368
 369                 pcie@0 {
 370                         reg = <0 0 0 0 0>;
 371                         #size-cells = <2>;
 372                         #address-cells = <3>;
 373                         device_type = "pci";
 374                         ranges = <0x02000000 0x0 0x80000000
 375                                   0x02000000 0x0 0x80000000
 376                                   0x0 0x40000000
 377
 378                                   0x01000000 0x0 0x00000000
 379                                   0x01000000 0x0 0x00000000
 380                                   0x0 0x00400000>;
 381                 };
 382         };
 383
 384         pci1: pcie@fef09000 {
 385                 compatible = "fsl,mpc8641-pcie";
 386                 device_type = "pci";
 387                 #interrupt-cells = <1>;
 388                 #size-cells = <2>;
 389                 #address-cells = <3>;
 390                 reg = <0xfef09000 0x1000>;
 391                 bus-range = <0x0 0xff>;
 392                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 393                           0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
 394                 clock-frequency = <33333333>;
 395                 interrupt-parent = <&mpic>;
 396                 interrupts = <0x19 0x2>;
 397                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 398                 interrupt-map = <
 399                         0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
 400                         0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
 401                         0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
 402                         0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
 403                         >;
 404
 405                 pcie@0 {
 406                         reg = <0 0 0 0 0>;
 407                         #size-cells = <2>;
 408                         #address-cells = <3>;
 409                         device_type = "pci";
 410                         ranges = <0x02000000 0x0 0xc0000000
 411                                   0x02000000 0x0 0xc0000000
 412                                   0x0 0x20000000
 413
 414                                   0x01000000 0x0 0x00000000
 415                                   0x01000000 0x0 0x00000000
 416                                   0x0 0x00400000>;
 417                 };
 418         };
 419 };