2 * PARISC TLB and cache flushing support
3 * Copyright (C) 2000-2001 Hewlett-Packard (John Marvin)
4 * Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org)
5 * Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * NOTE: fdc,fic, and pdc instructions that use base register modification
24 * should only use index and base registers that are not shadowed,
25 * so that the fast path emulation in the non access miss handler
36 #include <asm/assembly.h>
37 #include <asm/pgtable.h>
38 #include <asm/cache.h>
40 #include <asm/alternative.h>
41 #include <linux/linkage.h>
42 #include <linux/init.h>
47 ENTRY_CFI(flush_tlb_all_local)
49 * The pitlbe and pdtlbe instructions should only be used to
50 * flush the entire tlb. Also, there needs to be no intervening
51 * tlb operations, e.g. tlb misses, so the operation needs
52 * to happen in real mode with all interruptions disabled.
55 /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
56 rsm PSW_SM_I, %r19 /* save I-bit state */
64 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
65 mtctl %r0, %cr17 /* Clear IIASQ tail */
66 mtctl %r0, %cr17 /* Clear IIASQ head */
67 mtctl %r1, %cr18 /* IIAOQ head */
69 mtctl %r1, %cr18 /* IIAOQ tail */
70 load32 REAL_MODE_PSW, %r1
75 1: load32 PA(cache_info), %r1
77 /* Flush Instruction Tlb */
79 LDREG ITLB_SID_BASE(%r1), %r20
80 LDREG ITLB_SID_STRIDE(%r1), %r21
81 LDREG ITLB_SID_COUNT(%r1), %r22
82 LDREG ITLB_OFF_BASE(%r1), %arg0
83 LDREG ITLB_OFF_STRIDE(%r1), %arg1
84 LDREG ITLB_OFF_COUNT(%r1), %arg2
85 LDREG ITLB_LOOP(%r1), %arg3
87 addib,COND(=) -1, %arg3, fitoneloop /* Preadjust and test */
88 movb,<,n %arg3, %r31, fitdone /* If loop < 0, skip */
89 copy %arg0, %r28 /* Init base addr */
91 fitmanyloop: /* Loop if LOOP >= 2 */
93 add %r21, %r20, %r20 /* increment space */
94 copy %arg2, %r29 /* Init middle loop count */
96 fitmanymiddle: /* Loop if LOOP >= 2 */
97 addib,COND(>) -1, %r31, fitmanymiddle /* Adjusted inner loop decr */
98 pitlbe %r0(%sr1, %r28)
99 pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */
100 addib,COND(>) -1, %r29, fitmanymiddle /* Middle loop decr */
101 copy %arg3, %r31 /* Re-init inner loop count */
103 movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */
104 addib,COND(<=),n -1, %r22, fitdone /* Outer loop count decr */
106 fitoneloop: /* Loop if LOOP = 1 */
108 copy %arg0, %r28 /* init base addr */
109 copy %arg2, %r29 /* init middle loop count */
111 fitonemiddle: /* Loop if LOOP = 1 */
112 addib,COND(>) -1, %r29, fitonemiddle /* Middle loop count decr */
113 pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */
115 addib,COND(>) -1, %r22, fitoneloop /* Outer loop count decr */
116 add %r21, %r20, %r20 /* increment space */
122 LDREG DTLB_SID_BASE(%r1), %r20
123 LDREG DTLB_SID_STRIDE(%r1), %r21
124 LDREG DTLB_SID_COUNT(%r1), %r22
125 LDREG DTLB_OFF_BASE(%r1), %arg0
126 LDREG DTLB_OFF_STRIDE(%r1), %arg1
127 LDREG DTLB_OFF_COUNT(%r1), %arg2
128 LDREG DTLB_LOOP(%r1), %arg3
130 addib,COND(=) -1, %arg3, fdtoneloop /* Preadjust and test */
131 movb,<,n %arg3, %r31, fdtdone /* If loop < 0, skip */
132 copy %arg0, %r28 /* Init base addr */
134 fdtmanyloop: /* Loop if LOOP >= 2 */
136 add %r21, %r20, %r20 /* increment space */
137 copy %arg2, %r29 /* Init middle loop count */
139 fdtmanymiddle: /* Loop if LOOP >= 2 */
140 addib,COND(>) -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */
141 pdtlbe %r0(%sr1, %r28)
142 pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */
143 addib,COND(>) -1, %r29, fdtmanymiddle /* Middle loop decr */
144 copy %arg3, %r31 /* Re-init inner loop count */
146 movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */
147 addib,COND(<=),n -1, %r22,fdtdone /* Outer loop count decr */
149 fdtoneloop: /* Loop if LOOP = 1 */
151 copy %arg0, %r28 /* init base addr */
152 copy %arg2, %r29 /* init middle loop count */
154 fdtonemiddle: /* Loop if LOOP = 1 */
155 addib,COND(>) -1, %r29, fdtonemiddle /* Middle loop count decr */
156 pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */
158 addib,COND(>) -1, %r22, fdtoneloop /* Outer loop count decr */
159 add %r21, %r20, %r20 /* increment space */
164 * Switch back to virtual mode
175 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
176 mtctl %r0, %cr17 /* Clear IIASQ tail */
177 mtctl %r0, %cr17 /* Clear IIASQ head */
178 mtctl %r1, %cr18 /* IIAOQ head */
180 mtctl %r1, %cr18 /* IIAOQ tail */
181 load32 KERNEL_PSW, %r1
182 or %r1, %r19, %r1 /* I-bit to state on entry */
183 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
189 ENDPROC_CFI(flush_tlb_all_local)
191 .import cache_info,data
193 ENTRY_CFI(flush_instruction_cache_local)
194 88: load32 cache_info, %r1
196 /* Flush Instruction Cache */
198 LDREG ICACHE_BASE(%r1), %arg0
199 LDREG ICACHE_STRIDE(%r1), %arg1
200 LDREG ICACHE_COUNT(%r1), %arg2
201 LDREG ICACHE_LOOP(%r1), %arg3
202 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
204 addib,COND(=) -1, %arg3, fioneloop /* Preadjust and test */
205 movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */
207 fimanyloop: /* Loop if LOOP >= 2 */
208 addib,COND(>) -1, %r31, fimanyloop /* Adjusted inner loop decr */
209 fice %r0(%sr1, %arg0)
210 fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */
211 movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */
212 addib,COND(<=),n -1, %arg2, fisync /* Outer loop decr */
214 fioneloop: /* Loop if LOOP = 1 */
215 /* Some implementations may flush with a single fice instruction */
216 cmpib,COND(>>=),n 15, %arg2, fioneloop2
219 fice,m %arg1(%sr1, %arg0)
220 fice,m %arg1(%sr1, %arg0)
221 fice,m %arg1(%sr1, %arg0)
222 fice,m %arg1(%sr1, %arg0)
223 fice,m %arg1(%sr1, %arg0)
224 fice,m %arg1(%sr1, %arg0)
225 fice,m %arg1(%sr1, %arg0)
226 fice,m %arg1(%sr1, %arg0)
227 fice,m %arg1(%sr1, %arg0)
228 fice,m %arg1(%sr1, %arg0)
229 fice,m %arg1(%sr1, %arg0)
230 fice,m %arg1(%sr1, %arg0)
231 fice,m %arg1(%sr1, %arg0)
232 fice,m %arg1(%sr1, %arg0)
233 fice,m %arg1(%sr1, %arg0)
234 addib,COND(>) -16, %arg2, fioneloop1
235 fice,m %arg1(%sr1, %arg0)
238 cmpb,COND(=),n %arg2, %r0, fisync /* Predict branch taken */
241 addib,COND(>) -1, %arg2, fioneloop2 /* Outer loop count decr */
242 fice,m %arg1(%sr1, %arg0) /* Fice for one loop */
246 mtsm %r22 /* restore I-bit */
247 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
250 ENDPROC_CFI(flush_instruction_cache_local)
253 .import cache_info, data
254 ENTRY_CFI(flush_data_cache_local)
255 88: load32 cache_info, %r1
257 /* Flush Data Cache */
259 LDREG DCACHE_BASE(%r1), %arg0
260 LDREG DCACHE_STRIDE(%r1), %arg1
261 LDREG DCACHE_COUNT(%r1), %arg2
262 LDREG DCACHE_LOOP(%r1), %arg3
263 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
265 addib,COND(=) -1, %arg3, fdoneloop /* Preadjust and test */
266 movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */
268 fdmanyloop: /* Loop if LOOP >= 2 */
269 addib,COND(>) -1, %r31, fdmanyloop /* Adjusted inner loop decr */
270 fdce %r0(%sr1, %arg0)
271 fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */
272 movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */
273 addib,COND(<=),n -1, %arg2, fdsync /* Outer loop decr */
275 fdoneloop: /* Loop if LOOP = 1 */
276 /* Some implementations may flush with a single fdce instruction */
277 cmpib,COND(>>=),n 15, %arg2, fdoneloop2
280 fdce,m %arg1(%sr1, %arg0)
281 fdce,m %arg1(%sr1, %arg0)
282 fdce,m %arg1(%sr1, %arg0)
283 fdce,m %arg1(%sr1, %arg0)
284 fdce,m %arg1(%sr1, %arg0)
285 fdce,m %arg1(%sr1, %arg0)
286 fdce,m %arg1(%sr1, %arg0)
287 fdce,m %arg1(%sr1, %arg0)
288 fdce,m %arg1(%sr1, %arg0)
289 fdce,m %arg1(%sr1, %arg0)
290 fdce,m %arg1(%sr1, %arg0)
291 fdce,m %arg1(%sr1, %arg0)
292 fdce,m %arg1(%sr1, %arg0)
293 fdce,m %arg1(%sr1, %arg0)
294 fdce,m %arg1(%sr1, %arg0)
295 addib,COND(>) -16, %arg2, fdoneloop1
296 fdce,m %arg1(%sr1, %arg0)
299 cmpb,COND(=),n %arg2, %r0, fdsync /* Predict branch taken */
302 addib,COND(>) -1, %arg2, fdoneloop2 /* Outer loop count decr */
303 fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */
308 mtsm %r22 /* restore I-bit */
309 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
312 ENDPROC_CFI(flush_data_cache_local)
314 /* Macros to serialize TLB purge operations on SMP. */
316 .macro tlb_lock la,flags,tmp
319 #if __PA_LDCW_ALIGNMENT > 4
320 load32 pa_tlb_lock + __PA_LDCW_ALIGNMENT-1, \la
321 depi 0,31,__PA_LDCW_ALIGN_ORDER, \la
323 load32 pa_tlb_lock, \la
333 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
337 .macro tlb_unlock la,flags,tmp
343 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
347 /* Clear page using kernel mapping. */
349 ENTRY_CFI(clear_page_asm)
352 /* Unroll the loop. */
353 ldi (PAGE_SIZE / 128), %r1
373 /* Note reverse branch hint for addib is taken. */
374 addib,COND(>),n -1, %r1, 1b
380 * Note that until (if) we start saving the full 64-bit register
381 * values on interrupt, we can't use std on a 32 bit kernel.
383 ldi (PAGE_SIZE / 64), %r1
403 addib,COND(>),n -1, %r1, 1b
408 ENDPROC_CFI(clear_page_asm)
410 /* Copy page using kernel mapping. */
412 ENTRY_CFI(copy_page_asm)
414 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
415 * Unroll the loop by hand and arrange insn appropriately.
416 * Prefetch doesn't improve performance on rp3440.
417 * GCC probably can do this just as well...
420 ldi (PAGE_SIZE / 128), %r1
464 /* Note reverse branch hint for addib is taken. */
465 addib,COND(>),n -1, %r1, 1b
471 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
472 * bundles (very restricted rules for bundling).
473 * Note that until (if) we start saving
474 * the full 64 bit register values on interrupt, we can't
475 * use ldd/std on a 32 bit kernel.
478 ldi (PAGE_SIZE / 64), %r1
514 addib,COND(>),n -1, %r1, 1b
519 ENDPROC_CFI(copy_page_asm)
522 * NOTE: Code in clear_user_page has a hard coded dependency on the
523 * maximum alias boundary being 4 Mb. We've been assured by the
524 * parisc chip designers that there will not ever be a parisc
525 * chip with a larger alias boundary (Never say never :-) ).
527 * Subtle: the dtlb miss handlers support the temp alias region by
528 * "knowing" that if a dtlb miss happens within the temp alias
529 * region it must have occurred while in clear_user_page. Since
530 * this routine makes use of processor local translations, we
531 * don't want to insert them into the kernel page table. Instead,
532 * we load up some general registers (they need to be registers
533 * which aren't shadowed) with the physical page numbers (preshifted
534 * for tlb insertion) needed to insert the translations. When we
535 * miss on the translation, the dtlb miss handler inserts the
536 * translation into the tlb using these values:
538 * %r26 physical page (shifted for tlb insert) of "to" translation
539 * %r23 physical page (shifted for tlb insert) of "from" translation
542 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
543 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
544 .macro convert_phys_for_tlb_insert20 phys
545 extrd,u \phys, 56-PAGE_ADD_SHIFT, 32-PAGE_ADD_SHIFT, \phys
546 #if _PAGE_SIZE_ENCODING_DEFAULT
547 depdi _PAGE_SIZE_ENCODING_DEFAULT, 63, (63-58), \phys
552 * copy_user_page_asm() performs a page copy using mappings
553 * equivalent to the user page mappings. It can be used to
554 * implement copy_user_page() but unfortunately both the `from'
555 * and `to' pages need to be flushed through mappings equivalent
556 * to the user mappings after the copy because the kernel accesses
557 * the `from' page through the kmap kernel mapping and the `to'
558 * page needs to be flushed since code can be copied. As a
559 * result, this implementation is less efficient than the simpler
560 * copy using the kernel mapping. It only needs the `from' page
561 * to flushed via the user mapping. The kunmap routines handle
562 * the flushes needed for the kernel mapping.
564 * I'm still keeping this around because it may be possible to
565 * use it if more information is passed into copy_user_page().
566 * Have to do some measurements to see if it is worthwhile to
567 * lobby for such a change.
571 ENTRY_CFI(copy_user_page_asm)
572 /* Convert virtual `to' and `from' addresses to physical addresses.
573 Move `from' physical address to non shadowed register. */
574 ldil L%(__PAGE_OFFSET), %r1
578 ldil L%(TMPALIAS_MAP_START), %r28
580 #if (TMPALIAS_MAP_START >= 0x80000000)
581 depdi 0, 31,32, %r28 /* clear any sign extension */
583 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
584 convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */
585 depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
586 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
588 depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */
590 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
591 extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */
592 depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */
593 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
595 depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */
598 /* Purge any old translations */
604 tlb_lock %r20,%r21,%r22
607 tlb_unlock %r20,%r21,%r22
608 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
609 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
613 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
614 * Unroll the loop by hand and arrange insn appropriately.
615 * GCC probably can do this just as well.
619 ldi (PAGE_SIZE / 128), %r1
663 /* conditional branches nullify on forward taken branch, and on
664 * non-taken backward branch. Note that .+4 is a backwards branch.
665 * The ldd should only get executed if the branch is taken.
667 addib,COND(>),n -1, %r1, 1b /* bundle 10 */
668 ldd 0(%r29), %r19 /* start next loads */
671 ldi (PAGE_SIZE / 64), %r1
674 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
675 * bundles (very restricted rules for bundling). It probably
676 * does OK on PCXU and better, but we could do better with
677 * ldd/std instructions. Note that until (if) we start saving
678 * the full 64 bit register values on interrupt, we can't
679 * use ldd/std on a 32 bit kernel.
716 addib,COND(>) -1, %r1,1b
722 ENDPROC_CFI(copy_user_page_asm)
724 ENTRY_CFI(clear_user_page_asm)
727 ldil L%(TMPALIAS_MAP_START), %r28
729 #if (TMPALIAS_MAP_START >= 0x80000000)
730 depdi 0, 31,32, %r28 /* clear any sign extension */
732 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
733 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
734 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
736 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
737 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
738 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
741 /* Purge any old translation */
746 tlb_lock %r20,%r21,%r22
748 tlb_unlock %r20,%r21,%r22
749 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
753 ldi (PAGE_SIZE / 128), %r1
755 /* PREFETCH (Write) has not (yet) been proven to help here */
756 /* #define PREFETCHW_OP ldd 256(%0), %r0 */
774 addib,COND(>) -1, %r1, 1b
777 #else /* ! CONFIG_64BIT */
778 ldi (PAGE_SIZE / 64), %r1
796 addib,COND(>) -1, %r1, 1b
798 #endif /* CONFIG_64BIT */
802 ENDPROC_CFI(clear_user_page_asm)
804 ENTRY_CFI(flush_dcache_page_asm)
805 ldil L%(TMPALIAS_MAP_START), %r28
807 #if (TMPALIAS_MAP_START >= 0x80000000)
808 depdi 0, 31,32, %r28 /* clear any sign extension */
810 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
811 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
812 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
814 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
815 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
816 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
819 /* Purge any old translation */
824 tlb_lock %r20,%r21,%r22
826 tlb_unlock %r20,%r21,%r22
827 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
830 88: ldil L%dcache_stride, %r1
831 ldw R%dcache_stride(%r1), r31
834 depdi,z 1, 63-PAGE_SHIFT,1, %r25
836 depwi,z 1, 31-PAGE_SHIFT,1, %r25
856 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
859 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
863 ENDPROC_CFI(flush_dcache_page_asm)
865 ENTRY_CFI(purge_dcache_page_asm)
866 ldil L%(TMPALIAS_MAP_START), %r28
868 #if (TMPALIAS_MAP_START >= 0x80000000)
869 depdi 0, 31,32, %r28 /* clear any sign extension */
871 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
872 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
873 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
875 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
876 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
877 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
880 /* Purge any old translation */
885 tlb_lock %r20,%r21,%r22
887 tlb_unlock %r20,%r21,%r22
888 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
891 88: ldil L%dcache_stride, %r1
892 ldw R%dcache_stride(%r1), r31
895 depdi,z 1, 63-PAGE_SHIFT,1, %r25
897 depwi,z 1, 31-PAGE_SHIFT,1, %r25
917 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
920 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
924 ENDPROC_CFI(purge_dcache_page_asm)
926 ENTRY_CFI(flush_icache_page_asm)
927 ldil L%(TMPALIAS_MAP_START), %r28
929 #if (TMPALIAS_MAP_START >= 0x80000000)
930 depdi 0, 31,32, %r28 /* clear any sign extension */
932 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
933 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
934 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
936 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
937 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
938 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
941 /* Purge any old translation. Note that the FIC instruction
942 * may use either the instruction or data TLB. Given that we
943 * have a flat address space, it's not clear which TLB will be
944 * used. So, we purge both entries. */
948 1: pitlb,l %r0(%sr4,%r28)
949 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
951 tlb_lock %r20,%r21,%r22
953 1: pitlb %r0(%sr4,%r28)
954 tlb_unlock %r20,%r21,%r22
955 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
956 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
957 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
960 88: ldil L%icache_stride, %r1
961 ldw R%icache_stride(%r1), %r31
964 depdi,z 1, 63-PAGE_SHIFT,1, %r25
966 depwi,z 1, 31-PAGE_SHIFT,1, %r25
971 /* fic only has the type 26 form on PA1.1, requiring an
972 * explicit space specification, so use %sr4 */
973 1: fic,m %r31(%sr4,%r28)
974 fic,m %r31(%sr4,%r28)
975 fic,m %r31(%sr4,%r28)
976 fic,m %r31(%sr4,%r28)
977 fic,m %r31(%sr4,%r28)
978 fic,m %r31(%sr4,%r28)
979 fic,m %r31(%sr4,%r28)
980 fic,m %r31(%sr4,%r28)
981 fic,m %r31(%sr4,%r28)
982 fic,m %r31(%sr4,%r28)
983 fic,m %r31(%sr4,%r28)
984 fic,m %r31(%sr4,%r28)
985 fic,m %r31(%sr4,%r28)
986 fic,m %r31(%sr4,%r28)
987 fic,m %r31(%sr4,%r28)
988 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
989 fic,m %r31(%sr4,%r28)
991 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
995 ENDPROC_CFI(flush_icache_page_asm)
997 ENTRY_CFI(flush_kernel_dcache_page_asm)
998 88: ldil L%dcache_stride, %r1
999 ldw R%dcache_stride(%r1), %r23
1002 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1004 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1006 add %r26, %r25, %r25
1007 sub %r25, %r23, %r25
1024 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
1027 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1031 ENDPROC_CFI(flush_kernel_dcache_page_asm)
1033 ENTRY_CFI(purge_kernel_dcache_page_asm)
1034 88: ldil L%dcache_stride, %r1
1035 ldw R%dcache_stride(%r1), %r23
1038 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1040 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1042 add %r26, %r25, %r25
1043 sub %r25, %r23, %r25
1060 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
1063 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1067 ENDPROC_CFI(purge_kernel_dcache_page_asm)
1069 ENTRY_CFI(flush_user_dcache_range_asm)
1070 88: ldil L%dcache_stride, %r1
1071 ldw R%dcache_stride(%r1), %r23
1073 ANDCM %r26, %r21, %r26
1076 depd,z %r23, 59, 60, %r21
1078 depw,z %r23, 27, 28, %r21
1080 add %r26, %r21, %r22
1081 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1082 1: add %r22, %r21, %r22
1083 fdc,m %r23(%sr3, %r26)
1084 fdc,m %r23(%sr3, %r26)
1085 fdc,m %r23(%sr3, %r26)
1086 fdc,m %r23(%sr3, %r26)
1087 fdc,m %r23(%sr3, %r26)
1088 fdc,m %r23(%sr3, %r26)
1089 fdc,m %r23(%sr3, %r26)
1090 fdc,m %r23(%sr3, %r26)
1091 fdc,m %r23(%sr3, %r26)
1092 fdc,m %r23(%sr3, %r26)
1093 fdc,m %r23(%sr3, %r26)
1094 fdc,m %r23(%sr3, %r26)
1095 fdc,m %r23(%sr3, %r26)
1096 fdc,m %r23(%sr3, %r26)
1097 fdc,m %r23(%sr3, %r26)
1098 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1099 fdc,m %r23(%sr3, %r26)
1101 2: cmpb,COND(>>),n %r25, %r26, 2b
1102 fdc,m %r23(%sr3, %r26)
1104 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1108 ENDPROC_CFI(flush_user_dcache_range_asm)
1110 ENTRY_CFI(flush_kernel_dcache_range_asm)
1111 88: ldil L%dcache_stride, %r1
1112 ldw R%dcache_stride(%r1), %r23
1114 ANDCM %r26, %r21, %r26
1117 depd,z %r23, 59, 60, %r21
1119 depw,z %r23, 27, 28, %r21
1121 add %r26, %r21, %r22
1122 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1123 1: add %r22, %r21, %r22
1139 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1142 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1146 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1150 ENDPROC_CFI(flush_kernel_dcache_range_asm)
1152 ENTRY_CFI(purge_kernel_dcache_range_asm)
1153 88: ldil L%dcache_stride, %r1
1154 ldw R%dcache_stride(%r1), %r23
1156 ANDCM %r26, %r21, %r26
1159 depd,z %r23, 59, 60, %r21
1161 depw,z %r23, 27, 28, %r21
1163 add %r26, %r21, %r22
1164 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1165 1: add %r22, %r21, %r22
1181 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1184 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1188 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1192 ENDPROC_CFI(purge_kernel_dcache_range_asm)
1194 ENTRY_CFI(flush_user_icache_range_asm)
1195 88: ldil L%icache_stride, %r1
1196 ldw R%icache_stride(%r1), %r23
1198 ANDCM %r26, %r21, %r26
1201 depd,z %r23, 59, 60, %r21
1203 depw,z %r23, 27, 28, %r21
1205 add %r26, %r21, %r22
1206 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1207 1: add %r22, %r21, %r22
1208 fic,m %r23(%sr3, %r26)
1209 fic,m %r23(%sr3, %r26)
1210 fic,m %r23(%sr3, %r26)
1211 fic,m %r23(%sr3, %r26)
1212 fic,m %r23(%sr3, %r26)
1213 fic,m %r23(%sr3, %r26)
1214 fic,m %r23(%sr3, %r26)
1215 fic,m %r23(%sr3, %r26)
1216 fic,m %r23(%sr3, %r26)
1217 fic,m %r23(%sr3, %r26)
1218 fic,m %r23(%sr3, %r26)
1219 fic,m %r23(%sr3, %r26)
1220 fic,m %r23(%sr3, %r26)
1221 fic,m %r23(%sr3, %r26)
1222 fic,m %r23(%sr3, %r26)
1223 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1224 fic,m %r23(%sr3, %r26)
1226 2: cmpb,COND(>>),n %r25, %r26, 2b
1227 fic,m %r23(%sr3, %r26)
1229 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1233 ENDPROC_CFI(flush_user_icache_range_asm)
1235 ENTRY_CFI(flush_kernel_icache_page)
1236 88: ldil L%icache_stride, %r1
1237 ldw R%icache_stride(%r1), %r23
1240 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1242 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1244 add %r26, %r25, %r25
1245 sub %r25, %r23, %r25
1248 1: fic,m %r23(%sr4, %r26)
1249 fic,m %r23(%sr4, %r26)
1250 fic,m %r23(%sr4, %r26)
1251 fic,m %r23(%sr4, %r26)
1252 fic,m %r23(%sr4, %r26)
1253 fic,m %r23(%sr4, %r26)
1254 fic,m %r23(%sr4, %r26)
1255 fic,m %r23(%sr4, %r26)
1256 fic,m %r23(%sr4, %r26)
1257 fic,m %r23(%sr4, %r26)
1258 fic,m %r23(%sr4, %r26)
1259 fic,m %r23(%sr4, %r26)
1260 fic,m %r23(%sr4, %r26)
1261 fic,m %r23(%sr4, %r26)
1262 fic,m %r23(%sr4, %r26)
1263 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
1264 fic,m %r23(%sr4, %r26)
1266 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1270 ENDPROC_CFI(flush_kernel_icache_page)
1272 ENTRY_CFI(flush_kernel_icache_range_asm)
1273 88: ldil L%icache_stride, %r1
1274 ldw R%icache_stride(%r1), %r23
1276 ANDCM %r26, %r21, %r26
1279 depd,z %r23, 59, 60, %r21
1281 depw,z %r23, 27, 28, %r21
1283 add %r26, %r21, %r22
1284 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1285 1: add %r22, %r21, %r22
1286 fic,m %r23(%sr4, %r26)
1287 fic,m %r23(%sr4, %r26)
1288 fic,m %r23(%sr4, %r26)
1289 fic,m %r23(%sr4, %r26)
1290 fic,m %r23(%sr4, %r26)
1291 fic,m %r23(%sr4, %r26)
1292 fic,m %r23(%sr4, %r26)
1293 fic,m %r23(%sr4, %r26)
1294 fic,m %r23(%sr4, %r26)
1295 fic,m %r23(%sr4, %r26)
1296 fic,m %r23(%sr4, %r26)
1297 fic,m %r23(%sr4, %r26)
1298 fic,m %r23(%sr4, %r26)
1299 fic,m %r23(%sr4, %r26)
1300 fic,m %r23(%sr4, %r26)
1301 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1302 fic,m %r23(%sr4, %r26)
1304 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1305 fic,m %r23(%sr4, %r26)
1307 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1311 ENDPROC_CFI(flush_kernel_icache_range_asm)
1315 /* align should cover use of rfi in disable_sr_hashing_asm and
1319 ENTRY_CFI(disable_sr_hashing_asm)
1321 * Switch to real mode
1332 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1333 mtctl %r0, %cr17 /* Clear IIASQ tail */
1334 mtctl %r0, %cr17 /* Clear IIASQ head */
1335 mtctl %r1, %cr18 /* IIAOQ head */
1337 mtctl %r1, %cr18 /* IIAOQ tail */
1338 load32 REAL_MODE_PSW, %r1
1343 1: cmpib,=,n SRHASH_PCXST, %r26,srdis_pcxs
1344 cmpib,=,n SRHASH_PCXL, %r26,srdis_pcxl
1345 cmpib,=,n SRHASH_PA20, %r26,srdis_pa20
1350 /* Disable Space Register Hashing for PCXS,PCXT,PCXT' */
1352 .word 0x141c1a00 /* mfdiag %dr0, %r28 */
1353 .word 0x141c1a00 /* must issue twice */
1354 depwi 0,18,1, %r28 /* Clear DHE (dcache hash enable) */
1355 depwi 0,20,1, %r28 /* Clear IHE (icache hash enable) */
1356 .word 0x141c1600 /* mtdiag %r28, %dr0 */
1357 .word 0x141c1600 /* must issue twice */
1362 /* Disable Space Register Hashing for PCXL */
1364 .word 0x141c0600 /* mfdiag %dr0, %r28 */
1365 depwi 0,28,2, %r28 /* Clear DHASH_EN & IHASH_EN */
1366 .word 0x141c0240 /* mtdiag %r28, %dr0 */
1371 /* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
1373 .word 0x144008bc /* mfdiag %dr2, %r28 */
1374 depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */
1375 .word 0x145c1840 /* mtdiag %r28, %dr2 */
1379 /* Switch back to virtual mode */
1380 rsm PSW_SM_I, %r0 /* prep to load iia queue */
1388 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1389 mtctl %r0, %cr17 /* Clear IIASQ tail */
1390 mtctl %r0, %cr17 /* Clear IIASQ head */
1391 mtctl %r1, %cr18 /* IIAOQ head */
1393 mtctl %r1, %cr18 /* IIAOQ tail */
1394 load32 KERNEL_PSW, %r1
1401 ENDPROC_CFI(disable_sr_hashing_asm)