2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/asm-offsets.h>
27 /* we have the following possibilities to act on an interruption:
28 * - handle in assembly and use shadowed registers only
29 * - save registers to kernel stack and handle in assembly or C */
33 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
34 #include <asm/assembly.h> /* for LDREG/STREG defines */
35 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
39 #include <asm/traps.h>
40 #include <asm/thread_info.h>
41 #include <asm/alternative.h>
43 #include <linux/linkage.h>
51 .import pa_tlb_lock,data
52 .macro load_pa_tlb_lock reg
53 #if __PA_LDCW_ALIGNMENT > 4
54 load32 PA(pa_tlb_lock) + __PA_LDCW_ALIGNMENT-1, \reg
55 depi 0,31,__PA_LDCW_ALIGN_ORDER, \reg
57 load32 PA(pa_tlb_lock), \reg
61 /* space_to_prot macro creates a prot id from a space id */
63 #if (SPACEID_SHIFT) == 0
64 .macro space_to_prot spc prot
65 depd,z \spc,62,31,\prot
68 .macro space_to_prot spc prot
69 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
73 /* Switch to virtual mapping, trashing only %r1 */
76 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
81 load32 KERNEL_PSW, %r1
83 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
84 mtctl %r0, %cr17 /* Clear IIASQ tail */
85 mtctl %r0, %cr17 /* Clear IIASQ head */
88 mtctl %r1, %cr18 /* Set IIAOQ tail */
90 mtctl %r1, %cr18 /* Set IIAOQ head */
97 * The "get_stack" macros are responsible for determining the
101 * Already using a kernel stack, so call the
102 * get_stack_use_r30 macro to push a pt_regs structure
103 * on the stack, and store registers there.
105 * Need to set up a kernel stack, so call the
106 * get_stack_use_cr30 macro to set up a pointer
107 * to the pt_regs structure contained within the
108 * task pointer pointed to by cr30. Set the stack
109 * pointer to point to the end of the task structure.
111 * Note that we use shadowed registers for temps until
112 * we can save %r26 and %r29. %r26 is used to preserve
113 * %r8 (a shadowed register) which temporarily contained
114 * either the fault type ("code") or the eirr. We need
115 * to use a non-shadowed register to carry the value over
116 * the rfir in virt_map. We use %r26 since this value winds
117 * up being passed as the argument to either do_cpu_irq_mask
118 * or handle_interruption. %r29 is used to hold a pointer
119 * the register save area, and once again, it needs to
120 * be a non-shadowed register so that it survives the rfir.
122 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
125 .macro get_stack_use_cr30
127 /* we save the registers in the task struct */
131 ldo THREAD_SZ_ALGN(%r1), %r30
135 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
137 ldo TASK_REGS(%r9),%r9
138 STREG %r17,PT_GR30(%r9)
139 STREG %r29,PT_GR29(%r9)
140 STREG %r26,PT_GR26(%r9)
141 STREG %r16,PT_SR7(%r9)
145 .macro get_stack_use_r30
147 /* we put a struct pt_regs on the stack and save the registers there */
151 ldo PT_SZ_ALGN(%r30),%r30
152 STREG %r1,PT_GR30(%r9)
153 STREG %r29,PT_GR29(%r9)
154 STREG %r26,PT_GR26(%r9)
155 STREG %r16,PT_SR7(%r9)
160 LDREG PT_GR1(%r29), %r1
161 LDREG PT_GR30(%r29),%r30
162 LDREG PT_GR29(%r29),%r29
165 /* default interruption handler
166 * (calls traps.c:handle_interruption) */
173 /* Interrupt interruption handler
174 * (calls irq.c:do_cpu_irq_mask) */
181 .import os_hpmc, code
185 nop /* must be a NOP, will be patched later */
186 load32 PA(os_hpmc), %r3
189 .word 0 /* checksum (will be patched) */
190 .word 0 /* address of handler */
191 .word 0 /* length of handler */
195 * Performance Note: Instructions will be moved up into
196 * this part of the code later on, once we are sure
197 * that the tlb miss handlers are close to final form.
200 /* Register definitions for tlb miss handler macros */
202 va = r8 /* virtual address for which the trap occurred */
203 spc = r24 /* space for which the trap occurred */
208 * itlb miss interruption handler (parisc 1.1 - 32 bit)
222 * itlb miss interruption handler (parisc 2.0)
239 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
242 .macro naitlb_11 code
253 * naitlb miss interruption handler (parisc 2.0)
256 .macro naitlb_20 code
271 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
285 * dtlb miss interruption handler (parisc 2.0)
302 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
304 .macro nadtlb_11 code
314 /* nadtlb miss interruption handler (parisc 2.0) */
316 .macro nadtlb_20 code
331 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
345 * dirty bit trap interruption handler (parisc 2.0)
361 /* In LP64, the space contains part of the upper 32 bits of the
362 * fault. We have to extract this and place it in the va,
363 * zeroing the corresponding bits in the space register */
364 .macro space_adjust spc,va,tmp
366 extrd,u \spc,63,SPACEID_SHIFT,\tmp
367 depd %r0,63,SPACEID_SHIFT,\spc
368 depd \tmp,31,SPACEID_SHIFT,\va
372 .import swapper_pg_dir,code
374 /* Get the pgd. For faults on space zero (kernel space), this
375 * is simply swapper_pg_dir. For user space faults, the
376 * pgd is stored in %cr25 */
377 .macro get_pgd spc,reg
378 ldil L%PA(swapper_pg_dir),\reg
379 ldo R%PA(swapper_pg_dir)(\reg),\reg
380 or,COND(=) %r0,\spc,%r0
385 space_check(spc,tmp,fault)
387 spc - The space we saw the fault with.
388 tmp - The place to store the current space.
389 fault - Function to call on failure.
391 Only allow faults on different spaces from the
392 currently active one if we're the kernel
395 .macro space_check spc,tmp,fault
397 /* check against %r0 which is same value as LINUX_GATEWAY_SPACE */
398 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
399 * as kernel, so defeat the space
402 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
403 cmpb,COND(<>),n \tmp,\spc,\fault
406 /* Look up a PTE in a 2-Level scheme (faulting at each
407 * level if the entry isn't present
409 * NOTE: we use ldw even for LP64, since the short pointers
410 * can address up to 1TB
412 .macro L2_ptep pmd,pte,index,va,fault
413 #if CONFIG_PGTABLE_LEVELS == 3
414 extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
416 # if defined(CONFIG_64BIT)
417 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
419 # if PAGE_SIZE > 4096
420 extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
422 extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
426 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
428 ldw,s \index(\pmd),\pmd
429 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
430 dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
431 SHLREG \pmd,PxD_VALUE_SHIFT,\pmd
432 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
433 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
434 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
437 /* Look up PTE in a 3-Level scheme.
439 * Here we implement a Hybrid L2/L3 scheme: we allocate the
440 * first pmd adjacent to the pgd. This means that we can
441 * subtract a constant offset to get to it. The pmd and pgd
442 * sizes are arranged so that a single pmd covers 4GB (giving
443 * a full LP64 process access to 8TB) so our lookups are
444 * effectively L2 for the first 4GB of the kernel (i.e. for
445 * all ILP32 processes and all the kernel for machines with
446 * under 4GB of memory) */
447 .macro L3_ptep pgd,pte,index,va,fault
448 #if CONFIG_PGTABLE_LEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
449 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
450 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
451 ldw,s \index(\pgd),\pgd
452 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
453 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
454 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
455 shld \pgd,PxD_VALUE_SHIFT,\index
456 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
458 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
459 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
461 L2_ptep \pgd,\pte,\index,\va,\fault
464 /* Acquire pa_tlb_lock lock and check page is present. */
465 .macro tlb_lock spc,ptp,pte,tmp,tmp1,fault
467 98: cmpib,COND(=),n 0,\spc,2f
468 load_pa_tlb_lock \tmp
469 1: LDCW 0(\tmp),\tmp1
470 cmpib,COND(=) 0,\tmp1,1b
473 bb,<,n \pte,_PAGE_PRESENT_BIT,3f
476 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
478 2: LDREG 0(\ptp),\pte
479 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
483 /* Release pa_tlb_lock lock without reloading lock address. */
484 .macro tlb_unlock0 spc,tmp
486 98: or,COND(=) %r0,\spc,%r0
488 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
492 /* Release pa_tlb_lock lock. */
493 .macro tlb_unlock1 spc,tmp
495 98: load_pa_tlb_lock \tmp
496 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
497 tlb_unlock0 \spc,\tmp
501 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
502 * don't needlessly dirty the cache line if it was already set */
503 .macro update_accessed ptp,pte,tmp,tmp1
504 ldi _PAGE_ACCESSED,\tmp1
506 and,COND(<>) \tmp1,\pte,%r0
510 /* Set the dirty bit (and accessed bit). No need to be
511 * clever, this is only used from the dirty fault */
512 .macro update_dirty ptp,pte,tmp
513 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
518 /* We have (depending on the page size):
519 * - 38 to 52-bit Physical Page Number
520 * - 12 to 26-bit page offset
522 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
523 * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
524 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
525 #define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12)
527 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
528 .macro convert_for_tlb_insert20 pte,tmp
529 #ifdef CONFIG_HUGETLB_PAGE
531 extrd,u \tmp,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
532 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
534 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
535 (63-58)+PAGE_ADD_SHIFT,\pte
536 extrd,u,*= \tmp,_PAGE_HPAGE_BIT+32,1,%r0
537 depdi _HUGE_PAGE_SIZE_ENCODING_DEFAULT,63,\
538 (63-58)+PAGE_ADD_HUGE_SHIFT,\pte
539 #else /* Huge pages disabled */
540 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
541 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
542 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
543 (63-58)+PAGE_ADD_SHIFT,\pte
547 /* Convert the pte and prot to tlb insertion values. How
548 * this happens is quite subtle, read below */
549 .macro make_insert_tlb spc,pte,prot,tmp
550 space_to_prot \spc \prot /* create prot id from space */
551 /* The following is the real subtlety. This is depositing
552 * T <-> _PAGE_REFTRAP
554 * B <-> _PAGE_DMB (memory break)
556 * Then incredible subtlety: The access rights are
557 * _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE
558 * See 3-14 of the parisc 2.0 manual
560 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
561 * trigger an access rights trap in user space if the user
562 * tries to read an unreadable page */
565 /* PAGE_USER indicates the page can be read with user privileges,
566 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
567 * contains _PAGE_READ) */
568 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
570 /* If we're a gateway page, drop PL2 back to zero for promotion
571 * to kernel privilege (so we can execute the page as kernel).
572 * Any privilege promotion page always denys read and write */
573 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
574 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
576 /* Enforce uncacheable pages.
577 * This should ONLY be use for MMIO on PA 2.0 machines.
578 * Memory/DMA is cache coherent on all PA2.0 machines we support
579 * (that means T-class is NOT supported) and the memory controllers
580 * on most of those machines only handles cache transactions.
582 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
585 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
586 convert_for_tlb_insert20 \pte \tmp
589 /* Identical macro to make_insert_tlb above, except it
590 * makes the tlb entry for the differently formatted pa11
591 * insertion instructions */
592 .macro make_insert_tlb_11 spc,pte,prot
593 zdep \spc,30,15,\prot
595 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
597 extru,= \pte,_PAGE_USER_BIT,1,%r0
598 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
599 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
600 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
602 /* Get rid of prot bits and convert to page addr for iitlba */
604 depi 0,31,ASM_PFN_PTE_SHIFT,\pte
605 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
608 /* This is for ILP32 PA2.0 only. The TLB insertion needs
609 * to extend into I/O space if the address is 0xfXXXXXXX
610 * so we extend the f's into the top word of the pte in
612 .macro f_extend pte,tmp
613 extrd,s \pte,42,4,\tmp
615 extrd,s \pte,63,25,\pte
618 /* The alias region is an 8MB aligned 16MB to do clear and
619 * copy user pages at addresses congruent with the user
622 * To use the alias page, you set %r26 up with the to TLB
623 * entry (identifying the physical page) and %r23 up with
624 * the from tlb entry (or nothing if only a to entry---for
625 * clear_user_page_asm) */
626 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault,patype
627 cmpib,COND(<>),n 0,\spc,\fault
628 ldil L%(TMPALIAS_MAP_START),\tmp
629 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
630 /* on LP64, ldi will sign extend into the upper 32 bits,
631 * which is behaviour we don't want */
636 cmpb,COND(<>),n \tmp,\tmp1,\fault
637 mfctl %cr19,\tmp /* iir */
638 /* get the opcode (first six bits) into \tmp */
639 extrw,u \tmp,5,6,\tmp
641 * Only setting the T bit prevents data cache movein
642 * Setting access rights to zero prevents instruction cache movein
644 * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
645 * to type field and _PAGE_READ goes to top bit of PL1
647 ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
649 * so if the opcode is one (i.e. this is a memory management
650 * instruction) nullify the next load so \prot is only T.
651 * Otherwise this is a normal data operation
653 cmpiclr,= 0x01,\tmp,%r0
654 ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
656 depd,z \prot,8,7,\prot
659 depw,z \prot,8,7,\prot
661 .error "undefined PA type to do_alias"
665 * OK, it is in the temp alias region, check whether "from" or "to".
666 * Check "subtle" note in pacache.S re: r23/r26.
669 extrd,u,*= \va,41,1,%r0
671 extrw,u,= \va,9,1,%r0
673 or,COND(tr) %r23,%r0,\pte
679 * Fault_vectors are architecturally required to be aligned on a 2K
686 ENTRY(fault_vector_20)
687 /* First vector is invalid (0) */
688 .ascii "cows can fly"
697 itlb_20 PARISC_ITLB_TRAP
729 ENTRY(fault_vector_11)
730 /* First vector is invalid (0) */
731 .ascii "cows can fly"
740 itlb_11 PARISC_ITLB_TRAP
769 /* Fault vector is separately protected and *must* be on its own page */
772 .import handle_interruption,code
773 .import do_cpu_irq_mask,code
778 * copy_thread moved args into task save area.
781 ENTRY(ret_from_kernel_thread)
782 /* Call schedule_tail first though */
783 BL schedule_tail, %r2
786 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
787 LDREG TASK_PT_GR25(%r1), %r26
789 LDREG TASK_PT_GR27(%r1), %r27
791 LDREG TASK_PT_GR26(%r1), %r1
794 b finish_child_return
796 END(ret_from_kernel_thread)
800 * struct task_struct *_switch_to(struct task_struct *prev,
801 * struct task_struct *next)
803 * switch kernel stacks and return prev */
804 ENTRY_CFI(_switch_to)
805 STREG %r2, -RP_OFFSET(%r30)
810 load32 _switch_to_ret, %r2
812 STREG %r2, TASK_PT_KPC(%r26)
813 LDREG TASK_PT_KPC(%r25), %r2
815 STREG %r30, TASK_PT_KSP(%r26)
816 LDREG TASK_PT_KSP(%r25), %r30
817 LDREG TASK_THREAD_INFO(%r25), %r25
821 ENTRY(_switch_to_ret)
822 mtctl %r0, %cr0 /* Needed for single stepping */
826 LDREG -RP_OFFSET(%r30), %r2
829 ENDPROC_CFI(_switch_to)
832 * Common rfi return path for interruptions, kernel execve, and
833 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
834 * return via this path if the signal was received when the process
835 * was running; if the process was blocked on a syscall then the
836 * normal syscall_exit path is used. All syscalls for traced
837 * proceses exit via intr_restore.
839 * XXX If any syscalls that change a processes space id ever exit
840 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
847 ENTRY_CFI(syscall_exit_rfi)
849 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
850 ldo TASK_REGS(%r16),%r16
851 /* Force iaoq to userspace, as the user has had access to our current
852 * context via sigcontext. Also Filter the PSW for the same reason.
854 LDREG PT_IAOQ0(%r16),%r19
856 STREG %r19,PT_IAOQ0(%r16)
857 LDREG PT_IAOQ1(%r16),%r19
859 STREG %r19,PT_IAOQ1(%r16)
860 LDREG PT_PSW(%r16),%r19
861 load32 USER_PSW_MASK,%r1
863 load32 USER_PSW_HI_MASK,%r20
866 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
868 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
869 STREG %r19,PT_PSW(%r16)
872 * If we aren't being traced, we never saved space registers
873 * (we don't store them in the sigcontext), so set them
874 * to "proper" values now (otherwise we'll wind up restoring
875 * whatever was last stored in the task structure, which might
876 * be inconsistent if an interrupt occurred while on the gateway
877 * page). Note that we may be "trashing" values the user put in
878 * them, but we don't support the user changing them.
881 STREG %r0,PT_SR2(%r16)
883 STREG %r19,PT_SR0(%r16)
884 STREG %r19,PT_SR1(%r16)
885 STREG %r19,PT_SR3(%r16)
886 STREG %r19,PT_SR4(%r16)
887 STREG %r19,PT_SR5(%r16)
888 STREG %r19,PT_SR6(%r16)
889 STREG %r19,PT_SR7(%r16)
892 /* check for reschedule */
894 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
895 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
897 .import do_notify_resume,code
901 LDREG TI_FLAGS(%r1),%r19
902 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r20
903 and,COND(<>) %r19, %r20, %r0
904 b,n intr_restore /* skip past if we've nothing to do */
906 /* This check is critical to having LWS
907 * working. The IASQ is zero on the gateway
908 * page and we cannot deliver any signals until
909 * we get off the gateway page.
911 * Only do signals if we are returning to user space
913 LDREG PT_IASQ0(%r16), %r20
914 cmpib,COND(=),n LINUX_GATEWAY_SPACE, %r20, intr_restore /* backward */
915 LDREG PT_IASQ1(%r16), %r20
916 cmpib,COND(=),n LINUX_GATEWAY_SPACE, %r20, intr_restore /* backward */
918 /* NOTE: We need to enable interrupts if we have to deliver
919 * signals. We used to do this earlier but it caused kernel
920 * stack overflows. */
923 copy %r0, %r25 /* long in_syscall = 0 */
925 ldo -16(%r30),%r29 /* Reference param save area */
928 BL do_notify_resume,%r2
929 copy %r16, %r26 /* struct pt_regs *regs */
935 ldo PT_FR31(%r29),%r1
939 /* inverse of virt_map */
941 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
944 /* Restore space id's and special cr's from PT_REGS
945 * structure pointed to by r29
949 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
950 * It also restores r1 and r30.
957 #ifndef CONFIG_PREEMPT
958 # define intr_do_preempt intr_restore
959 #endif /* !CONFIG_PREEMPT */
961 .import schedule,code
963 /* Only call schedule on return to userspace. If we're returning
964 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
965 * we jump back to intr_restore.
967 LDREG PT_IASQ0(%r16), %r20
968 cmpib,COND(=) 0, %r20, intr_do_preempt
970 LDREG PT_IASQ1(%r16), %r20
971 cmpib,COND(=) 0, %r20, intr_do_preempt
974 /* NOTE: We need to enable interrupts if we schedule. We used
975 * to do this earlier but it caused kernel stack overflows. */
979 ldo -16(%r30),%r29 /* Reference param save area */
982 ldil L%intr_check_sig, %r2
986 load32 schedule, %r20
989 ldo R%intr_check_sig(%r2), %r2
991 /* preempt the current task on returning to kernel
992 * mode from an interrupt, iff need_resched is set,
993 * and preempt_count is 0. otherwise, we continue on
994 * our merry way back to the current running task.
996 #ifdef CONFIG_PREEMPT
997 .import preempt_schedule_irq,code
999 rsm PSW_SM_I, %r0 /* disable interrupts */
1001 /* current_thread_info()->preempt_count */
1003 LDREG TI_PRE_COUNT(%r1), %r19
1004 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
1005 nop /* prev insn branched backwards */
1007 /* check if we interrupted a critical path */
1008 LDREG PT_PSW(%r16), %r20
1009 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
1012 BL preempt_schedule_irq, %r2
1015 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
1016 #endif /* CONFIG_PREEMPT */
1019 * External interrupts.
1023 cmpib,COND(=),n 0,%r16,1f
1035 ldo PT_FR0(%r29), %r24
1040 copy %r29, %r26 /* arg0 is pt_regs */
1041 copy %r29, %r16 /* save pt_regs */
1043 ldil L%intr_return, %r2
1046 ldo -16(%r30),%r29 /* Reference param save area */
1050 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1051 ENDPROC_CFI(syscall_exit_rfi)
1054 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1056 ENTRY_CFI(intr_save) /* for os_hpmc */
1058 cmpib,COND(=),n 0,%r16,1f
1070 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1071 cmpib,COND(=),n PARISC_ITLB_TRAP,%r26,skip_save_ior
1075 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1081 * If the interrupted code was running with W bit off (32 bit),
1082 * clear the b bits (bits 0 & 1) in the ior.
1083 * save_specials left ipsw value in r8 for us to test.
1085 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1088 /* adjust isr/ior: get high bits from isr and deposit in ior */
1089 space_adjust %r16,%r17,%r1
1091 STREG %r16, PT_ISR(%r29)
1092 STREG %r17, PT_IOR(%r29)
1094 #if 0 && defined(CONFIG_64BIT)
1095 /* Revisit when we have 64-bit code above 4Gb */
1099 /* We have a itlb miss, and when executing code above 4 Gb on ILP64, we
1100 * need to adjust iasq/iaoq here in the same way we adjusted isr/ior
1103 extrd,u,* %r8,PSW_W_BIT,1,%r1
1104 cmpib,COND(=),n 1,%r1,intr_save2
1105 LDREG PT_IASQ0(%r29), %r16
1106 LDREG PT_IAOQ0(%r29), %r17
1107 /* adjust iasq/iaoq */
1108 space_adjust %r16,%r17,%r1
1109 STREG %r16, PT_IASQ0(%r29)
1110 STREG %r17, PT_IAOQ0(%r29)
1119 ldo PT_FR0(%r29), %r25
1124 copy %r29, %r25 /* arg1 is pt_regs */
1126 ldo -16(%r30),%r29 /* Reference param save area */
1129 ldil L%intr_check_sig, %r2
1130 copy %r25, %r16 /* save pt_regs */
1132 b handle_interruption
1133 ldo R%intr_check_sig(%r2), %r2
1134 ENDPROC_CFI(intr_save)
1138 * Note for all tlb miss handlers:
1140 * cr24 contains a pointer to the kernel address space
1143 * cr25 contains a pointer to the current user address
1144 * space page directory.
1146 * sr3 will contain the space id of the user address space
1147 * of the current running thread while that thread is
1148 * running in the kernel.
1152 * register number allocations. Note that these are all
1153 * in the shadowed registers
1156 t0 = r1 /* temporary register 0 */
1157 va = r8 /* virtual address for which the trap occurred */
1158 t1 = r9 /* temporary register 1 */
1159 pte = r16 /* pte/phys page # */
1160 prot = r17 /* prot bits */
1161 spc = r24 /* space for which the trap occurred */
1162 ptp = r25 /* page directory/page table pointer */
1167 space_adjust spc,va,t0
1169 space_check spc,t0,dtlb_fault
1171 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1173 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20w
1174 update_accessed ptp,pte,t0,t1
1176 make_insert_tlb spc,pte,prot,t1
1184 dtlb_check_alias_20w:
1185 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1193 space_adjust spc,va,t0
1195 space_check spc,t0,nadtlb_fault
1197 L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
1199 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20w
1200 update_accessed ptp,pte,t0,t1
1202 make_insert_tlb spc,pte,prot,t1
1210 nadtlb_check_alias_20w:
1211 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1223 space_check spc,t0,dtlb_fault
1225 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1227 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_11
1228 update_accessed ptp,pte,t0,t1
1230 make_insert_tlb_11 spc,pte,prot
1232 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1235 idtlba pte,(%sr1,va)
1236 idtlbp prot,(%sr1,va)
1238 mtsp t1, %sr1 /* Restore sr1 */
1244 dtlb_check_alias_11:
1245 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,11
1256 space_check spc,t0,nadtlb_fault
1258 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
1260 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_11
1261 update_accessed ptp,pte,t0,t1
1263 make_insert_tlb_11 spc,pte,prot
1265 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1268 idtlba pte,(%sr1,va)
1269 idtlbp prot,(%sr1,va)
1271 mtsp t1, %sr1 /* Restore sr1 */
1277 nadtlb_check_alias_11:
1278 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,11
1287 space_adjust spc,va,t0
1289 space_check spc,t0,dtlb_fault
1291 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1293 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20
1294 update_accessed ptp,pte,t0,t1
1296 make_insert_tlb spc,pte,prot,t1
1306 dtlb_check_alias_20:
1307 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1317 space_check spc,t0,nadtlb_fault
1319 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
1321 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20
1322 update_accessed ptp,pte,t0,t1
1324 make_insert_tlb spc,pte,prot,t1
1334 nadtlb_check_alias_20:
1335 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1347 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1348 * probei instructions. We don't want to fault for these
1349 * instructions (not only does it not make sense, it can cause
1350 * deadlocks, since some flushes are done with the mmap
1351 * semaphore held). If the translation doesn't exist, we can't
1352 * insert a translation, so have to emulate the side effects
1353 * of the instruction. Since we don't insert a translation
1354 * we can get a lot of faults during a flush loop, so it makes
1355 * sense to try to do it here with minimum overhead. We only
1356 * emulate fdc,fic,pdc,probew,prober instructions whose base
1357 * and index registers are not shadowed. We defer everything
1358 * else to the "slow" path.
1361 mfctl %cr19,%r9 /* Get iir */
1363 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1364 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1366 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1369 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1370 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1371 BL get_register,%r25
1372 extrw,u %r9,15,5,%r8 /* Get index register # */
1373 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1375 BL get_register,%r25
1376 extrw,u %r9,10,5,%r8 /* Get base register # */
1377 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1378 BL set_register,%r25
1379 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1384 or %r8,%r9,%r8 /* Set PSW_N */
1391 When there is no translation for the probe address then we
1392 must nullify the insn and return zero in the target register.
1393 This will indicate to the calling code that it does not have
1394 write/read privileges to this address.
1396 This should technically work for prober and probew in PA 1.1,
1397 and also probe,r and probe,w in PA 2.0
1399 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1400 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1406 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1407 BL get_register,%r25 /* Find the target register */
1408 extrw,u %r9,31,5,%r8 /* Get target register */
1409 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1410 BL set_register,%r25
1411 copy %r0,%r1 /* Write zero to target register */
1412 b nadtlb_nullify /* Nullify return insn */
1420 * I miss is a little different, since we allow users to fault
1421 * on the gateway page which is in the kernel address space.
1424 space_adjust spc,va,t0
1426 space_check spc,t0,itlb_fault
1428 L3_ptep ptp,pte,t0,va,itlb_fault
1430 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1431 update_accessed ptp,pte,t0,t1
1433 make_insert_tlb spc,pte,prot,t1
1444 * I miss is a little different, since we allow users to fault
1445 * on the gateway page which is in the kernel address space.
1448 space_adjust spc,va,t0
1450 space_check spc,t0,naitlb_fault
1452 L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
1454 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20w
1455 update_accessed ptp,pte,t0,t1
1457 make_insert_tlb spc,pte,prot,t1
1465 naitlb_check_alias_20w:
1466 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1478 space_check spc,t0,itlb_fault
1480 L2_ptep ptp,pte,t0,va,itlb_fault
1482 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1483 update_accessed ptp,pte,t0,t1
1485 make_insert_tlb_11 spc,pte,prot
1487 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1490 iitlba pte,(%sr1,va)
1491 iitlbp prot,(%sr1,va)
1493 mtsp t1, %sr1 /* Restore sr1 */
1502 space_check spc,t0,naitlb_fault
1504 L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
1506 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_11
1507 update_accessed ptp,pte,t0,t1
1509 make_insert_tlb_11 spc,pte,prot
1511 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1514 iitlba pte,(%sr1,va)
1515 iitlbp prot,(%sr1,va)
1517 mtsp t1, %sr1 /* Restore sr1 */
1523 naitlb_check_alias_11:
1524 do_alias spc,t0,t1,va,pte,prot,itlb_fault,11
1526 iitlba pte,(%sr0, va)
1527 iitlbp prot,(%sr0, va)
1536 space_check spc,t0,itlb_fault
1538 L2_ptep ptp,pte,t0,va,itlb_fault
1540 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1541 update_accessed ptp,pte,t0,t1
1543 make_insert_tlb spc,pte,prot,t1
1556 space_check spc,t0,naitlb_fault
1558 L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
1560 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20
1561 update_accessed ptp,pte,t0,t1
1563 make_insert_tlb spc,pte,prot,t1
1573 naitlb_check_alias_20:
1574 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1586 space_adjust spc,va,t0
1588 space_check spc,t0,dbit_fault
1590 L3_ptep ptp,pte,t0,va,dbit_fault
1592 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1593 update_dirty ptp,pte,t1
1595 make_insert_tlb spc,pte,prot,t1
1608 space_check spc,t0,dbit_fault
1610 L2_ptep ptp,pte,t0,va,dbit_fault
1612 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1613 update_dirty ptp,pte,t1
1615 make_insert_tlb_11 spc,pte,prot
1617 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1620 idtlba pte,(%sr1,va)
1621 idtlbp prot,(%sr1,va)
1623 mtsp t1, %sr1 /* Restore sr1 */
1632 space_check spc,t0,dbit_fault
1634 L2_ptep ptp,pte,t0,va,dbit_fault
1636 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1637 update_dirty ptp,pte,t1
1639 make_insert_tlb spc,pte,prot,t1
1650 .import handle_interruption,code
1654 ldi 31,%r8 /* Use an unused code */
1662 ldi PARISC_ITLB_TRAP,%r8
1676 /* Register saving semantics for system calls:
1678 %r1 clobbered by system call macro in userspace
1679 %r2 saved in PT_REGS by gateway page
1680 %r3 - %r18 preserved by C code (saved by signal code)
1681 %r19 - %r20 saved in PT_REGS by gateway page
1682 %r21 - %r22 non-standard syscall args
1683 stored in kernel stack by gateway page
1684 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1685 %r27 - %r30 saved in PT_REGS by gateway page
1686 %r31 syscall return pointer
1689 /* Floating point registers (FIXME: what do we do with these?)
1691 %fr0 - %fr3 status/exception, not preserved
1692 %fr4 - %fr7 arguments
1693 %fr8 - %fr11 not preserved by C code
1694 %fr12 - %fr21 preserved by C code
1695 %fr22 - %fr31 not preserved by C code
1698 .macro reg_save regs
1699 STREG %r3, PT_GR3(\regs)
1700 STREG %r4, PT_GR4(\regs)
1701 STREG %r5, PT_GR5(\regs)
1702 STREG %r6, PT_GR6(\regs)
1703 STREG %r7, PT_GR7(\regs)
1704 STREG %r8, PT_GR8(\regs)
1705 STREG %r9, PT_GR9(\regs)
1706 STREG %r10,PT_GR10(\regs)
1707 STREG %r11,PT_GR11(\regs)
1708 STREG %r12,PT_GR12(\regs)
1709 STREG %r13,PT_GR13(\regs)
1710 STREG %r14,PT_GR14(\regs)
1711 STREG %r15,PT_GR15(\regs)
1712 STREG %r16,PT_GR16(\regs)
1713 STREG %r17,PT_GR17(\regs)
1714 STREG %r18,PT_GR18(\regs)
1717 .macro reg_restore regs
1718 LDREG PT_GR3(\regs), %r3
1719 LDREG PT_GR4(\regs), %r4
1720 LDREG PT_GR5(\regs), %r5
1721 LDREG PT_GR6(\regs), %r6
1722 LDREG PT_GR7(\regs), %r7
1723 LDREG PT_GR8(\regs), %r8
1724 LDREG PT_GR9(\regs), %r9
1725 LDREG PT_GR10(\regs),%r10
1726 LDREG PT_GR11(\regs),%r11
1727 LDREG PT_GR12(\regs),%r12
1728 LDREG PT_GR13(\regs),%r13
1729 LDREG PT_GR14(\regs),%r14
1730 LDREG PT_GR15(\regs),%r15
1731 LDREG PT_GR16(\regs),%r16
1732 LDREG PT_GR17(\regs),%r17
1733 LDREG PT_GR18(\regs),%r18
1736 .macro fork_like name
1737 ENTRY_CFI(sys_\name\()_wrapper)
1738 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1739 ldo TASK_REGS(%r1),%r1
1742 ldil L%sys_\name, %r31
1743 be R%sys_\name(%sr4,%r31)
1744 STREG %r28, PT_CR27(%r1)
1745 ENDPROC_CFI(sys_\name\()_wrapper)
1752 /* Set the return value for the child */
1754 BL schedule_tail, %r2
1756 finish_child_return:
1757 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1758 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1760 LDREG PT_CR27(%r1), %r3
1767 ENTRY_CFI(sys_rt_sigreturn_wrapper)
1768 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1769 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1770 /* Don't save regs, we are going to restore them from sigcontext. */
1771 STREG %r2, -RP_OFFSET(%r30)
1773 ldo FRAME_SIZE(%r30), %r30
1774 BL sys_rt_sigreturn,%r2
1775 ldo -16(%r30),%r29 /* Reference param save area */
1777 BL sys_rt_sigreturn,%r2
1778 ldo FRAME_SIZE(%r30), %r30
1781 ldo -FRAME_SIZE(%r30), %r30
1782 LDREG -RP_OFFSET(%r30), %r2
1784 /* FIXME: I think we need to restore a few more things here. */
1785 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1786 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1789 /* If the signal was received while the process was blocked on a
1790 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1791 * take us to syscall_exit_rfi and on to intr_return.
1794 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1795 ENDPROC_CFI(sys_rt_sigreturn_wrapper)
1798 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
1799 * via syscall_exit_rfi if the signal was received while the process
1803 /* save return value now */
1806 LDREG TI_TASK(%r1),%r1
1807 STREG %r28,TASK_PT_GR28(%r1)
1809 /* Seems to me that dp could be wrong here, if the syscall involved
1810 * calling a module, and nothing got round to restoring dp on return.
1814 syscall_check_resched:
1816 /* check for reschedule */
1818 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
1819 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
1821 .import do_signal,code
1823 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1824 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r26
1825 and,COND(<>) %r19, %r26, %r0
1826 b,n syscall_restore /* skip past if we've nothing to do */
1829 /* Save callee-save registers (for sigcontext).
1830 * FIXME: After this point the process structure should be
1831 * consistent with all the relevant state of the process
1832 * before the syscall. We need to verify this.
1834 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1835 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
1839 ldo -16(%r30),%r29 /* Reference param save area */
1842 BL do_notify_resume,%r2
1843 ldi 1, %r25 /* long in_syscall = 1 */
1845 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1846 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
1849 b,n syscall_check_sig
1852 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1854 /* Are we being ptraced? */
1855 ldw TASK_FLAGS(%r1),%r19
1856 ldi _TIF_SYSCALL_TRACE_MASK,%r2
1857 and,COND(=) %r19,%r2,%r0
1858 b,n syscall_restore_rfi
1860 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
1863 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
1866 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
1867 LDREG TASK_PT_GR19(%r1),%r19
1868 LDREG TASK_PT_GR20(%r1),%r20
1869 LDREG TASK_PT_GR21(%r1),%r21
1870 LDREG TASK_PT_GR22(%r1),%r22
1871 LDREG TASK_PT_GR23(%r1),%r23
1872 LDREG TASK_PT_GR24(%r1),%r24
1873 LDREG TASK_PT_GR25(%r1),%r25
1874 LDREG TASK_PT_GR26(%r1),%r26
1875 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
1876 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
1877 LDREG TASK_PT_GR29(%r1),%r29
1878 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
1880 /* NOTE: We use rsm/ssm pair to make this operation atomic */
1881 LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
1883 copy %r1,%r30 /* Restore user sp */
1884 mfsp %sr3,%r1 /* Get user space id */
1885 mtsp %r1,%sr7 /* Restore sr7 */
1888 /* Set sr2 to zero for userspace syscalls to work. */
1890 mtsp %r1,%sr4 /* Restore sr4 */
1891 mtsp %r1,%sr5 /* Restore sr5 */
1892 mtsp %r1,%sr6 /* Restore sr6 */
1894 depi 3,31,2,%r31 /* ensure return to user mode. */
1897 /* decide whether to reset the wide mode bit
1899 * For a syscall, the W bit is stored in the lowest bit
1900 * of sp. Extract it and reset W if it is zero */
1901 extrd,u,*<> %r30,63,1,%r1
1903 /* now reset the lowest bit of sp if it was set */
1906 be,n 0(%sr3,%r31) /* return to user space */
1908 /* We have to return via an RFI, so that PSW T and R bits can be set
1910 * This sets up pt_regs so we can return via intr_restore, which is not
1911 * the most efficient way of doing things, but it works.
1913 syscall_restore_rfi:
1914 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
1915 mtctl %r2,%cr0 /* for immediate trap */
1916 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
1917 ldi 0x0b,%r20 /* Create new PSW */
1918 depi -1,13,1,%r20 /* C, Q, D, and I bits */
1920 /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
1921 * set in thread_info.h and converted to PA bitmap
1922 * numbers in asm-offsets.c */
1924 /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
1925 extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
1926 depi -1,27,1,%r20 /* R bit */
1928 /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
1929 extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
1930 depi -1,7,1,%r20 /* T bit */
1932 STREG %r20,TASK_PT_PSW(%r1)
1934 /* Always store space registers, since sr3 can be changed (e.g. fork) */
1937 STREG %r25,TASK_PT_SR3(%r1)
1938 STREG %r25,TASK_PT_SR4(%r1)
1939 STREG %r25,TASK_PT_SR5(%r1)
1940 STREG %r25,TASK_PT_SR6(%r1)
1941 STREG %r25,TASK_PT_SR7(%r1)
1942 STREG %r25,TASK_PT_IASQ0(%r1)
1943 STREG %r25,TASK_PT_IASQ1(%r1)
1946 /* Now if old D bit is clear, it means we didn't save all registers
1947 * on syscall entry, so do that now. This only happens on TRACEME
1948 * calls, or if someone attached to us while we were on a syscall.
1949 * We could make this more efficient by not saving r3-r18, but
1950 * then we wouldn't be able to use the common intr_restore path.
1951 * It is only for traced processes anyway, so performance is not
1954 bb,< %r2,30,pt_regs_ok /* Branch if D set */
1955 ldo TASK_REGS(%r1),%r25
1956 reg_save %r25 /* Save r3 to r18 */
1958 /* Save the current sr */
1960 STREG %r2,TASK_PT_SR0(%r1)
1962 /* Save the scratch sr */
1964 STREG %r2,TASK_PT_SR1(%r1)
1966 /* sr2 should be set to zero for userspace syscalls */
1967 STREG %r0,TASK_PT_SR2(%r1)
1969 LDREG TASK_PT_GR31(%r1),%r2
1970 depi 3,31,2,%r2 /* ensure return to user mode. */
1971 STREG %r2,TASK_PT_IAOQ0(%r1)
1973 STREG %r2,TASK_PT_IAOQ1(%r1)
1978 LDREG TASK_PT_IAOQ0(%r1),%r2
1979 depi 3,31,2,%r2 /* ensure return to user mode. */
1980 STREG %r2,TASK_PT_IAOQ0(%r1)
1981 LDREG TASK_PT_IAOQ1(%r1),%r2
1983 STREG %r2,TASK_PT_IAOQ1(%r1)
1988 load32 syscall_check_resched,%r2 /* if resched, we start over again */
1989 load32 schedule,%r19
1990 bv %r0(%r19) /* jumps to schedule() */
1992 ldo -16(%r30),%r29 /* Reference param save area */
1999 #ifdef CONFIG_FUNCTION_TRACER
2001 .import ftrace_function_trampoline,code
2002 .align L1_CACHE_BYTES
2003 ENTRY_CFI(mcount, caller)
2005 .export _mcount,data
2007 * The 64bit mcount() function pointer needs 4 dwords, of which the
2008 * first two are free. We optimize it here and put 2 instructions for
2009 * calling mcount(), and 2 instructions for ftrace_stub(). That way we
2010 * have all on one L1 cacheline.
2012 b ftrace_function_trampoline
2013 copy %r3, %arg2 /* caller original %sp */
2016 .type ftrace_stub, @function
2025 .dword 0 /* code in head.S puts value of global gp here */
2029 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2031 ENTRY_CFI(return_to_handler, caller,frame=FRAME_SIZE)
2032 .export parisc_return_to_handler,data
2033 parisc_return_to_handler:
2035 STREG %r0,-RP_OFFSET(%sp) /* store 0 as %rp */
2037 STREGM %r1,FRAME_SIZE(%sp)
2045 /* call ftrace_return_to_handler(0) */
2046 .import ftrace_return_to_handler,code
2047 load32 ftrace_return_to_handler,%ret0
2048 load32 .Lftrace_ret,%r2
2050 ldo -16(%sp),%ret1 /* Reference param save area */
2059 /* restore original return values */
2063 /* return from function */
2069 LDREGM -FRAME_SIZE(%sp),%r3
2070 ENDPROC_CFI(return_to_handler)
2072 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
2074 #endif /* CONFIG_FUNCTION_TRACER */
2076 #ifdef CONFIG_IRQSTACKS
2077 /* void call_on_stack(unsigned long param1, void *func,
2078 unsigned long new_stack) */
2079 ENTRY_CFI(call_on_stack, FRAME=2*FRAME_SIZE,CALLS,SAVE_RP,SAVE_SP)
2080 ENTRY(_call_on_stack)
2083 /* Regarding the HPPA calling conventions for function pointers,
2084 we assume the PIC register is not changed across call. For
2085 CONFIG_64BIT, the argument pointer is left to point at the
2086 argument region allocated for the call to call_on_stack. */
2088 /* Switch to new stack. We allocate two frames. */
2089 ldo 2*FRAME_SIZE(%arg2), %sp
2090 # ifdef CONFIG_64BIT
2091 /* Save previous stack pointer and return pointer in frame marker */
2092 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2093 /* Calls always use function descriptor */
2094 LDREG 16(%arg1), %arg1
2096 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2097 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2099 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2101 /* Save previous stack pointer and return pointer in frame marker */
2102 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2103 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2104 /* Calls use function descriptor if PLABEL bit is set */
2105 bb,>=,n %arg1, 30, 1f
2107 LDREG 0(%arg1), %arg1
2109 be,l 0(%sr4,%arg1), %sr0, %r31
2111 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2113 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2114 # endif /* CONFIG_64BIT */
2115 ENDPROC_CFI(call_on_stack)
2116 #endif /* CONFIG_IRQSTACKS */
2118 ENTRY_CFI(get_register)
2120 * get_register is used by the non access tlb miss handlers to
2121 * copy the value of the general register specified in r8 into
2122 * r1. This routine can't be used for shadowed registers, since
2123 * the rfir will restore the original value. So, for the shadowed
2124 * registers we put a -1 into r1 to indicate that the register
2125 * should not be used (the register being copied could also have
2126 * a -1 in it, but that is OK, it just means that we will have
2127 * to use the slow path instead).
2131 bv %r0(%r25) /* r0 */
2133 bv %r0(%r25) /* r1 - shadowed */
2135 bv %r0(%r25) /* r2 */
2137 bv %r0(%r25) /* r3 */
2139 bv %r0(%r25) /* r4 */
2141 bv %r0(%r25) /* r5 */
2143 bv %r0(%r25) /* r6 */
2145 bv %r0(%r25) /* r7 */
2147 bv %r0(%r25) /* r8 - shadowed */
2149 bv %r0(%r25) /* r9 - shadowed */
2151 bv %r0(%r25) /* r10 */
2153 bv %r0(%r25) /* r11 */
2155 bv %r0(%r25) /* r12 */
2157 bv %r0(%r25) /* r13 */
2159 bv %r0(%r25) /* r14 */
2161 bv %r0(%r25) /* r15 */
2163 bv %r0(%r25) /* r16 - shadowed */
2165 bv %r0(%r25) /* r17 - shadowed */
2167 bv %r0(%r25) /* r18 */
2169 bv %r0(%r25) /* r19 */
2171 bv %r0(%r25) /* r20 */
2173 bv %r0(%r25) /* r21 */
2175 bv %r0(%r25) /* r22 */
2177 bv %r0(%r25) /* r23 */
2179 bv %r0(%r25) /* r24 - shadowed */
2181 bv %r0(%r25) /* r25 - shadowed */
2183 bv %r0(%r25) /* r26 */
2185 bv %r0(%r25) /* r27 */
2187 bv %r0(%r25) /* r28 */
2189 bv %r0(%r25) /* r29 */
2191 bv %r0(%r25) /* r30 */
2193 bv %r0(%r25) /* r31 */
2195 ENDPROC_CFI(get_register)
2198 ENTRY_CFI(set_register)
2200 * set_register is used by the non access tlb miss handlers to
2201 * copy the value of r1 into the general register specified in
2206 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2208 bv %r0(%r25) /* r1 */
2210 bv %r0(%r25) /* r2 */
2212 bv %r0(%r25) /* r3 */
2214 bv %r0(%r25) /* r4 */
2216 bv %r0(%r25) /* r5 */
2218 bv %r0(%r25) /* r6 */
2220 bv %r0(%r25) /* r7 */
2222 bv %r0(%r25) /* r8 */
2224 bv %r0(%r25) /* r9 */
2226 bv %r0(%r25) /* r10 */
2228 bv %r0(%r25) /* r11 */
2230 bv %r0(%r25) /* r12 */
2232 bv %r0(%r25) /* r13 */
2234 bv %r0(%r25) /* r14 */
2236 bv %r0(%r25) /* r15 */
2238 bv %r0(%r25) /* r16 */
2240 bv %r0(%r25) /* r17 */
2242 bv %r0(%r25) /* r18 */
2244 bv %r0(%r25) /* r19 */
2246 bv %r0(%r25) /* r20 */
2248 bv %r0(%r25) /* r21 */
2250 bv %r0(%r25) /* r22 */
2252 bv %r0(%r25) /* r23 */
2254 bv %r0(%r25) /* r24 */
2256 bv %r0(%r25) /* r25 */
2258 bv %r0(%r25) /* r26 */
2260 bv %r0(%r25) /* r27 */
2262 bv %r0(%r25) /* r28 */
2264 bv %r0(%r25) /* r29 */
2266 bv %r0(%r25) /* r30 */
2268 bv %r0(%r25) /* r31 */
2270 ENDPROC_CFI(set_register)