arch/parisc/kernel/cache.c

   1 /* $Id: cache.c,v 1.4 2000/01/25 00:11:38 prumpf Exp $
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
   8  * Copyright (C) 1999 SuSE GmbH Nuernberg
   9  * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
  10  *
  11  * Cache and TLB management
  12  *
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/pagemap.h>
  21
  22 #include <asm/pdc.h>
  23 #include <asm/cache.h>
  24 #include <asm/cacheflush.h>
  25 #include <asm/tlbflush.h>
  26 #include <asm/system.h>
  27 #include <asm/page.h>
  28 #include <asm/pgalloc.h>
  29 #include <asm/processor.h>
  30 #include <asm/sections.h>
  31
  32 int split_tlb __read_mostly;
  33 int dcache_stride __read_mostly;
  34 int icache_stride __read_mostly;
  35 EXPORT_SYMBOL(dcache_stride);
  36
  37
  38 /* On some machines (e.g. ones with the Merced bus), there can be
  39  * only a single PxTLB broadcast at a time; this must be guaranteed
  40  * by software.  We put a spinlock around all TLB flushes  to
  41  * ensure this.
  42  */
  43 DEFINE_SPINLOCK(pa_tlb_lock);
  44
  45 struct pdc_cache_info cache_info __read_mostly;
  46 #ifndef CONFIG_PA20
  47 static struct pdc_btlb_info btlb_info __read_mostly;
  48 #endif
  49
  50 #ifdef CONFIG_SMP
  51 void
  52 flush_data_cache(void)
  53 {
  54         on_each_cpu(flush_data_cache_local, NULL, 1, 1);
  55 }
  56 void
  57 flush_instruction_cache(void)
  58 {
  59         on_each_cpu(flush_instruction_cache_local, NULL, 1, 1);
  60 }
  61 #endif
  62
  63 void
  64 flush_cache_all_local(void)
  65 {
  66         flush_instruction_cache_local(NULL);
  67         flush_data_cache_local(NULL);
  68 }
  69 EXPORT_SYMBOL(flush_cache_all_local);
  70
  71 /* flushes EVERYTHING (tlb & cache) */
  72
  73 void
  74 flush_all_caches(void)
  75 {
  76         flush_cache_all();
  77         flush_tlb_all();
  78 }
  79 EXPORT_SYMBOL(flush_all_caches);
  80
  81 void
  82 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
  83 {
  84         struct page *page = pte_page(pte);
  85
  86         if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
  87             test_bit(PG_dcache_dirty, &page->flags)) {
  88
  89                 flush_kernel_dcache_page(page);
  90                 clear_bit(PG_dcache_dirty, &page->flags);
  91         } else if (parisc_requires_coherency())
  92                 flush_kernel_dcache_page(page);
  93 }
  94
  95 void
  96 show_cache_info(struct seq_file *m)
  97 {
  98         char buf[32];
  99
 100         seq_printf(m, "I-cache\t\t: %ld KB\n",
 101                 cache_info.ic_size/1024 );
 102         if (cache_info.dc_loop == 1)
 103                 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
 104         seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
 105                 cache_info.dc_size/1024,
 106                 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
 107                 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
 108                 ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
 109         seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
 110                 cache_info.it_size,
 111                 cache_info.dt_size,
 112                 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
 113         );
 114
 115 #ifndef CONFIG_PA20
 116         /* BTLB - Block TLB */
 117         if (btlb_info.max_size==0) {
 118                 seq_printf(m, "BTLB\t\t: not supported\n" );
 119         } else {
 120                 seq_printf(m,
 121                 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
 122                 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
 123                 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
 124                 btlb_info.max_size, (int)4096,
 125                 btlb_info.max_size>>8,
 126                 btlb_info.fixed_range_info.num_i,
 127                 btlb_info.fixed_range_info.num_d,
 128                 btlb_info.fixed_range_info.num_comb,
 129                 btlb_info.variable_range_info.num_i,
 130                 btlb_info.variable_range_info.num_d,
 131                 btlb_info.variable_range_info.num_comb
 132                 );
 133         }
 134 #endif
 135 }
 136
 137 void __init
 138 parisc_cache_init(void)
 139 {
 140         if (pdc_cache_info(&cache_info) < 0)
 141                 panic("parisc_cache_init: pdc_cache_info failed");
 142
 143 #if 0
 144         printk("ic_size %lx dc_size %lx it_size %lx\n",
 145                 cache_info.ic_size,
 146                 cache_info.dc_size,
 147                 cache_info.it_size);
 148
 149         printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 150                 cache_info.dc_base,
 151                 cache_info.dc_stride,
 152                 cache_info.dc_count,
 153                 cache_info.dc_loop);
 154
 155         printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 156                 *(unsigned long *) (&cache_info.dc_conf),
 157                 cache_info.dc_conf.cc_alias,
 158                 cache_info.dc_conf.cc_block,
 159                 cache_info.dc_conf.cc_line,
 160                 cache_info.dc_conf.cc_shift);
 161         printk("        wt %d sh %d cst %d hv %d\n",
 162                 cache_info.dc_conf.cc_wt,
 163                 cache_info.dc_conf.cc_sh,
 164                 cache_info.dc_conf.cc_cst,
 165                 cache_info.dc_conf.cc_hv);
 166
 167         printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 168                 cache_info.ic_base,
 169                 cache_info.ic_stride,
 170                 cache_info.ic_count,
 171                 cache_info.ic_loop);
 172
 173         printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 174                 *(unsigned long *) (&cache_info.ic_conf),
 175                 cache_info.ic_conf.cc_alias,
 176                 cache_info.ic_conf.cc_block,
 177                 cache_info.ic_conf.cc_line,
 178                 cache_info.ic_conf.cc_shift);
 179         printk("        wt %d sh %d cst %d hv %d\n",
 180                 cache_info.ic_conf.cc_wt,
 181                 cache_info.ic_conf.cc_sh,
 182                 cache_info.ic_conf.cc_cst,
 183                 cache_info.ic_conf.cc_hv);
 184
 185         printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
 186                 cache_info.dt_conf.tc_sh,
 187                 cache_info.dt_conf.tc_page,
 188                 cache_info.dt_conf.tc_cst,
 189                 cache_info.dt_conf.tc_aid,
 190                 cache_info.dt_conf.tc_pad1);
 191
 192         printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
 193                 cache_info.it_conf.tc_sh,
 194                 cache_info.it_conf.tc_page,
 195                 cache_info.it_conf.tc_cst,
 196                 cache_info.it_conf.tc_aid,
 197                 cache_info.it_conf.tc_pad1);
 198 #endif
 199
 200         split_tlb = 0;
 201         if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
 202                 if (cache_info.dt_conf.tc_sh == 2)
 203                         printk(KERN_WARNING "Unexpected TLB configuration. "
 204                         "Will flush I/D separately (could be optimized).\n");
 205
 206                 split_tlb = 1;
 207         }
 208
 209         /* "New and Improved" version from Jim Hull
 210          *      (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
 211          * The following CAFL_STRIDE is an optimized version, see
 212          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
 213          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
 214          */
 215 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
 216         dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
 217         icache_stride = CAFL_STRIDE(cache_info.ic_conf);
 218 #undef CAFL_STRIDE
 219
 220 #ifndef CONFIG_PA20
 221         if (pdc_btlb_info(&btlb_info) < 0) {
 222                 memset(&btlb_info, 0, sizeof btlb_info);
 223         }
 224 #endif
 225
 226         if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
 227                                                 PDC_MODEL_NVA_UNSUPPORTED) {
 228                 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
 229 #if 0
 230                 panic("SMP kernel required to avoid non-equivalent aliasing");
 231 #endif
 232         }
 233 }
 234
 235 void disable_sr_hashing(void)
 236 {
 237         int srhash_type, retval;
 238         unsigned long space_bits;
 239
 240         switch (boot_cpu_data.cpu_type) {
 241         case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
 242                 BUG();
 243                 return;
 244
 245         case pcxs:
 246         case pcxt:
 247         case pcxt_:
 248                 srhash_type = SRHASH_PCXST;
 249                 break;
 250
 251         case pcxl:
 252                 srhash_type = SRHASH_PCXL;
 253                 break;
 254
 255         case pcxl2: /* pcxl2 doesn't support space register hashing */
 256                 return;
 257
 258         default: /* Currently all PA2.0 machines use the same ins. sequence */
 259                 srhash_type = SRHASH_PA20;
 260                 break;
 261         }
 262
 263         disable_sr_hashing_asm(srhash_type);
 264
 265         retval = pdc_spaceid_bits(&space_bits);
 266         /* If this procedure isn't implemented, don't panic. */
 267         if (retval < 0 && retval != PDC_BAD_OPTION)
 268                 panic("pdc_spaceid_bits call failed.\n");
 269         if (space_bits != 0)
 270                 panic("SpaceID hashing is still on!\n");
 271 }
 272
 273 void flush_dcache_page(struct page *page)
 274 {
 275         struct address_space *mapping = page_mapping(page);
 276         struct vm_area_struct *mpnt;
 277         struct prio_tree_iter iter;
 278         unsigned long offset;
 279         unsigned long addr;
 280         pgoff_t pgoff;
 281         unsigned long pfn = page_to_pfn(page);
 282
 283
 284         if (mapping && !mapping_mapped(mapping)) {
 285                 set_bit(PG_dcache_dirty, &page->flags);
 286                 return;
 287         }
 288
 289         flush_kernel_dcache_page(page);
 290
 291         if (!mapping)
 292                 return;
 293
 294         pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
 295
 296         /* We have carefully arranged in arch_get_unmapped_area() that
 297          * *any* mappings of a file are always congruently mapped (whether
 298          * declared as MAP_PRIVATE or MAP_SHARED), so we only need
 299          * to flush one address here for them all to become coherent */
 300
 301         flush_dcache_mmap_lock(mapping);
 302         vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
 303                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 304                 addr = mpnt->vm_start + offset;
 305
 306                 /* Flush instructions produce non access tlb misses.
 307                  * On PA, we nullify these instructions rather than
 308                  * taking a page fault if the pte doesn't exist.
 309                  * This is just for speed.  If the page translation
 310                  * isn't there, there's no point exciting the
 311                  * nadtlb handler into a nullification frenzy.
 312                  *
 313                  * Make sure we really have this page: the private
 314                  * mappings may cover this area but have COW'd this
 315                  * particular page.
 316                  */
 317                 if (translation_exists(mpnt, addr, pfn)) {
 318                         __flush_cache_page(mpnt, addr);
 319                         break;
 320                 }
 321         }
 322         flush_dcache_mmap_unlock(mapping);
 323 }
 324 EXPORT_SYMBOL(flush_dcache_page);
 325
 326 /* Defined in arch/parisc/kernel/pacache.S */
 327 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
 328 EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
 329 EXPORT_SYMBOL(flush_data_cache_local);
 330 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
 331
 332 void clear_user_page_asm(void *page, unsigned long vaddr)
 333 {
 334         /* This function is implemented in assembly in pacache.S */
 335         extern void __clear_user_page_asm(void *page, unsigned long vaddr);
 336
 337         purge_tlb_start();
 338         __clear_user_page_asm(page, vaddr);
 339         purge_tlb_end();
 340 }
 341
 342 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
 343 int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
 344
 345 void parisc_setup_cache_timing(void)
 346 {
 347         unsigned long rangetime, alltime;
 348         unsigned long size;
 349
 350         alltime = mfctl(16);
 351         flush_data_cache();
 352         alltime = mfctl(16) - alltime;
 353
 354         size = (unsigned long)(_end - _text);
 355         rangetime = mfctl(16);
 356         flush_kernel_dcache_range((unsigned long)_text, size);
 357         rangetime = mfctl(16) - rangetime;
 358
 359         printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
 360                 alltime, size, rangetime);
 361
 362         /* Racy, but if we see an intermediate value, it's ok too... */
 363         parisc_cache_flush_threshold = size * alltime / rangetime;
 364
 365         parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
 366         if (!parisc_cache_flush_threshold)
 367                 parisc_cache_flush_threshold = FLUSH_THRESHOLD;
 368
 369         printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
 370 }
 371
 372 extern void purge_kernel_dcache_page(unsigned long);
 373 extern void clear_user_page_asm(void *page, unsigned long vaddr);
 374
 375 void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
 376 {
 377         purge_kernel_dcache_page((unsigned long)page);
 378         purge_tlb_start();
 379         pdtlb_kernel(page);
 380         purge_tlb_end();
 381         clear_user_page_asm(page, vaddr);
 382 }
 383 EXPORT_SYMBOL(clear_user_page);
 384
 385 void flush_kernel_dcache_page_addr(void *addr)
 386 {
 387         flush_kernel_dcache_page_asm(addr);
 388         purge_tlb_start();
 389         pdtlb_kernel(addr);
 390         purge_tlb_end();
 391 }
 392 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
 393
 394 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
 395                     struct page *pg)
 396 {
 397         /* no coherency needed (all in kmap/kunmap) */
 398         copy_user_page_asm(vto, vfrom);
 399         if (!parisc_requires_coherency())
 400                 flush_kernel_dcache_page_asm(vto);
 401 }
 402 EXPORT_SYMBOL(copy_user_page);
 403
 404 #ifdef CONFIG_PA8X00
 405
 406 void kunmap_parisc(void *addr)
 407 {
 408         if (parisc_requires_coherency())
 409                 flush_kernel_dcache_page_addr(addr);
 410 }
 411 EXPORT_SYMBOL(kunmap_parisc);
 412 #endif