arch/mips/sibyte/common/sb_tbprof.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License
   4  * as published by the Free Software Foundation; either version 2
   5  * of the License, or (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  15  *
  16  * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
  17  * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
  18  * Copyright (C) 2007 MIPS Technologies, Inc.
  19  *    written by Ralf Baechle <ralf@linux-mips.org>
  20  */
  21
  22 #undef DEBUG
  23
  24 #include <linux/device.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/vmalloc.h>
  31 #include <linux/fs.h>
  32 #include <linux/errno.h>
  33 #include <linux/wait.h>
  34 #include <asm/io.h>
  35 #include <asm/sibyte/sb1250.h>
  36
  37 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  38 #include <asm/sibyte/bcm1480_regs.h>
  39 #include <asm/sibyte/bcm1480_scd.h>
  40 #include <asm/sibyte/bcm1480_int.h>
  41 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  42 #include <asm/sibyte/sb1250_regs.h>
  43 #include <asm/sibyte/sb1250_scd.h>
  44 #include <asm/sibyte/sb1250_int.h>
  45 #else
  46 #error invalid SiByte UART configuation
  47 #endif
  48
  49 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  50 #undef K_INT_TRACE_FREEZE
  51 #define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
  52 #undef K_INT_PERF_CNT
  53 #define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
  54 #endif
  55
  56 #include <asm/system.h>
  57 #include <asm/uaccess.h>
  58
  59 #define SBPROF_TB_MAJOR 240
  60
  61 typedef u64 tb_sample_t[6*256];
  62
  63 enum open_status {
  64         SB_CLOSED,
  65         SB_OPENING,
  66         SB_OPEN
  67 };
  68
  69 struct sbprof_tb {
  70         wait_queue_head_t       tb_sync;
  71         wait_queue_head_t       tb_read;
  72         struct mutex            lock;
  73         enum open_status        open;
  74         tb_sample_t             *sbprof_tbbuf;
  75         int                     next_tb_sample;
  76
  77         volatile int            tb_enable;
  78         volatile int            tb_armed;
  79
  80 };
  81
  82 static struct sbprof_tb sbp;
  83
  84 #define MAX_SAMPLE_BYTES (24*1024*1024)
  85 #define MAX_TBSAMPLE_BYTES (12*1024*1024)
  86
  87 #define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
  88 #define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
  89 #define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
  90
  91 /* ioctls */
  92 #define SBPROF_ZBSTART          _IOW('s', 0, int)
  93 #define SBPROF_ZBSTOP           _IOW('s', 1, int)
  94 #define SBPROF_ZBWAITFULL       _IOW('s', 2, int)
  95
  96 /*
  97  * Routines for using 40-bit SCD cycle counter
  98  *
  99  * Client responsible for either handling interrupts or making sure
 100  * the cycles counter never saturates, e.g., by doing
 101  * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
 102  */
 103
 104 /*
 105  * Configures SCD counter 0 to count ZCLKs starting from val;
 106  * Configures SCD counters1,2,3 to count nothing.
 107  * Must not be called while gathering ZBbus profiles.
 108  */
 109
 110 #define zclk_timer_init(val) \
 111   __asm__ __volatile__ (".set push;" \
 112                         ".set mips64;" \
 113                         "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
 114                         "sd   %0, 0x10($8);"   /* write val to counter0 */ \
 115                         "sd   %1, 0($8);"      /* config counter0 for zclks*/ \
 116                         ".set pop" \
 117                         : /* no outputs */ \
 118                                                      /* enable, counter0 */ \
 119                         : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
 120                         : /* modifies */ "$8" )
 121
 122
 123 /* Reads SCD counter 0 and puts result in value
 124    unsigned long long val; */
 125 #define zclk_get(val) \
 126   __asm__ __volatile__ (".set push;" \
 127                         ".set mips64;" \
 128                         "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
 129                         "ld   %0, 0x10($8);"   /* write val to counter0 */ \
 130                         ".set pop" \
 131                         : /* outputs */ "=r"(val) \
 132                         : /* inputs */ \
 133                         : /* modifies */ "$8" )
 134
 135 #define DEVNAME "sb_tbprof"
 136
 137 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
 138
 139 /*
 140  * Support for ZBbus sampling using the trace buffer
 141  *
 142  * We use the SCD performance counter interrupt, caused by a Zclk counter
 143  * overflow, to trigger the start of tracing.
 144  *
 145  * We set the trace buffer to sample everything and freeze on
 146  * overflow.
 147  *
 148  * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
 149  *
 150  */
 151
 152 static u64 tb_period;
 153
 154 static void arm_tb(void)
 155 {
 156         u64 scdperfcnt;
 157         u64 next = (1ULL << 40) - tb_period;
 158         u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
 159
 160         /*
 161          * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
 162          * trigger start of trace.  XXX vary sampling period
 163          */
 164         __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
 165         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 166
 167         /*
 168          * Unfortunately, in Pass 2 we must clear all counters to knock down
 169          * a previous interrupt request.  This means that bus profiling
 170          * requires ALL of the SCD perf counters.
 171          */
 172 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 173         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
 174                                                 /* keep counters 0,2,3,4,5,6,7 as is */
 175                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 176                      IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));
 177         __raw_writeq(
 178                      M_SPC_CFG_ENABLE |         /* enable counting */
 179                      M_SPC_CFG_CLEAR |          /* clear all counters */
 180                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 181                      IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));
 182 #else
 183         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
 184                                                 /* keep counters 0,2,3 as is */
 185                      M_SPC_CFG_ENABLE |         /* enable counting */
 186                      M_SPC_CFG_CLEAR |          /* clear all counters */
 187                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 188                      IOADDR(A_SCD_PERF_CNT_CFG));
 189 #endif
 190         __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
 191         /* Reset the trace buffer */
 192         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 193 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
 194         /* XXXKW may want to expose control to the data-collector */
 195         tb_options |= M_SCD_TRACE_CFG_FORCECNT;
 196 #endif
 197         __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
 198         sbp.tb_armed = 1;
 199 }
 200
 201 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
 202 {
 203         int i;
 204
 205         pr_debug(DEVNAME ": tb_intr\n");
 206
 207         if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
 208                 /* XXX should use XKPHYS to make writes bypass L2 */
 209                 u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
 210                 /* Read out trace */
 211                 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
 212                              IOADDR(A_SCD_TRACE_CFG));
 213                 __asm__ __volatile__ ("sync" : : : "memory");
 214                 /* Loop runs backwards because bundles are read out in reverse order */
 215                 for (i = 256 * 6; i > 0; i -= 6) {
 216                         /* Subscripts decrease to put bundle in the order */
 217                         /*   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
 218                         p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 219                         /* read t2 hi */
 220                         p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 221                         /* read t2 lo */
 222                         p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 223                         /* read t1 hi */
 224                         p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 225                         /* read t1 lo */
 226                         p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 227                         /* read t0 hi */
 228                         p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 229                         /* read t0 lo */
 230                 }
 231                 if (!sbp.tb_enable) {
 232                         pr_debug(DEVNAME ": tb_intr shutdown\n");
 233                         __raw_writeq(M_SCD_TRACE_CFG_RESET,
 234                                      IOADDR(A_SCD_TRACE_CFG));
 235                         sbp.tb_armed = 0;
 236                         wake_up_interruptible(&sbp.tb_sync);
 237                 } else {
 238                         /* knock down current interrupt and get another one later */
 239                         arm_tb();
 240                 }
 241         } else {
 242                 /* No more trace buffer samples */
 243                 pr_debug(DEVNAME ": tb_intr full\n");
 244                 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 245                 sbp.tb_armed = 0;
 246                 if (!sbp.tb_enable)
 247                         wake_up_interruptible(&sbp.tb_sync);
 248                 wake_up_interruptible(&sbp.tb_read);
 249         }
 250         return IRQ_HANDLED;
 251 }
 252
 253 static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
 254 {
 255         printk(DEVNAME ": unexpected pc_intr");
 256         return IRQ_NONE;
 257 }
 258
 259 /*
 260  * Requires: Already called zclk_timer_init with a value that won't
 261  *           saturate 40 bits.  No subsequent use of SCD performance counters
 262  *           or trace buffer.
 263  */
 264
 265 static int sbprof_zbprof_start(struct file *filp)
 266 {
 267         u64 scdperfcnt;
 268         int err;
 269
 270         if (xchg(&sbp.tb_enable, 1))
 271                 return -EBUSY;
 272
 273         pr_debug(DEVNAME ": starting\n");
 274
 275         sbp.next_tb_sample = 0;
 276         filp->f_pos = 0;
 277
 278         err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
 279                           DEVNAME " trace freeze", &sbp);
 280         if (err)
 281                 return -EBUSY;
 282
 283         /* Make sure there isn't a perf-cnt interrupt waiting */
 284         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 285         /* Disable and clear counters, override SRC_1 */
 286         __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
 287                      M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
 288                      IOADDR(A_SCD_PERF_CNT_CFG));
 289
 290         /*
 291          * We grab this interrupt to prevent others from trying to use
 292          * it, even though we don't want to service the interrupts
 293          * (they only feed into the trace-on-interrupt mechanism)
 294          */
 295         if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
 296                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 297                 return -EBUSY;
 298         }
 299
 300         /*
 301          * I need the core to mask these, but the interrupt mapper to
 302          *  pass them through.  I am exploiting my knowledge that
 303          *  cp0_status masks out IP[5]. krw
 304          */
 305 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 306         __raw_writeq(K_BCM1480_INT_MAP_I3,
 307                      IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
 308                             ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
 309 #else
 310         __raw_writeq(K_INT_MAP_I3,
 311                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 312                             (K_INT_PERF_CNT << 3)));
 313 #endif
 314
 315         /* Initialize address traps */
 316         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
 317         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
 318         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
 319         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
 320
 321         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
 322         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
 323         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
 324         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
 325
 326         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
 327         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
 328         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
 329         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 330
 331         /* Initialize Trace Event 0-7 */
 332         /*                              when interrupt  */
 333         __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
 334         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
 335         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
 336         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
 337         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
 338         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
 339         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
 340         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
 341
 342         /* Initialize Trace Sequence 0-7 */
 343         /*                                   Start on event 0 (interrupt) */
 344         __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
 345                      IOADDR(A_SCD_TRACE_SEQUENCE_0));
 346         /*                        dsamp when d used | asamp when a used */
 347         __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
 348                      K_SCD_TRSEQ_TRIGGER_ALL,
 349                      IOADDR(A_SCD_TRACE_SEQUENCE_1));
 350         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
 351         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
 352         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
 353         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
 354         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
 355         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
 356
 357         /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
 358 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 359         __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
 360                      IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
 361 #else
 362         __raw_writeq(1ULL << K_INT_PERF_CNT,
 363                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
 364 #endif
 365         arm_tb();
 366
 367         pr_debug(DEVNAME ": done starting\n");
 368
 369         return 0;
 370 }
 371
 372 static int sbprof_zbprof_stop(void)
 373 {
 374         int err = 0;
 375
 376         pr_debug(DEVNAME ": stopping\n");
 377
 378         if (sbp.tb_enable) {
 379                 /*
 380                  * XXXKW there is a window here where the intr handler may run,
 381                  * see the disable, and do the wake_up before this sleep
 382                  * happens.
 383                  */
 384                 pr_debug(DEVNAME ": wait for disarm\n");
 385                 err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed);
 386                 pr_debug(DEVNAME ": disarm complete, stat %d\n", err);
 387
 388                 if (err)
 389                         return err;
 390
 391                 sbp.tb_enable = 0;
 392                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 393                 free_irq(K_INT_PERF_CNT, &sbp);
 394         }
 395
 396         pr_debug(DEVNAME ": done stopping\n");
 397
 398         return err;
 399 }
 400
 401 static int sbprof_tb_open(struct inode *inode, struct file *filp)
 402 {
 403         int minor;
 404
 405         minor = iminor(inode);
 406         if (minor != 0)
 407                 return -ENODEV;
 408
 409         if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED)
 410                 return -EBUSY;
 411
 412         memset(&sbp, 0, sizeof(struct sbprof_tb));
 413         sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
 414         if (!sbp.sbprof_tbbuf) {
 415                 sbp.open = SB_CLOSED;
 416                 wmb();
 417                 return -ENOMEM;
 418         }
 419
 420         memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
 421         init_waitqueue_head(&sbp.tb_sync);
 422         init_waitqueue_head(&sbp.tb_read);
 423         mutex_init(&sbp.lock);
 424
 425         sbp.open = SB_OPEN;
 426         wmb();
 427
 428         return 0;
 429 }
 430
 431 static int sbprof_tb_release(struct inode *inode, struct file *filp)
 432 {
 433         int minor;
 434
 435         minor = iminor(inode);
 436         if (minor != 0 || sbp.open != SB_CLOSED)
 437                 return -ENODEV;
 438
 439         mutex_lock(&sbp.lock);
 440
 441         if (sbp.tb_armed || sbp.tb_enable)
 442                 sbprof_zbprof_stop();
 443
 444         vfree(sbp.sbprof_tbbuf);
 445         sbp.open = SB_CLOSED;
 446         wmb();
 447
 448         mutex_unlock(&sbp.lock);
 449
 450         return 0;
 451 }
 452
 453 static ssize_t sbprof_tb_read(struct file *filp, char *buf,
 454                               size_t size, loff_t *offp)
 455 {
 456         int cur_sample, sample_off, cur_count, sample_left;
 457         char *src;
 458         int   count   =  0;
 459         char *dest    =  buf;
 460         long  cur_off = *offp;
 461
 462         if (!access_ok(VERIFY_WRITE, buf, size))
 463                 return -EFAULT;
 464
 465         mutex_lock(&sbp.lock);
 466
 467         count = 0;
 468         cur_sample = cur_off / TB_SAMPLE_SIZE;
 469         sample_off = cur_off % TB_SAMPLE_SIZE;
 470         sample_left = TB_SAMPLE_SIZE - sample_off;
 471
 472         while (size && (cur_sample < sbp.next_tb_sample)) {
 473                 int err;
 474
 475                 cur_count = size < sample_left ? size : sample_left;
 476                 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
 477                 err = __copy_to_user(dest, src, cur_count);
 478                 if (err) {
 479                         *offp = cur_off + cur_count - err;
 480                         mutex_unlock(&sbp.lock);
 481                         return err;
 482                 }
 483                 pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
 484                          cur_sample, cur_count);
 485                 size -= cur_count;
 486                 sample_left -= cur_count;
 487                 if (!sample_left) {
 488                         cur_sample++;
 489                         sample_off = 0;
 490                         sample_left = TB_SAMPLE_SIZE;
 491                 } else {
 492                         sample_off += cur_count;
 493                 }
 494                 cur_off += cur_count;
 495                 dest += cur_count;
 496                 count += cur_count;
 497         }
 498         *offp = cur_off;
 499         mutex_unlock(&sbp.lock);
 500
 501         return count;
 502 }
 503
 504 static long sbprof_tb_ioctl(struct file *filp,
 505                             unsigned int command,
 506                             unsigned long arg)
 507 {
 508         int err = 0;
 509
 510         switch (command) {
 511         case SBPROF_ZBSTART:
 512                 mutex_lock(&sbp.lock);
 513                 err = sbprof_zbprof_start(filp);
 514                 mutex_unlock(&sbp.lock);
 515                 break;
 516
 517         case SBPROF_ZBSTOP:
 518                 mutex_lock(&sbp.lock);
 519                 err = sbprof_zbprof_stop();
 520                 mutex_unlock(&sbp.lock);
 521                 break;
 522
 523         case SBPROF_ZBWAITFULL: {
 524                 err = wait_event_interruptible(sbp.tb_read, TB_FULL);
 525                 if (err)
 526                         break;
 527
 528                 err = put_user(TB_FULL, (int *) arg);
 529                 break;
 530         }
 531
 532         default:
 533                 err = -EINVAL;
 534                 break;
 535         }
 536
 537         return err;
 538 }
 539
 540 static const struct file_operations sbprof_tb_fops = {
 541         .owner          = THIS_MODULE,
 542         .open           = sbprof_tb_open,
 543         .release        = sbprof_tb_release,
 544         .read           = sbprof_tb_read,
 545         .unlocked_ioctl = sbprof_tb_ioctl,
 546         .compat_ioctl   = sbprof_tb_ioctl,
 547         .mmap           = NULL,
 548 };
 549
 550 static struct class *tb_class;
 551 static struct device *tb_dev;
 552
 553 static int __init sbprof_tb_init(void)
 554 {
 555         struct device *dev;
 556         struct class *tbc;
 557         int err;
 558
 559         if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
 560                 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
 561                        SBPROF_TB_MAJOR);
 562                 return -EIO;
 563         }
 564
 565         tbc = class_create(THIS_MODULE, "sb_tracebuffer");
 566         if (IS_ERR(tbc)) {
 567                 err = PTR_ERR(tbc);
 568                 goto out_chrdev;
 569         }
 570
 571         tb_class = tbc;
 572
 573         dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), NULL, "tb");
 574         if (IS_ERR(dev)) {
 575                 err = PTR_ERR(dev);
 576                 goto out_class;
 577         }
 578         tb_dev = dev;
 579
 580         sbp.open = SB_CLOSED;
 581         wmb();
 582         tb_period = zbbus_mhz * 10000LL;
 583         pr_info(DEVNAME ": initialized - tb_period = %lld\n",
 584                 (long long) tb_period);
 585         return 0;
 586
 587 out_class:
 588         class_destroy(tb_class);
 589 out_chrdev:
 590         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 591
 592         return err;
 593 }
 594
 595 static void __exit sbprof_tb_cleanup(void)
 596 {
 597         device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0));
 598         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 599         class_destroy(tb_class);
 600 }
 601
 602 module_init(sbprof_tb_init);
 603 module_exit(sbprof_tb_cleanup);
 604
 605 MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
 606 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
 607 MODULE_LICENSE("GPL");