2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/linkage.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
24 #include <linux/slab.h>
25 #include <linux/kernel_stat.h>
27 #include <asm/errno.h>
28 #include <asm/irq_regs.h>
29 #include <asm/signal.h>
30 #include <asm/system.h>
33 #include <asm/sibyte/bcm1480_regs.h>
34 #include <asm/sibyte/bcm1480_int.h>
35 #include <asm/sibyte/bcm1480_scd.h>
37 #include <asm/sibyte/sb1250_uart.h>
38 #include <asm/sibyte/sb1250.h>
41 * These are the routines that handle all the low level interrupt stuff.
42 * Actions handled here are: initialization of the interrupt map, requesting of
43 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
48 static void end_bcm1480_irq(unsigned int irq);
49 static void enable_bcm1480_irq(unsigned int irq);
50 static void disable_bcm1480_irq(unsigned int irq);
51 static void ack_bcm1480_irq(unsigned int irq);
53 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask);
57 extern unsigned long ht_eoi_space;
60 static struct irq_chip bcm1480_irq_type = {
61 .name = "BCM1480-IMR",
62 .ack = ack_bcm1480_irq,
63 .mask = disable_bcm1480_irq,
64 .mask_ack = ack_bcm1480_irq,
65 .unmask = enable_bcm1480_irq,
66 .end = end_bcm1480_irq,
68 .set_affinity = bcm1480_set_affinity
72 /* Store the CPU id (not the logical number) */
73 int bcm1480_irq_owner[BCM1480_NR_IRQS];
75 DEFINE_SPINLOCK(bcm1480_imr_lock);
77 void bcm1480_mask_irq(int cpu, int irq)
79 unsigned long flags, hl_spacing;
82 spin_lock_irqsave(&bcm1480_imr_lock, flags);
84 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
85 hl_spacing = BCM1480_IMR_HL_SPACING;
86 irq -= BCM1480_NR_IRQS_HALF;
88 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
89 cur_ints |= (((u64) 1) << irq);
90 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
91 spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
94 void bcm1480_unmask_irq(int cpu, int irq)
96 unsigned long flags, hl_spacing;
99 spin_lock_irqsave(&bcm1480_imr_lock, flags);
101 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
102 hl_spacing = BCM1480_IMR_HL_SPACING;
103 irq -= BCM1480_NR_IRQS_HALF;
105 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
106 cur_ints &= ~(((u64) 1) << irq);
107 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
108 spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
112 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
114 int i = 0, old_cpu, cpu, int_on, k;
117 unsigned int irq_dirty;
119 if (cpumask_weight(mask) != 1) {
120 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
123 i = cpumask_first(mask);
125 /* Convert logical CPU to physical CPU */
126 cpu = cpu_logical_map(i);
128 /* Protect against other affinity changers and IMR manipulation */
129 spin_lock_irqsave(&bcm1480_imr_lock, flags);
131 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
132 old_cpu = bcm1480_irq_owner[irq];
134 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
135 irq_dirty -= BCM1480_NR_IRQS_HALF;
138 for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
139 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
140 int_on = !(cur_ints & (((u64) 1) << irq_dirty));
142 /* If it was on, mask it */
143 cur_ints |= (((u64) 1) << irq_dirty);
144 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
146 bcm1480_irq_owner[irq] = cpu;
148 /* unmask for the new CPU */
149 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
150 cur_ints &= ~(((u64) 1) << irq_dirty);
151 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
154 spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
161 /*****************************************************************************/
163 static void disable_bcm1480_irq(unsigned int irq)
165 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
168 static void enable_bcm1480_irq(unsigned int irq)
170 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
174 static void ack_bcm1480_irq(unsigned int irq)
177 unsigned int irq_dirty;
181 * If the interrupt was an HT interrupt, now is the time to
182 * clear it. NOTE: we assume the HT bridge was set up to
183 * deliver the interrupts to all CPUs (which makes affinity
184 * changing easier for us)
187 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
188 irq_dirty -= BCM1480_NR_IRQS_HALF;
190 for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
191 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
192 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
193 pending &= ((u64)1 << (irq_dirty));
197 for (i=0; i<NR_CPUS; i++) {
199 * Clear for all CPUs so an affinity switch
200 * doesn't find an old status
202 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
203 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
206 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
210 * Generate EOI. For Pass 1 parts, EOI is a nop. For
211 * Pass 2, the LDT world may be edge-triggered, but
212 * this EOI shouldn't hurt. If they are
213 * level-sensitive, the EOI is required.
217 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
221 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
225 static void end_bcm1480_irq(unsigned int irq)
227 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
228 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
233 void __init init_bcm1480_irqs(void)
237 for (i = 0; i < BCM1480_NR_IRQS; i++) {
238 set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
239 bcm1480_irq_owner[i] = 0;
244 * init_IRQ is called early in the boot sequence from init/main.c. It
245 * is responsible for setting up the interrupt mapper and installing the
246 * handler that will be responsible for dispatching interrupts to the
250 * For now, map all interrupts to IP[2]. We could save
251 * some cycles by parceling out system interrupts to different
252 * IP lines, but keep it simple for bringup. We'll also direct
253 * all interrupts to a single CPU; we should probably route
254 * PCI and LDT to one cpu and everything else to the other
255 * to balance the load a bit.
257 * On the second cpu, everything is set to IP5, which is
258 * ignored, EXCEPT the mailbox interrupt. That one is
259 * set to IP[2] so it is handled. This is needed so we
260 * can do cross-cpu function calls, as requred by SMP
263 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
264 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
265 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
266 #define IMR_IP5_VAL K_BCM1480_INT_MAP_I3
267 #define IMR_IP6_VAL K_BCM1480_INT_MAP_I4
269 void __init arch_init_irq(void)
273 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
274 STATUSF_IP1 | STATUSF_IP0;
276 /* Default everything to IP2 */
277 /* Start with _high registers which has no bit 0 interrupt source */
278 for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
279 for (cpu = 0; cpu < 4; cpu++) {
280 __raw_writeq(IMR_IP2_VAL,
281 IOADDR(A_BCM1480_IMR_REGISTER(cpu,
282 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
286 /* Now do _low registers */
287 for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
288 for (cpu = 0; cpu < 4; cpu++) {
289 __raw_writeq(IMR_IP2_VAL,
290 IOADDR(A_BCM1480_IMR_REGISTER(cpu,
291 R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
298 * Map the high 16 bits of mailbox_0 registers to IP[3], for
302 for (cpu = 0; cpu < 4; cpu++) {
303 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
304 (K_BCM1480_INT_MBOX_0_0 << 3)));
308 /* Clear the mailboxes. The firmware may leave them dirty */
309 for (cpu = 0; cpu < 4; cpu++) {
310 __raw_writeq(0xffffffffffffffffULL,
311 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
312 __raw_writeq(0xffffffffffffffffULL,
313 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
317 /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
318 tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
319 for (cpu = 0; cpu < 4; cpu++) {
320 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
323 for (cpu = 0; cpu < 4; cpu++) {
324 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
328 * Note that the timer interrupts are also mapped, but this is
329 * done in bcm1480_time_init(). Also, the profiling driver
330 * does its own management of IP7.
333 /* Enable necessary IPs, disable the rest */
334 change_c0_status(ST0_IM, imask);
337 extern void bcm1480_mailbox_interrupt(void);
339 static inline void dispatch_ip2(void)
341 unsigned long long mask_h, mask_l;
342 unsigned int cpu = smp_processor_id();
346 * Default...we've hit an IP[2] interrupt, which means we've got to
347 * check the 1480 interrupt registers to figure out what to do. Need
348 * to detect which CPU we're on, now that smp_affinity is supported.
350 base = A_BCM1480_IMR_MAPPER(cpu);
351 mask_h = __raw_readq(
352 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
353 mask_l = __raw_readq(
354 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
358 do_IRQ(fls64(mask_h) - 1);
360 do_IRQ(63 + fls64(mask_l));
364 asmlinkage void plat_irq_dispatch(void)
366 unsigned int cpu = smp_processor_id();
367 unsigned int pending;
369 #ifdef CONFIG_SIBYTE_BCM1480_PROF
370 /* Set compare to count to silence count/compare timer interrupts */
371 write_c0_compare(read_c0_count());
374 pending = read_c0_cause() & read_c0_status();
376 #ifdef CONFIG_SIBYTE_BCM1480_PROF
377 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
382 if (pending & CAUSEF_IP4)
383 do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
385 else if (pending & CAUSEF_IP3)
386 bcm1480_mailbox_interrupt();
389 else if (pending & CAUSEF_IP2)