1 // SPDX-License-Identifier: GPL-2.0
3 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
5 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
6 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
7 * Copyright (C) 1999 - 2001 Kanoj Sarcar
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/ioport.h>
13 #include <linux/kernel.h>
14 #include <linux/bitops.h>
17 #include <asm/irq_cpu.h>
18 #include <asm/pci/bridge.h>
19 #include <asm/sn/addrs.h>
20 #include <asm/sn/agent.h>
21 #include <asm/sn/arch.h>
22 #include <asm/sn/hub.h>
23 #include <asm/sn/intr.h>
26 struct bridge_controller *bc;
33 static DECLARE_BITMAP(hub_irq_map, IP27_HUB_IRQ_COUNT);
35 static DEFINE_PER_CPU(unsigned long [2], irq_enable_mask);
37 static inline int alloc_level(void)
42 level = find_first_zero_bit(hub_irq_map, IP27_HUB_IRQ_COUNT);
43 if (level >= IP27_HUB_IRQ_COUNT)
46 if (test_and_set_bit(level, hub_irq_map))
52 static void enable_hub_irq(struct irq_data *d)
54 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
55 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
57 set_bit(hd->bit, mask);
58 __raw_writeq(mask[0], hd->irq_mask[0]);
59 __raw_writeq(mask[1], hd->irq_mask[1]);
62 static void disable_hub_irq(struct irq_data *d)
64 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
65 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
67 clear_bit(hd->bit, mask);
68 __raw_writeq(mask[0], hd->irq_mask[0]);
69 __raw_writeq(mask[1], hd->irq_mask[1]);
72 static unsigned int startup_bridge_irq(struct irq_data *d)
74 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
75 struct bridge_controller *bc;
86 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(hd->cpu));
87 bridge_write(bc, b_int_addr[pin].addr,
88 (0x20000 | hd->bit | (nasid << 8)));
89 bridge_set(bc, b_int_enable, (1 << pin));
90 bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
93 * Enable sending of an interrupt clear packt to the hub on a high to
94 * low transition of the interrupt pin.
96 * IRIX sets additional bits in the address which are documented as
97 * reserved in the bridge docs.
99 bridge_set(bc, b_int_mode, (1UL << pin));
102 * We assume the bridge to have a 1:1 mapping between devices
103 * (slots) and intr pins.
105 device = bridge_read(bc, b_int_device);
106 device &= ~(7 << (pin*3));
107 device |= (pin << (pin*3));
108 bridge_write(bc, b_int_device, device);
110 bridge_read(bc, b_wid_tflush);
114 return 0; /* Never anything pending. */
117 static void shutdown_bridge_irq(struct irq_data *d)
119 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
120 struct bridge_controller *bc;
128 bridge_clr(bc, b_int_enable, (1 << hd->pin));
129 bridge_read(bc, b_wid_tflush);
132 static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask)
137 cpu = cpumask_first_and(mask, cpu_online_mask);
138 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
140 if (!cputoslice(cpu)) {
141 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_A);
142 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_A);
144 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B);
145 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B);
148 /* Make sure it's not already pending when we connect it. */
149 REMOTE_HUB_CLR_INTR(nasid, hd->bit);
152 static int set_affinity_hub_irq(struct irq_data *d, const struct cpumask *mask,
155 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
160 if (irqd_is_started(d))
163 setup_hub_mask(hd, mask);
165 if (irqd_is_started(d))
166 startup_bridge_irq(d);
168 irq_data_update_effective_affinity(d, cpumask_of(hd->cpu));
173 static struct irq_chip hub_irq_type = {
175 .irq_startup = startup_bridge_irq,
176 .irq_shutdown = shutdown_bridge_irq,
177 .irq_mask = disable_hub_irq,
178 .irq_unmask = enable_hub_irq,
179 .irq_set_affinity = set_affinity_hub_irq,
182 int request_bridge_irq(struct bridge_controller *bc, int pin)
184 struct hub_irq_data *hd;
185 struct hub_data *hub;
186 struct irq_desc *desc;
190 hd = kzalloc(sizeof(*hd), GFP_KERNEL);
194 swlevel = alloc_level();
195 if (unlikely(swlevel < 0)) {
199 irq = swlevel + IP27_HUB_IRQ_BASE;
204 irq_set_chip_data(irq, hd);
206 /* use CPU connected to nearest hub */
207 hub = hub_data(NASID_TO_COMPACT_NODEID(bc->nasid));
208 setup_hub_mask(hd, &hub->h_cpus);
210 desc = irq_to_desc(irq);
211 desc->irq_common_data.node = bc->nasid;
212 cpumask_copy(desc->irq_common_data.affinity, &hub->h_cpus);
217 void ip27_hub_irq_init(void)
221 for (i = IP27_HUB_IRQ_BASE;
222 i < (IP27_HUB_IRQ_BASE + IP27_HUB_IRQ_COUNT); i++)
223 irq_set_chip_and_handler(i, &hub_irq_type, handle_level_irq);
226 * Some interrupts are reserved by hardware or by software convention.
227 * Mark these as reserved right away so they won't be used accidentally
230 for (i = 0; i <= BASE_PCI_IRQ; i++)
231 set_bit(i, hub_irq_map);
233 set_bit(IP_PEND0_6_63, hub_irq_map);
235 for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++)
236 set_bit(i, hub_irq_map);
240 * This code is unnecessarily complex, because we do
241 * intr enabling. Basically, once we grab the set of intrs we need
242 * to service, we must mask _all_ these interrupts; firstly, to make
243 * sure the same intr does not intr again, causing recursion that
244 * can lead to stack overflow. Secondly, we can not just mask the
245 * one intr we are do_IRQing, because the non-masked intrs in the
246 * first set might intr again, causing multiple servicings of the
247 * same intr. This effect is mostly seen for intercpu intrs.
251 static void ip27_do_irq_mask0(struct irq_desc *desc)
253 cpuid_t cpu = smp_processor_id();
254 unsigned long *mask = per_cpu(irq_enable_mask, cpu);
257 /* copied from Irix intpend0() */
258 pend0 = LOCAL_HUB_L(PI_INT_PEND0);
260 pend0 &= mask[0]; /* Pick intrs we should look at */
265 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
266 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
268 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
269 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
271 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
272 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
273 generic_smp_call_function_interrupt();
274 } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
275 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
276 generic_smp_call_function_interrupt();
279 generic_handle_irq(__ffs(pend0) + IP27_HUB_IRQ_BASE);
281 LOCAL_HUB_L(PI_INT_PEND0);
284 static void ip27_do_irq_mask1(struct irq_desc *desc)
286 cpuid_t cpu = smp_processor_id();
287 unsigned long *mask = per_cpu(irq_enable_mask, cpu);
290 /* copied from Irix intpend0() */
291 pend1 = LOCAL_HUB_L(PI_INT_PEND1);
293 pend1 &= mask[1]; /* Pick intrs we should look at */
297 generic_handle_irq(__ffs(pend1) + IP27_HUB_IRQ_BASE + 64);
299 LOCAL_HUB_L(PI_INT_PEND1);
302 void install_ipi(void)
304 int cpu = smp_processor_id();
305 unsigned long *mask = per_cpu(irq_enable_mask, cpu);
306 int slice = LOCAL_HUB_L(PI_CPU_NUM);
309 resched = CPU_RESCHED_A_IRQ + slice;
310 set_bit(resched, mask);
311 LOCAL_HUB_CLR_INTR(resched);
313 call = CPU_CALL_A_IRQ + slice;
315 LOCAL_HUB_CLR_INTR(call);
318 LOCAL_HUB_S(PI_INT_MASK0_A, mask[0]);
319 LOCAL_HUB_S(PI_INT_MASK1_A, mask[1]);
321 LOCAL_HUB_S(PI_INT_MASK0_B, mask[0]);
322 LOCAL_HUB_S(PI_INT_MASK1_B, mask[1]);
326 void __init arch_init_irq(void)
331 irq_set_percpu_devid(IP27_HUB_PEND0_IRQ);
332 irq_set_chained_handler(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0);
333 irq_set_percpu_devid(IP27_HUB_PEND1_IRQ);
334 irq_set_chained_handler(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1);