arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/percpu-defs.h>
  39 #include <linux/perf_event.h>
  40
  41 #include <asm/branch.h>
  42 #include <asm/inst.h>
  43 #include <asm/ptrace.h>
  44 #include <asm/signal.h>
  45 #include <linux/uaccess.h>
  46
  47 #include <asm/cpu-info.h>
  48 #include <asm/processor.h>
  49 #include <asm/fpu_emulator.h>
  50 #include <asm/fpu.h>
  51 #include <asm/mips-r2-to-r6-emul.h>
  52
  53 #include "ieee754.h"
  54
  55 /* Function which emulates a floating point instruction. */
  56
  57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  58         mips_instruction);
  59
  60 static int fpux_emu(struct pt_regs *,
  61         struct mips_fpu_struct *, mips_instruction, void *__user *);
  62
  63 /* Control registers */
  64
  65 #define FPCREG_RID      0       /* $0  = revision id */
  66 #define FPCREG_FCCR     25      /* $25 = fccr */
  67 #define FPCREG_FEXR     26      /* $26 = fexr */
  68 #define FPCREG_FENR     28      /* $28 = fenr */
  69 #define FPCREG_CSR      31      /* $31 = csr */
  70
  71 /* convert condition code register number to csr bit */
  72 const unsigned int fpucondbit[8] = {
  73         FPU_CSR_COND,
  74         FPU_CSR_COND1,
  75         FPU_CSR_COND2,
  76         FPU_CSR_COND3,
  77         FPU_CSR_COND4,
  78         FPU_CSR_COND5,
  79         FPU_CSR_COND6,
  80         FPU_CSR_COND7
  81 };
  82
  83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  84 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  85 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  86 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  87 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  88
  89 /*
  90  * This functions translates a 32-bit microMIPS instruction
  91  * into a 32-bit MIPS32 instruction. Returns 0 on success
  92  * and SIGILL otherwise.
  93  */
  94 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  95 {
  96         union mips_instruction insn = *insn_ptr;
  97         union mips_instruction mips32_insn = insn;
  98         int func, fmt, op;
  99
 100         switch (insn.mm_i_format.opcode) {
 101         case mm_ldc132_op:
 102                 mips32_insn.mm_i_format.opcode = ldc1_op;
 103                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 104                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 105                 break;
 106         case mm_lwc132_op:
 107                 mips32_insn.mm_i_format.opcode = lwc1_op;
 108                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 109                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 110                 break;
 111         case mm_sdc132_op:
 112                 mips32_insn.mm_i_format.opcode = sdc1_op;
 113                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 114                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 115                 break;
 116         case mm_swc132_op:
 117                 mips32_insn.mm_i_format.opcode = swc1_op;
 118                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 119                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 120                 break;
 121         case mm_pool32i_op:
 122                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 123                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 124                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 125                         mips32_insn.fb_format.opcode = cop1_op;
 126                         mips32_insn.fb_format.bc = bc_op;
 127                         mips32_insn.fb_format.flag =
 128                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 129                 } else
 130                         return SIGILL;
 131                 break;
 132         case mm_pool32f_op:
 133                 switch (insn.mm_fp0_format.func) {
 134                 case mm_32f_01_op:
 135                 case mm_32f_11_op:
 136                 case mm_32f_02_op:
 137                 case mm_32f_12_op:
 138                 case mm_32f_41_op:
 139                 case mm_32f_51_op:
 140                 case mm_32f_42_op:
 141                 case mm_32f_52_op:
 142                         op = insn.mm_fp0_format.func;
 143                         if (op == mm_32f_01_op)
 144                                 func = madd_s_op;
 145                         else if (op == mm_32f_11_op)
 146                                 func = madd_d_op;
 147                         else if (op == mm_32f_02_op)
 148                                 func = nmadd_s_op;
 149                         else if (op == mm_32f_12_op)
 150                                 func = nmadd_d_op;
 151                         else if (op == mm_32f_41_op)
 152                                 func = msub_s_op;
 153                         else if (op == mm_32f_51_op)
 154                                 func = msub_d_op;
 155                         else if (op == mm_32f_42_op)
 156                                 func = nmsub_s_op;
 157                         else
 158                                 func = nmsub_d_op;
 159                         mips32_insn.fp6_format.opcode = cop1x_op;
 160                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 161                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 162                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 163                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 164                         mips32_insn.fp6_format.func = func;
 165                         break;
 166                 case mm_32f_10_op:
 167                         func = -1;      /* Invalid */
 168                         op = insn.mm_fp5_format.op & 0x7;
 169                         if (op == mm_ldxc1_op)
 170                                 func = ldxc1_op;
 171                         else if (op == mm_sdxc1_op)
 172                                 func = sdxc1_op;
 173                         else if (op == mm_lwxc1_op)
 174                                 func = lwxc1_op;
 175                         else if (op == mm_swxc1_op)
 176                                 func = swxc1_op;
 177
 178                         if (func != -1) {
 179                                 mips32_insn.r_format.opcode = cop1x_op;
 180                                 mips32_insn.r_format.rs =
 181                                         insn.mm_fp5_format.base;
 182                                 mips32_insn.r_format.rt =
 183                                         insn.mm_fp5_format.index;
 184                                 mips32_insn.r_format.rd = 0;
 185                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 186                                 mips32_insn.r_format.func = func;
 187                         } else
 188                                 return SIGILL;
 189                         break;
 190                 case mm_32f_40_op:
 191                         op = -1;        /* Invalid */
 192                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 193                                 op = 1;
 194                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 195                                 op = 0;
 196                         if (op != -1) {
 197                                 mips32_insn.fp0_format.opcode = cop1_op;
 198                                 mips32_insn.fp0_format.fmt =
 199                                         sdps_format[insn.mm_fp2_format.fmt];
 200                                 mips32_insn.fp0_format.ft =
 201                                         (insn.mm_fp2_format.cc<<2) + op;
 202                                 mips32_insn.fp0_format.fs =
 203                                         insn.mm_fp2_format.fs;
 204                                 mips32_insn.fp0_format.fd =
 205                                         insn.mm_fp2_format.fd;
 206                                 mips32_insn.fp0_format.func = fmovc_op;
 207                         } else
 208                                 return SIGILL;
 209                         break;
 210                 case mm_32f_60_op:
 211                         func = -1;      /* Invalid */
 212                         if (insn.mm_fp0_format.op == mm_fadd_op)
 213                                 func = fadd_op;
 214                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 215                                 func = fsub_op;
 216                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 217                                 func = fmul_op;
 218                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 219                                 func = fdiv_op;
 220                         if (func != -1) {
 221                                 mips32_insn.fp0_format.opcode = cop1_op;
 222                                 mips32_insn.fp0_format.fmt =
 223                                         sdps_format[insn.mm_fp0_format.fmt];
 224                                 mips32_insn.fp0_format.ft =
 225                                         insn.mm_fp0_format.ft;
 226                                 mips32_insn.fp0_format.fs =
 227                                         insn.mm_fp0_format.fs;
 228                                 mips32_insn.fp0_format.fd =
 229                                         insn.mm_fp0_format.fd;
 230                                 mips32_insn.fp0_format.func = func;
 231                         } else
 232                                 return SIGILL;
 233                         break;
 234                 case mm_32f_70_op:
 235                         func = -1;      /* Invalid */
 236                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 237                                 func = fmovn_op;
 238                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 239                                 func = fmovz_op;
 240                         if (func != -1) {
 241                                 mips32_insn.fp0_format.opcode = cop1_op;
 242                                 mips32_insn.fp0_format.fmt =
 243                                         sdps_format[insn.mm_fp0_format.fmt];
 244                                 mips32_insn.fp0_format.ft =
 245                                         insn.mm_fp0_format.ft;
 246                                 mips32_insn.fp0_format.fs =
 247                                         insn.mm_fp0_format.fs;
 248                                 mips32_insn.fp0_format.fd =
 249                                         insn.mm_fp0_format.fd;
 250                                 mips32_insn.fp0_format.func = func;
 251                         } else
 252                                 return SIGILL;
 253                         break;
 254                 case mm_32f_73_op:    /* POOL32FXF */
 255                         switch (insn.mm_fp1_format.op) {
 256                         case mm_movf0_op:
 257                         case mm_movf1_op:
 258                         case mm_movt0_op:
 259                         case mm_movt1_op:
 260                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 261                                     mm_movf0_op)
 262                                         op = 0;
 263                                 else
 264                                         op = 1;
 265                                 mips32_insn.r_format.opcode = spec_op;
 266                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 267                                 mips32_insn.r_format.rt =
 268                                         (insn.mm_fp4_format.cc << 2) + op;
 269                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 270                                 mips32_insn.r_format.re = 0;
 271                                 mips32_insn.r_format.func = movc_op;
 272                                 break;
 273                         case mm_fcvtd0_op:
 274                         case mm_fcvtd1_op:
 275                         case mm_fcvts0_op:
 276                         case mm_fcvts1_op:
 277                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 278                                     mm_fcvtd0_op) {
 279                                         func = fcvtd_op;
 280                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 281                                 } else {
 282                                         func = fcvts_op;
 283                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 284                                 }
 285                                 mips32_insn.fp0_format.opcode = cop1_op;
 286                                 mips32_insn.fp0_format.fmt = fmt;
 287                                 mips32_insn.fp0_format.ft = 0;
 288                                 mips32_insn.fp0_format.fs =
 289                                         insn.mm_fp3_format.fs;
 290                                 mips32_insn.fp0_format.fd =
 291                                         insn.mm_fp3_format.rt;
 292                                 mips32_insn.fp0_format.func = func;
 293                                 break;
 294                         case mm_fmov0_op:
 295                         case mm_fmov1_op:
 296                         case mm_fabs0_op:
 297                         case mm_fabs1_op:
 298                         case mm_fneg0_op:
 299                         case mm_fneg1_op:
 300                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 301                                     mm_fmov0_op)
 302                                         func = fmov_op;
 303                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 304                                          mm_fabs0_op)
 305                                         func = fabs_op;
 306                                 else
 307                                         func = fneg_op;
 308                                 mips32_insn.fp0_format.opcode = cop1_op;
 309                                 mips32_insn.fp0_format.fmt =
 310                                         sdps_format[insn.mm_fp3_format.fmt];
 311                                 mips32_insn.fp0_format.ft = 0;
 312                                 mips32_insn.fp0_format.fs =
 313                                         insn.mm_fp3_format.fs;
 314                                 mips32_insn.fp0_format.fd =
 315                                         insn.mm_fp3_format.rt;
 316                                 mips32_insn.fp0_format.func = func;
 317                                 break;
 318                         case mm_ffloorl_op:
 319                         case mm_ffloorw_op:
 320                         case mm_fceill_op:
 321                         case mm_fceilw_op:
 322                         case mm_ftruncl_op:
 323                         case mm_ftruncw_op:
 324                         case mm_froundl_op:
 325                         case mm_froundw_op:
 326                         case mm_fcvtl_op:
 327                         case mm_fcvtw_op:
 328                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 329                                         func = ffloorl_op;
 330                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 331                                         func = ffloor_op;
 332                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 333                                         func = fceill_op;
 334                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 335                                         func = fceil_op;
 336                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 337                                         func = ftruncl_op;
 338                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 339                                         func = ftrunc_op;
 340                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 341                                         func = froundl_op;
 342                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 343                                         func = fround_op;
 344                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 345                                         func = fcvtl_op;
 346                                 else
 347                                         func = fcvtw_op;
 348                                 mips32_insn.fp0_format.opcode = cop1_op;
 349                                 mips32_insn.fp0_format.fmt =
 350                                         sd_format[insn.mm_fp1_format.fmt];
 351                                 mips32_insn.fp0_format.ft = 0;
 352                                 mips32_insn.fp0_format.fs =
 353                                         insn.mm_fp1_format.fs;
 354                                 mips32_insn.fp0_format.fd =
 355                                         insn.mm_fp1_format.rt;
 356                                 mips32_insn.fp0_format.func = func;
 357                                 break;
 358                         case mm_frsqrt_op:
 359                         case mm_fsqrt_op:
 360                         case mm_frecip_op:
 361                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 362                                         func = frsqrt_op;
 363                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 364                                         func = fsqrt_op;
 365                                 else
 366                                         func = frecip_op;
 367                                 mips32_insn.fp0_format.opcode = cop1_op;
 368                                 mips32_insn.fp0_format.fmt =
 369                                         sdps_format[insn.mm_fp1_format.fmt];
 370                                 mips32_insn.fp0_format.ft = 0;
 371                                 mips32_insn.fp0_format.fs =
 372                                         insn.mm_fp1_format.fs;
 373                                 mips32_insn.fp0_format.fd =
 374                                         insn.mm_fp1_format.rt;
 375                                 mips32_insn.fp0_format.func = func;
 376                                 break;
 377                         case mm_mfc1_op:
 378                         case mm_mtc1_op:
 379                         case mm_cfc1_op:
 380                         case mm_ctc1_op:
 381                         case mm_mfhc1_op:
 382                         case mm_mthc1_op:
 383                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 384                                         op = mfc_op;
 385                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 386                                         op = mtc_op;
 387                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 388                                         op = cfc_op;
 389                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 390                                         op = ctc_op;
 391                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 392                                         op = mfhc_op;
 393                                 else
 394                                         op = mthc_op;
 395                                 mips32_insn.fp1_format.opcode = cop1_op;
 396                                 mips32_insn.fp1_format.op = op;
 397                                 mips32_insn.fp1_format.rt =
 398                                         insn.mm_fp1_format.rt;
 399                                 mips32_insn.fp1_format.fs =
 400                                         insn.mm_fp1_format.fs;
 401                                 mips32_insn.fp1_format.fd = 0;
 402                                 mips32_insn.fp1_format.func = 0;
 403                                 break;
 404                         default:
 405                                 return SIGILL;
 406                         }
 407                         break;
 408                 case mm_32f_74_op:      /* c.cond.fmt */
 409                         mips32_insn.fp0_format.opcode = cop1_op;
 410                         mips32_insn.fp0_format.fmt =
 411                                 sdps_format[insn.mm_fp4_format.fmt];
 412                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 413                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 414                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 415                         mips32_insn.fp0_format.func =
 416                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 417                         break;
 418                 default:
 419                         return SIGILL;
 420                 }
 421                 break;
 422         default:
 423                 return SIGILL;
 424         }
 425
 426         *insn_ptr = mips32_insn;
 427         return 0;
 428 }
 429
 430 /*
 431  * Redundant with logic already in kernel/branch.c,
 432  * embedded in compute_return_epc.  At some point,
 433  * a single subroutine should be used across both
 434  * modules.
 435  */
 436 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 437                   unsigned long *contpc)
 438 {
 439         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 440         unsigned int fcr31;
 441         unsigned int bit = 0;
 442         unsigned int bit0;
 443         union fpureg *fpr;
 444
 445         switch (insn.i_format.opcode) {
 446         case spec_op:
 447                 switch (insn.r_format.func) {
 448                 case jalr_op:
 449                         if (insn.r_format.rd != 0) {
 450                                 regs->regs[insn.r_format.rd] =
 451                                         regs->cp0_epc + dec_insn.pc_inc +
 452                                         dec_insn.next_pc_inc;
 453                         }
 454                         /* Fall through */
 455                 case jr_op:
 456                         /* For R6, JR already emulated in jalr_op */
 457                         if (NO_R6EMU && insn.r_format.func == jr_op)
 458                                 break;
 459                         *contpc = regs->regs[insn.r_format.rs];
 460                         return 1;
 461                 }
 462                 break;
 463         case bcond_op:
 464                 switch (insn.i_format.rt) {
 465                 case bltzal_op:
 466                 case bltzall_op:
 467                         if (NO_R6EMU && (insn.i_format.rs ||
 468                             insn.i_format.rt == bltzall_op))
 469                                 break;
 470
 471                         regs->regs[31] = regs->cp0_epc +
 472                                 dec_insn.pc_inc +
 473                                 dec_insn.next_pc_inc;
 474                         /* Fall through */
 475                 case bltzl_op:
 476                         if (NO_R6EMU)
 477                                 break;
 478                 case bltz_op:
 479                         if ((long)regs->regs[insn.i_format.rs] < 0)
 480                                 *contpc = regs->cp0_epc +
 481                                         dec_insn.pc_inc +
 482                                         (insn.i_format.simmediate << 2);
 483                         else
 484                                 *contpc = regs->cp0_epc +
 485                                         dec_insn.pc_inc +
 486                                         dec_insn.next_pc_inc;
 487                         return 1;
 488                 case bgezal_op:
 489                 case bgezall_op:
 490                         if (NO_R6EMU && (insn.i_format.rs ||
 491                             insn.i_format.rt == bgezall_op))
 492                                 break;
 493
 494                         regs->regs[31] = regs->cp0_epc +
 495                                 dec_insn.pc_inc +
 496                                 dec_insn.next_pc_inc;
 497                         /* Fall through */
 498                 case bgezl_op:
 499                         if (NO_R6EMU)
 500                                 break;
 501                 case bgez_op:
 502                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 503                                 *contpc = regs->cp0_epc +
 504                                         dec_insn.pc_inc +
 505                                         (insn.i_format.simmediate << 2);
 506                         else
 507                                 *contpc = regs->cp0_epc +
 508                                         dec_insn.pc_inc +
 509                                         dec_insn.next_pc_inc;
 510                         return 1;
 511                 }
 512                 break;
 513         case jalx_op:
 514                 set_isa16_mode(bit);
 515         case jal_op:
 516                 regs->regs[31] = regs->cp0_epc +
 517                         dec_insn.pc_inc +
 518                         dec_insn.next_pc_inc;
 519                 /* Fall through */
 520         case j_op:
 521                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 522                 *contpc >>= 28;
 523                 *contpc <<= 28;
 524                 *contpc |= (insn.j_format.target << 2);
 525                 /* Set microMIPS mode bit: XOR for jalx. */
 526                 *contpc ^= bit;
 527                 return 1;
 528         case beql_op:
 529                 if (NO_R6EMU)
 530                         break;
 531         case beq_op:
 532                 if (regs->regs[insn.i_format.rs] ==
 533                     regs->regs[insn.i_format.rt])
 534                         *contpc = regs->cp0_epc +
 535                                 dec_insn.pc_inc +
 536                                 (insn.i_format.simmediate << 2);
 537                 else
 538                         *contpc = regs->cp0_epc +
 539                                 dec_insn.pc_inc +
 540                                 dec_insn.next_pc_inc;
 541                 return 1;
 542         case bnel_op:
 543                 if (NO_R6EMU)
 544                         break;
 545         case bne_op:
 546                 if (regs->regs[insn.i_format.rs] !=
 547                     regs->regs[insn.i_format.rt])
 548                         *contpc = regs->cp0_epc +
 549                                 dec_insn.pc_inc +
 550                                 (insn.i_format.simmediate << 2);
 551                 else
 552                         *contpc = regs->cp0_epc +
 553                                 dec_insn.pc_inc +
 554                                 dec_insn.next_pc_inc;
 555                 return 1;
 556         case blezl_op:
 557                 if (!insn.i_format.rt && NO_R6EMU)
 558                         break;
 559         case blez_op:
 560
 561                 /*
 562                  * Compact branches for R6 for the
 563                  * blez and blezl opcodes.
 564                  * BLEZ  | rs = 0 | rt != 0  == BLEZALC
 565                  * BLEZ  | rs = rt != 0      == BGEZALC
 566                  * BLEZ  | rs != 0 | rt != 0 == BGEUC
 567                  * BLEZL | rs = 0 | rt != 0  == BLEZC
 568                  * BLEZL | rs = rt != 0      == BGEZC
 569                  * BLEZL | rs != 0 | rt != 0 == BGEC
 570                  *
 571                  * For real BLEZ{,L}, rt is always 0.
 572                  */
 573                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 574                         if ((insn.i_format.opcode == blez_op) &&
 575                             ((!insn.i_format.rs && insn.i_format.rt) ||
 576                              (insn.i_format.rs == insn.i_format.rt)))
 577                                 regs->regs[31] = regs->cp0_epc +
 578                                         dec_insn.pc_inc;
 579                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 580                                 dec_insn.next_pc_inc;
 581
 582                         return 1;
 583                 }
 584                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 585                         *contpc = regs->cp0_epc +
 586                                 dec_insn.pc_inc +
 587                                 (insn.i_format.simmediate << 2);
 588                 else
 589                         *contpc = regs->cp0_epc +
 590                                 dec_insn.pc_inc +
 591                                 dec_insn.next_pc_inc;
 592                 return 1;
 593         case bgtzl_op:
 594                 if (!insn.i_format.rt && NO_R6EMU)
 595                         break;
 596         case bgtz_op:
 597                 /*
 598                  * Compact branches for R6 for the
 599                  * bgtz and bgtzl opcodes.
 600                  * BGTZ  | rs = 0 | rt != 0  == BGTZALC
 601                  * BGTZ  | rs = rt != 0      == BLTZALC
 602                  * BGTZ  | rs != 0 | rt != 0 == BLTUC
 603                  * BGTZL | rs = 0 | rt != 0  == BGTZC
 604                  * BGTZL | rs = rt != 0      == BLTZC
 605                  * BGTZL | rs != 0 | rt != 0 == BLTC
 606                  *
 607                  * *ZALC varint for BGTZ &&& rt != 0
 608                  * For real GTZ{,L}, rt is always 0.
 609                  */
 610                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 611                         if ((insn.i_format.opcode == blez_op) &&
 612                             ((!insn.i_format.rs && insn.i_format.rt) ||
 613                              (insn.i_format.rs == insn.i_format.rt)))
 614                                 regs->regs[31] = regs->cp0_epc +
 615                                         dec_insn.pc_inc;
 616                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 617                                 dec_insn.next_pc_inc;
 618
 619                         return 1;
 620                 }
 621
 622                 if ((long)regs->regs[insn.i_format.rs] > 0)
 623                         *contpc = regs->cp0_epc +
 624                                 dec_insn.pc_inc +
 625                                 (insn.i_format.simmediate << 2);
 626                 else
 627                         *contpc = regs->cp0_epc +
 628                                 dec_insn.pc_inc +
 629                                 dec_insn.next_pc_inc;
 630                 return 1;
 631         case pop10_op:
 632         case pop30_op:
 633                 if (!cpu_has_mips_r6)
 634                         break;
 635                 if (insn.i_format.rt && !insn.i_format.rs)
 636                         regs->regs[31] = regs->cp0_epc + 4;
 637                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 638                         dec_insn.next_pc_inc;
 639
 640                 return 1;
 641 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 642         case lwc2_op: /* This is bbit0 on Octeon */
 643                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 644                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 645                 else
 646                         *contpc = regs->cp0_epc + 8;
 647                 return 1;
 648         case ldc2_op: /* This is bbit032 on Octeon */
 649                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 650                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 651                 else
 652                         *contpc = regs->cp0_epc + 8;
 653                 return 1;
 654         case swc2_op: /* This is bbit1 on Octeon */
 655                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 656                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 657                 else
 658                         *contpc = regs->cp0_epc + 8;
 659                 return 1;
 660         case sdc2_op: /* This is bbit132 on Octeon */
 661                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 662                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 663                 else
 664                         *contpc = regs->cp0_epc + 8;
 665                 return 1;
 666 #else
 667         case bc6_op:
 668                 /*
 669                  * Only valid for MIPS R6 but we can still end up
 670                  * here from a broken userland so just tell emulator
 671                  * this is not a branch and let it break later on.
 672                  */
 673                 if  (!cpu_has_mips_r6)
 674                         break;
 675                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 676                         dec_insn.next_pc_inc;
 677
 678                 return 1;
 679         case balc6_op:
 680                 if (!cpu_has_mips_r6)
 681                         break;
 682                 regs->regs[31] = regs->cp0_epc + 4;
 683                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 684                         dec_insn.next_pc_inc;
 685
 686                 return 1;
 687         case pop66_op:
 688                 if (!cpu_has_mips_r6)
 689                         break;
 690                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 691                         dec_insn.next_pc_inc;
 692
 693                 return 1;
 694         case pop76_op:
 695                 if (!cpu_has_mips_r6)
 696                         break;
 697                 if (!insn.i_format.rs)
 698                         regs->regs[31] = regs->cp0_epc + 4;
 699                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 700                         dec_insn.next_pc_inc;
 701
 702                 return 1;
 703 #endif
 704         case cop0_op:
 705         case cop1_op:
 706                 /* Need to check for R6 bc1nez and bc1eqz branches */
 707                 if (cpu_has_mips_r6 &&
 708                     ((insn.i_format.rs == bc1eqz_op) ||
 709                      (insn.i_format.rs == bc1nez_op))) {
 710                         bit = 0;
 711                         fpr = &current->thread.fpu.fpr[insn.i_format.rt];
 712                         bit0 = get_fpr32(fpr, 0) & 0x1;
 713                         switch (insn.i_format.rs) {
 714                         case bc1eqz_op:
 715                                 bit = bit0 == 0;
 716                                 break;
 717                         case bc1nez_op:
 718                                 bit = bit0 != 0;
 719                                 break;
 720                         }
 721                         if (bit)
 722                                 *contpc = regs->cp0_epc +
 723                                         dec_insn.pc_inc +
 724                                         (insn.i_format.simmediate << 2);
 725                         else
 726                                 *contpc = regs->cp0_epc +
 727                                         dec_insn.pc_inc +
 728                                         dec_insn.next_pc_inc;
 729
 730                         return 1;
 731                 }
 732                 /* R2/R6 compatible cop1 instruction. Fall through */
 733         case cop2_op:
 734         case cop1x_op:
 735                 if (insn.i_format.rs == bc_op) {
 736                         preempt_disable();
 737                         if (is_fpu_owner())
 738                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 739                         else
 740                                 fcr31 = current->thread.fpu.fcr31;
 741                         preempt_enable();
 742
 743                         bit = (insn.i_format.rt >> 2);
 744                         bit += (bit != 0);
 745                         bit += 23;
 746                         switch (insn.i_format.rt & 3) {
 747                         case 0: /* bc1f */
 748                         case 2: /* bc1fl */
 749                                 if (~fcr31 & (1 << bit))
 750                                         *contpc = regs->cp0_epc +
 751                                                 dec_insn.pc_inc +
 752                                                 (insn.i_format.simmediate << 2);
 753                                 else
 754                                         *contpc = regs->cp0_epc +
 755                                                 dec_insn.pc_inc +
 756                                                 dec_insn.next_pc_inc;
 757                                 return 1;
 758                         case 1: /* bc1t */
 759                         case 3: /* bc1tl */
 760                                 if (fcr31 & (1 << bit))
 761                                         *contpc = regs->cp0_epc +
 762                                                 dec_insn.pc_inc +
 763                                                 (insn.i_format.simmediate << 2);
 764                                 else
 765                                         *contpc = regs->cp0_epc +
 766                                                 dec_insn.pc_inc +
 767                                                 dec_insn.next_pc_inc;
 768                                 return 1;
 769                         }
 770                 }
 771                 break;
 772         }
 773         return 0;
 774 }
 775
 776 /*
 777  * In the Linux kernel, we support selection of FPR format on the
 778  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 779  * is hardwired to zero, which would imply a 32-bit FPU even for
 780  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 781  * FPU emu is slow and bulky and optimizing this function offers fairly
 782  * sizeable benefits so we try to be clever and make this function return
 783  * a constant whenever possible, that is on 64-bit kernels without O32
 784  * compatibility enabled and on 32-bit without 64-bit FPU support.
 785  */
 786 static inline int cop1_64bit(struct pt_regs *xcp)
 787 {
 788         if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32))
 789                 return 1;
 790         else if (IS_ENABLED(CONFIG_32BIT) &&
 791                  !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
 792                 return 0;
 793
 794         return !test_thread_flag(TIF_32BIT_FPREGS);
 795 }
 796
 797 static inline bool hybrid_fprs(void)
 798 {
 799         return test_thread_flag(TIF_HYBRID_FPREGS);
 800 }
 801
 802 #define SIFROMREG(si, x)                                                \
 803 do {                                                                    \
 804         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
 805                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
 806         else                                                            \
 807                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 808 } while (0)
 809
 810 #define SITOREG(si, x)                                                  \
 811 do {                                                                    \
 812         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
 813                 unsigned i;                                             \
 814                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 815                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 816                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 817         } else {                                                        \
 818                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 819         }                                                               \
 820 } while (0)
 821
 822 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 823
 824 #define SITOHREG(si, x)                                                 \
 825 do {                                                                    \
 826         unsigned i;                                                     \
 827         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 828         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 829                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 830 } while (0)
 831
 832 #define DIFROMREG(di, x)                                                \
 833         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 834
 835 #define DITOREG(di, x)                                                  \
 836 do {                                                                    \
 837         unsigned fpr, i;                                                \
 838         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 839         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 840         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 841                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 842 } while (0)
 843
 844 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 845 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 846 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 847 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 848
 849 /*
 850  * Emulate a CFC1 instruction.
 851  */
 852 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 853                             mips_instruction ir)
 854 {
 855         u32 fcr31 = ctx->fcr31;
 856         u32 value = 0;
 857
 858         switch (MIPSInst_RD(ir)) {
 859         case FPCREG_CSR:
 860                 value = fcr31;
 861                 pr_debug("%p gpr[%d]<-csr=%08x\n",
 862                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 863                 break;
 864
 865         case FPCREG_FENR:
 866                 if (!cpu_has_mips_r)
 867                         break;
 868                 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
 869                         MIPS_FENR_FS;
 870                 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
 871                 pr_debug("%p gpr[%d]<-enr=%08x\n",
 872                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 873                 break;
 874
 875         case FPCREG_FEXR:
 876                 if (!cpu_has_mips_r)
 877                         break;
 878                 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 879                 pr_debug("%p gpr[%d]<-exr=%08x\n",
 880                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 881                 break;
 882
 883         case FPCREG_FCCR:
 884                 if (!cpu_has_mips_r)
 885                         break;
 886                 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
 887                         MIPS_FCCR_COND0;
 888                 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
 889                          (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
 890                 pr_debug("%p gpr[%d]<-ccr=%08x\n",
 891                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 892                 break;
 893
 894         case FPCREG_RID:
 895                 value = boot_cpu_data.fpu_id;
 896                 break;
 897
 898         default:
 899                 break;
 900         }
 901
 902         if (MIPSInst_RT(ir))
 903                 xcp->regs[MIPSInst_RT(ir)] = value;
 904 }
 905
 906 /*
 907  * Emulate a CTC1 instruction.
 908  */
 909 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 910                             mips_instruction ir)
 911 {
 912         u32 fcr31 = ctx->fcr31;
 913         u32 value;
 914         u32 mask;
 915
 916         if (MIPSInst_RT(ir) == 0)
 917                 value = 0;
 918         else
 919                 value = xcp->regs[MIPSInst_RT(ir)];
 920
 921         switch (MIPSInst_RD(ir)) {
 922         case FPCREG_CSR:
 923                 pr_debug("%p gpr[%d]->csr=%08x\n",
 924                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 925
 926                 /* Preserve read-only bits.  */
 927                 mask = boot_cpu_data.fpu_msk31;
 928                 fcr31 = (value & ~mask) | (fcr31 & mask);
 929                 break;
 930
 931         case FPCREG_FENR:
 932                 if (!cpu_has_mips_r)
 933                         break;
 934                 pr_debug("%p gpr[%d]->enr=%08x\n",
 935                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 936                 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
 937                 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
 938                          FPU_CSR_FS;
 939                 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
 940                 break;
 941
 942         case FPCREG_FEXR:
 943                 if (!cpu_has_mips_r)
 944                         break;
 945                 pr_debug("%p gpr[%d]->exr=%08x\n",
 946                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 947                 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 948                 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 949                 break;
 950
 951         case FPCREG_FCCR:
 952                 if (!cpu_has_mips_r)
 953                         break;
 954                 pr_debug("%p gpr[%d]->ccr=%08x\n",
 955                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 956                 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
 957                 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
 958                          FPU_CSR_COND;
 959                 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
 960                          FPU_CSR_CONDX;
 961                 break;
 962
 963         default:
 964                 break;
 965         }
 966
 967         ctx->fcr31 = fcr31;
 968 }
 969
 970 /*
 971  * Emulate the single floating point instruction pointed at by EPC.
 972  * Two instructions if the instruction is in a branch delay slot.
 973  */
 974
 975 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 976                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 977 {
 978         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 979         unsigned int cond, cbit, bit0;
 980         mips_instruction ir;
 981         int likely, pc_inc;
 982         union fpureg *fpr;
 983         u32 __user *wva;
 984         u64 __user *dva;
 985         u32 wval;
 986         u64 dval;
 987         int sig;
 988
 989         /*
 990          * These are giving gcc a gentle hint about what to expect in
 991          * dec_inst in order to do better optimization.
 992          */
 993         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 994                 unreachable();
 995
 996         /* XXX NEC Vr54xx bug workaround */
 997         if (delay_slot(xcp)) {
 998                 if (dec_insn.micro_mips_mode) {
 999                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
1000                                 clear_delay_slot(xcp);
1001                 } else {
1002                         if (!isBranchInstr(xcp, dec_insn, &contpc))
1003                                 clear_delay_slot(xcp);
1004                 }
1005         }
1006
1007         if (delay_slot(xcp)) {
1008                 /*
1009                  * The instruction to be emulated is in a branch delay slot
1010                  * which means that we have to  emulate the branch instruction
1011                  * BEFORE we do the cop1 instruction.
1012                  *
1013                  * This branch could be a COP1 branch, but in that case we
1014                  * would have had a trap for that instruction, and would not
1015                  * come through this route.
1016                  *
1017                  * Linux MIPS branch emulator operates on context, updating the
1018                  * cp0_epc.
1019                  */
1020                 ir = dec_insn.next_insn;  /* process delay slot instr */
1021                 pc_inc = dec_insn.next_pc_inc;
1022         } else {
1023                 ir = dec_insn.insn;       /* process current instr */
1024                 pc_inc = dec_insn.pc_inc;
1025         }
1026
1027         /*
1028          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1029          * instructions, we want to convert microMIPS FPU instructions
1030          * into MIPS32 instructions so that we could reuse all of the
1031          * FPU emulation code.
1032          *
1033          * NOTE: We cannot do this for branch instructions since they
1034          *       are not a subset. Example: Cannot emulate a 16-bit
1035          *       aligned target address with a MIPS32 instruction.
1036          */
1037         if (dec_insn.micro_mips_mode) {
1038                 /*
1039                  * If next instruction is a 16-bit instruction, then it
1040                  * it cannot be a FPU instruction. This could happen
1041                  * since we can be called for non-FPU instructions.
1042                  */
1043                 if ((pc_inc == 2) ||
1044                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1045                          == SIGILL))
1046                         return SIGILL;
1047         }
1048
1049 emul:
1050         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1051         MIPS_FPU_EMU_INC_STATS(emulated);
1052         switch (MIPSInst_OPCODE(ir)) {
1053         case ldc1_op:
1054                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1055                                      MIPSInst_SIMM(ir));
1056                 MIPS_FPU_EMU_INC_STATS(loads);
1057
1058                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1059                         MIPS_FPU_EMU_INC_STATS(errors);
1060                         *fault_addr = dva;
1061                         return SIGBUS;
1062                 }
1063                 if (__get_user(dval, dva)) {
1064                         MIPS_FPU_EMU_INC_STATS(errors);
1065                         *fault_addr = dva;
1066                         return SIGSEGV;
1067                 }
1068                 DITOREG(dval, MIPSInst_RT(ir));
1069                 break;
1070
1071         case sdc1_op:
1072                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1073                                       MIPSInst_SIMM(ir));
1074                 MIPS_FPU_EMU_INC_STATS(stores);
1075                 DIFROMREG(dval, MIPSInst_RT(ir));
1076                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1077                         MIPS_FPU_EMU_INC_STATS(errors);
1078                         *fault_addr = dva;
1079                         return SIGBUS;
1080                 }
1081                 if (__put_user(dval, dva)) {
1082                         MIPS_FPU_EMU_INC_STATS(errors);
1083                         *fault_addr = dva;
1084                         return SIGSEGV;
1085                 }
1086                 break;
1087
1088         case lwc1_op:
1089                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1090                                       MIPSInst_SIMM(ir));
1091                 MIPS_FPU_EMU_INC_STATS(loads);
1092                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1093                         MIPS_FPU_EMU_INC_STATS(errors);
1094                         *fault_addr = wva;
1095                         return SIGBUS;
1096                 }
1097                 if (__get_user(wval, wva)) {
1098                         MIPS_FPU_EMU_INC_STATS(errors);
1099                         *fault_addr = wva;
1100                         return SIGSEGV;
1101                 }
1102                 SITOREG(wval, MIPSInst_RT(ir));
1103                 break;
1104
1105         case swc1_op:
1106                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1107                                       MIPSInst_SIMM(ir));
1108                 MIPS_FPU_EMU_INC_STATS(stores);
1109                 SIFROMREG(wval, MIPSInst_RT(ir));
1110                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1111                         MIPS_FPU_EMU_INC_STATS(errors);
1112                         *fault_addr = wva;
1113                         return SIGBUS;
1114                 }
1115                 if (__put_user(wval, wva)) {
1116                         MIPS_FPU_EMU_INC_STATS(errors);
1117                         *fault_addr = wva;
1118                         return SIGSEGV;
1119                 }
1120                 break;
1121
1122         case cop1_op:
1123                 switch (MIPSInst_RS(ir)) {
1124                 case dmfc_op:
1125                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1126                                 return SIGILL;
1127
1128                         /* copregister fs -> gpr[rt] */
1129                         if (MIPSInst_RT(ir) != 0) {
1130                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1131                                         MIPSInst_RD(ir));
1132                         }
1133                         break;
1134
1135                 case dmtc_op:
1136                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1137                                 return SIGILL;
1138
1139                         /* copregister fs <- rt */
1140                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1141                         break;
1142
1143                 case mfhc_op:
1144                         if (!cpu_has_mips_r2_r6)
1145                                 goto sigill;
1146
1147                         /* copregister rd -> gpr[rt] */
1148                         if (MIPSInst_RT(ir) != 0) {
1149                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1150                                         MIPSInst_RD(ir));
1151                         }
1152                         break;
1153
1154                 case mthc_op:
1155                         if (!cpu_has_mips_r2_r6)
1156                                 goto sigill;
1157
1158                         /* copregister rd <- gpr[rt] */
1159                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1160                         break;
1161
1162                 case mfc_op:
1163                         /* copregister rd -> gpr[rt] */
1164                         if (MIPSInst_RT(ir) != 0) {
1165                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1166                                         MIPSInst_RD(ir));
1167                         }
1168                         break;
1169
1170                 case mtc_op:
1171                         /* copregister rd <- rt */
1172                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1173                         break;
1174
1175                 case cfc_op:
1176                         /* cop control register rd -> gpr[rt] */
1177                         cop1_cfc(xcp, ctx, ir);
1178                         break;
1179
1180                 case ctc_op:
1181                         /* copregister rd <- rt */
1182                         cop1_ctc(xcp, ctx, ir);
1183                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1184                                 return SIGFPE;
1185                         }
1186                         break;
1187
1188                 case bc1eqz_op:
1189                 case bc1nez_op:
1190                         if (!cpu_has_mips_r6 || delay_slot(xcp))
1191                                 return SIGILL;
1192
1193                         cond = likely = 0;
1194                         fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];
1195                         bit0 = get_fpr32(fpr, 0) & 0x1;
1196                         switch (MIPSInst_RS(ir)) {
1197                         case bc1eqz_op:
1198                                 cond = bit0 == 0;
1199                                 break;
1200                         case bc1nez_op:
1201                                 cond = bit0 != 0;
1202                                 break;
1203                         }
1204                         goto branch_common;
1205
1206                 case bc_op:
1207                         if (delay_slot(xcp))
1208                                 return SIGILL;
1209
1210                         if (cpu_has_mips_4_5_r)
1211                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1212                         else
1213                                 cbit = FPU_CSR_COND;
1214                         cond = ctx->fcr31 & cbit;
1215
1216                         likely = 0;
1217                         switch (MIPSInst_RT(ir) & 3) {
1218                         case bcfl_op:
1219                                 if (cpu_has_mips_2_3_4_5_r)
1220                                         likely = 1;
1221                                 /* Fall through */
1222                         case bcf_op:
1223                                 cond = !cond;
1224                                 break;
1225                         case bctl_op:
1226                                 if (cpu_has_mips_2_3_4_5_r)
1227                                         likely = 1;
1228                                 /* Fall through */
1229                         case bct_op:
1230                                 break;
1231                         }
1232 branch_common:
1233                         set_delay_slot(xcp);
1234                         if (cond) {
1235                                 /*
1236                                  * Branch taken: emulate dslot instruction
1237                                  */
1238                                 unsigned long bcpc;
1239
1240                                 /*
1241                                  * Remember EPC at the branch to point back
1242                                  * at so that any delay-slot instruction
1243                                  * signal is not silently ignored.
1244                                  */
1245                                 bcpc = xcp->cp0_epc;
1246                                 xcp->cp0_epc += dec_insn.pc_inc;
1247
1248                                 contpc = MIPSInst_SIMM(ir);
1249                                 ir = dec_insn.next_insn;
1250                                 if (dec_insn.micro_mips_mode) {
1251                                         contpc = (xcp->cp0_epc + (contpc << 1));
1252
1253                                         /* If 16-bit instruction, not FPU. */
1254                                         if ((dec_insn.next_pc_inc == 2) ||
1255                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1256
1257                                                 /*
1258                                                  * Since this instruction will
1259                                                  * be put on the stack with
1260                                                  * 32-bit words, get around
1261                                                  * this problem by putting a
1262                                                  * NOP16 as the second one.
1263                                                  */
1264                                                 if (dec_insn.next_pc_inc == 2)
1265                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1266
1267                                                 /*
1268                                                  * Single step the non-CP1
1269                                                  * instruction in the dslot.
1270                                                  */
1271                                                 sig = mips_dsemul(xcp, ir,
1272                                                                   bcpc, contpc);
1273                                                 if (sig < 0)
1274                                                         break;
1275                                                 if (sig)
1276                                                         xcp->cp0_epc = bcpc;
1277                                                 /*
1278                                                  * SIGILL forces out of
1279                                                  * the emulation loop.
1280                                                  */
1281                                                 return sig ? sig : SIGILL;
1282                                         }
1283                                 } else
1284                                         contpc = (xcp->cp0_epc + (contpc << 2));
1285
1286                                 switch (MIPSInst_OPCODE(ir)) {
1287                                 case lwc1_op:
1288                                 case swc1_op:
1289                                         goto emul;
1290
1291                                 case ldc1_op:
1292                                 case sdc1_op:
1293                                         if (cpu_has_mips_2_3_4_5_r)
1294                                                 goto emul;
1295
1296                                         goto bc_sigill;
1297
1298                                 case cop1_op:
1299                                         goto emul;
1300
1301                                 case cop1x_op:
1302                                         if (cpu_has_mips_4_5_64_r2_r6)
1303                                                 /* its one of ours */
1304                                                 goto emul;
1305
1306                                         goto bc_sigill;
1307
1308                                 case spec_op:
1309                                         switch (MIPSInst_FUNC(ir)) {
1310                                         case movc_op:
1311                                                 if (cpu_has_mips_4_5_r)
1312                                                         goto emul;
1313
1314                                                 goto bc_sigill;
1315                                         }
1316                                         break;
1317
1318                                 bc_sigill:
1319                                         xcp->cp0_epc = bcpc;
1320                                         return SIGILL;
1321                                 }
1322
1323                                 /*
1324                                  * Single step the non-cp1
1325                                  * instruction in the dslot
1326                                  */
1327                                 sig = mips_dsemul(xcp, ir, bcpc, contpc);
1328                                 if (sig < 0)
1329                                         break;
1330                                 if (sig)
1331                                         xcp->cp0_epc = bcpc;
1332                                 /* SIGILL forces out of the emulation loop.  */
1333                                 return sig ? sig : SIGILL;
1334                         } else if (likely) {    /* branch not taken */
1335                                 /*
1336                                  * branch likely nullifies
1337                                  * dslot if not taken
1338                                  */
1339                                 xcp->cp0_epc += dec_insn.pc_inc;
1340                                 contpc += dec_insn.pc_inc;
1341                                 /*
1342                                  * else continue & execute
1343                                  * dslot as normal insn
1344                                  */
1345                         }
1346                         break;
1347
1348                 default:
1349                         if (!(MIPSInst_RS(ir) & 0x10))
1350                                 return SIGILL;
1351
1352                         /* a real fpu computation instruction */
1353                         if ((sig = fpu_emu(xcp, ctx, ir)))
1354                                 return sig;
1355                 }
1356                 break;
1357
1358         case cop1x_op:
1359                 if (!cpu_has_mips_4_5_64_r2_r6)
1360                         return SIGILL;
1361
1362                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1363                 if (sig)
1364                         return sig;
1365                 break;
1366
1367         case spec_op:
1368                 if (!cpu_has_mips_4_5_r)
1369                         return SIGILL;
1370
1371                 if (MIPSInst_FUNC(ir) != movc_op)
1372                         return SIGILL;
1373                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1374                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1375                         xcp->regs[MIPSInst_RD(ir)] =
1376                                 xcp->regs[MIPSInst_RS(ir)];
1377                 break;
1378         default:
1379 sigill:
1380                 return SIGILL;
1381         }
1382
1383         /* we did it !! */
1384         xcp->cp0_epc = contpc;
1385         clear_delay_slot(xcp);
1386
1387         return 0;
1388 }
1389
1390 /*
1391  * Conversion table from MIPS compare ops 48-63
1392  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1393  */
1394 static const unsigned char cmptab[8] = {
1395         0,                      /* cmp_0 (sig) cmp_sf */
1396         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1397         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1398         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1399         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1400         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1401         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1402         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1403 };
1404
1405 static const unsigned char negative_cmptab[8] = {
1406         0, /* Reserved */
1407         IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1408         IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1409         IEEE754_CLT | IEEE754_CGT,
1410         /* Reserved */
1411 };
1412
1413
1414 /*
1415  * Additional MIPS4 instructions
1416  */
1417
1418 #define DEF3OP(name, p, f1, f2, f3)                                     \
1419 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1420         union ieee754##p s, union ieee754##p t)                         \
1421 {                                                                       \
1422         struct _ieee754_csr ieee754_csr_save;                           \
1423         s = f1(s, t);                                                   \
1424         ieee754_csr_save = ieee754_csr;                                 \
1425         s = f2(s, r);                                                   \
1426         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1427         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1428         s = f3(s);                                                      \
1429         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1430         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1431         return s;                                                       \
1432 }
1433
1434 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1435 {
1436         return ieee754dp_div(ieee754dp_one(0), d);
1437 }
1438
1439 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1440 {
1441         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1442 }
1443
1444 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1445 {
1446         return ieee754sp_div(ieee754sp_one(0), s);
1447 }
1448
1449 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1450 {
1451         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1452 }
1453
1454 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1455 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1456 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1457 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1458 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1459 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1460 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1461 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1462
1463 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1464         mips_instruction ir, void *__user *fault_addr)
1465 {
1466         unsigned rcsr = 0;      /* resulting csr */
1467
1468         MIPS_FPU_EMU_INC_STATS(cp1xops);
1469
1470         switch (MIPSInst_FMA_FFMT(ir)) {
1471         case s_fmt:{            /* 0 */
1472
1473                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1474                 union ieee754sp fd, fr, fs, ft;
1475                 u32 __user *va;
1476                 u32 val;
1477
1478                 switch (MIPSInst_FUNC(ir)) {
1479                 case lwxc1_op:
1480                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1481                                 xcp->regs[MIPSInst_FT(ir)]);
1482
1483                         MIPS_FPU_EMU_INC_STATS(loads);
1484                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1485                                 MIPS_FPU_EMU_INC_STATS(errors);
1486                                 *fault_addr = va;
1487                                 return SIGBUS;
1488                         }
1489                         if (__get_user(val, va)) {
1490                                 MIPS_FPU_EMU_INC_STATS(errors);
1491                                 *fault_addr = va;
1492                                 return SIGSEGV;
1493                         }
1494                         SITOREG(val, MIPSInst_FD(ir));
1495                         break;
1496
1497                 case swxc1_op:
1498                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1499                                 xcp->regs[MIPSInst_FT(ir)]);
1500
1501                         MIPS_FPU_EMU_INC_STATS(stores);
1502
1503                         SIFROMREG(val, MIPSInst_FS(ir));
1504                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1505                                 MIPS_FPU_EMU_INC_STATS(errors);
1506                                 *fault_addr = va;
1507                                 return SIGBUS;
1508                         }
1509                         if (put_user(val, va)) {
1510                                 MIPS_FPU_EMU_INC_STATS(errors);
1511                                 *fault_addr = va;
1512                                 return SIGSEGV;
1513                         }
1514                         break;
1515
1516                 case madd_s_op:
1517                         handler = fpemu_sp_madd;
1518                         goto scoptop;
1519                 case msub_s_op:
1520                         handler = fpemu_sp_msub;
1521                         goto scoptop;
1522                 case nmadd_s_op:
1523                         handler = fpemu_sp_nmadd;
1524                         goto scoptop;
1525                 case nmsub_s_op:
1526                         handler = fpemu_sp_nmsub;
1527                         goto scoptop;
1528
1529                       scoptop:
1530                         SPFROMREG(fr, MIPSInst_FR(ir));
1531                         SPFROMREG(fs, MIPSInst_FS(ir));
1532                         SPFROMREG(ft, MIPSInst_FT(ir));
1533                         fd = (*handler) (fr, fs, ft);
1534                         SPTOREG(fd, MIPSInst_FD(ir));
1535
1536                       copcsr:
1537                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1538                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1539                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1540                         }
1541                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1542                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1543                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1544                         }
1545                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1546                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1547                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1548                         }
1549                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1550                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1551                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1552                         }
1553
1554                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1555                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1556                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1557                                    ctx->fcr31); */
1558                                 return SIGFPE;
1559                         }
1560
1561                         break;
1562
1563                 default:
1564                         return SIGILL;
1565                 }
1566                 break;
1567         }
1568
1569         case d_fmt:{            /* 1 */
1570                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1571                 union ieee754dp fd, fr, fs, ft;
1572                 u64 __user *va;
1573                 u64 val;
1574
1575                 switch (MIPSInst_FUNC(ir)) {
1576                 case ldxc1_op:
1577                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1578                                 xcp->regs[MIPSInst_FT(ir)]);
1579
1580                         MIPS_FPU_EMU_INC_STATS(loads);
1581                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1582                                 MIPS_FPU_EMU_INC_STATS(errors);
1583                                 *fault_addr = va;
1584                                 return SIGBUS;
1585                         }
1586                         if (__get_user(val, va)) {
1587                                 MIPS_FPU_EMU_INC_STATS(errors);
1588                                 *fault_addr = va;
1589                                 return SIGSEGV;
1590                         }
1591                         DITOREG(val, MIPSInst_FD(ir));
1592                         break;
1593
1594                 case sdxc1_op:
1595                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1596                                 xcp->regs[MIPSInst_FT(ir)]);
1597
1598                         MIPS_FPU_EMU_INC_STATS(stores);
1599                         DIFROMREG(val, MIPSInst_FS(ir));
1600                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1601                                 MIPS_FPU_EMU_INC_STATS(errors);
1602                                 *fault_addr = va;
1603                                 return SIGBUS;
1604                         }
1605                         if (__put_user(val, va)) {
1606                                 MIPS_FPU_EMU_INC_STATS(errors);
1607                                 *fault_addr = va;
1608                                 return SIGSEGV;
1609                         }
1610                         break;
1611
1612                 case madd_d_op:
1613                         handler = fpemu_dp_madd;
1614                         goto dcoptop;
1615                 case msub_d_op:
1616                         handler = fpemu_dp_msub;
1617                         goto dcoptop;
1618                 case nmadd_d_op:
1619                         handler = fpemu_dp_nmadd;
1620                         goto dcoptop;
1621                 case nmsub_d_op:
1622                         handler = fpemu_dp_nmsub;
1623                         goto dcoptop;
1624
1625                       dcoptop:
1626                         DPFROMREG(fr, MIPSInst_FR(ir));
1627                         DPFROMREG(fs, MIPSInst_FS(ir));
1628                         DPFROMREG(ft, MIPSInst_FT(ir));
1629                         fd = (*handler) (fr, fs, ft);
1630                         DPTOREG(fd, MIPSInst_FD(ir));
1631                         goto copcsr;
1632
1633                 default:
1634                         return SIGILL;
1635                 }
1636                 break;
1637         }
1638
1639         case 0x3:
1640                 if (MIPSInst_FUNC(ir) != pfetch_op)
1641                         return SIGILL;
1642
1643                 /* ignore prefx operation */
1644                 break;
1645
1646         default:
1647                 return SIGILL;
1648         }
1649
1650         return 0;
1651 }
1652
1653
1654
1655 /*
1656  * Emulate a single COP1 arithmetic instruction.
1657  */
1658 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1659         mips_instruction ir)
1660 {
1661         int rfmt;               /* resulting format */
1662         unsigned rcsr = 0;      /* resulting csr */
1663         unsigned int oldrm;
1664         unsigned int cbit;
1665         unsigned cond;
1666         union {
1667                 union ieee754dp d;
1668                 union ieee754sp s;
1669                 int w;
1670                 s64 l;
1671         } rv;                   /* resulting value */
1672         u64 bits;
1673
1674         MIPS_FPU_EMU_INC_STATS(cp1ops);
1675         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1676         case s_fmt: {           /* 0 */
1677                 union {
1678                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1679                         union ieee754sp(*u) (union ieee754sp);
1680                 } handler;
1681                 union ieee754sp fd, fs, ft;
1682
1683                 switch (MIPSInst_FUNC(ir)) {
1684                         /* binary ops */
1685                 case fadd_op:
1686                         handler.b = ieee754sp_add;
1687                         goto scopbop;
1688                 case fsub_op:
1689                         handler.b = ieee754sp_sub;
1690                         goto scopbop;
1691                 case fmul_op:
1692                         handler.b = ieee754sp_mul;
1693                         goto scopbop;
1694                 case fdiv_op:
1695                         handler.b = ieee754sp_div;
1696                         goto scopbop;
1697
1698                         /* unary  ops */
1699                 case fsqrt_op:
1700                         if (!cpu_has_mips_2_3_4_5_r)
1701                                 return SIGILL;
1702
1703                         handler.u = ieee754sp_sqrt;
1704                         goto scopuop;
1705
1706                 /*
1707                  * Note that on some MIPS IV implementations such as the
1708                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1709                  * achieve full IEEE-754 accuracy - however this emulator does.
1710                  */
1711                 case frsqrt_op:
1712                         if (!cpu_has_mips_4_5_64_r2_r6)
1713                                 return SIGILL;
1714
1715                         handler.u = fpemu_sp_rsqrt;
1716                         goto scopuop;
1717
1718                 case frecip_op:
1719                         if (!cpu_has_mips_4_5_64_r2_r6)
1720                                 return SIGILL;
1721
1722                         handler.u = fpemu_sp_recip;
1723                         goto scopuop;
1724
1725                 case fmovc_op:
1726                         if (!cpu_has_mips_4_5_r)
1727                                 return SIGILL;
1728
1729                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1730                         if (((ctx->fcr31 & cond) != 0) !=
1731                                 ((MIPSInst_FT(ir) & 1) != 0))
1732                                 return 0;
1733                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1734                         break;
1735
1736                 case fmovz_op:
1737                         if (!cpu_has_mips_4_5_r)
1738                                 return SIGILL;
1739
1740                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1741                                 return 0;
1742                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1743                         break;
1744
1745                 case fmovn_op:
1746                         if (!cpu_has_mips_4_5_r)
1747                                 return SIGILL;
1748
1749                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1750                                 return 0;
1751                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1752                         break;
1753
1754                 case fseleqz_op:
1755                         if (!cpu_has_mips_r6)
1756                                 return SIGILL;
1757
1758                         SPFROMREG(rv.s, MIPSInst_FT(ir));
1759                         if (rv.w & 0x1)
1760                                 rv.w = 0;
1761                         else
1762                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
1763                         break;
1764
1765                 case fselnez_op:
1766                         if (!cpu_has_mips_r6)
1767                                 return SIGILL;
1768
1769                         SPFROMREG(rv.s, MIPSInst_FT(ir));
1770                         if (rv.w & 0x1)
1771                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
1772                         else
1773                                 rv.w = 0;
1774                         break;
1775
1776                 case fmaddf_op: {
1777                         union ieee754sp ft, fs, fd;
1778
1779                         if (!cpu_has_mips_r6)
1780                                 return SIGILL;
1781
1782                         SPFROMREG(ft, MIPSInst_FT(ir));
1783                         SPFROMREG(fs, MIPSInst_FS(ir));
1784                         SPFROMREG(fd, MIPSInst_FD(ir));
1785                         rv.s = ieee754sp_maddf(fd, fs, ft);
1786                         break;
1787                 }
1788
1789                 case fmsubf_op: {
1790                         union ieee754sp ft, fs, fd;
1791
1792                         if (!cpu_has_mips_r6)
1793                                 return SIGILL;
1794
1795                         SPFROMREG(ft, MIPSInst_FT(ir));
1796                         SPFROMREG(fs, MIPSInst_FS(ir));
1797                         SPFROMREG(fd, MIPSInst_FD(ir));
1798                         rv.s = ieee754sp_msubf(fd, fs, ft);
1799                         break;
1800                 }
1801
1802                 case frint_op: {
1803                         union ieee754sp fs;
1804
1805                         if (!cpu_has_mips_r6)
1806                                 return SIGILL;
1807
1808                         SPFROMREG(fs, MIPSInst_FS(ir));
1809                         rv.l = ieee754sp_tlong(fs);
1810                         rv.s = ieee754sp_flong(rv.l);
1811                         goto copcsr;
1812                 }
1813
1814                 case fclass_op: {
1815                         union ieee754sp fs;
1816
1817                         if (!cpu_has_mips_r6)
1818                                 return SIGILL;
1819
1820                         SPFROMREG(fs, MIPSInst_FS(ir));
1821                         rv.w = ieee754sp_2008class(fs);
1822                         rfmt = w_fmt;
1823                         break;
1824                 }
1825
1826                 case fmin_op: {
1827                         union ieee754sp fs, ft;
1828
1829                         if (!cpu_has_mips_r6)
1830                                 return SIGILL;
1831
1832                         SPFROMREG(ft, MIPSInst_FT(ir));
1833                         SPFROMREG(fs, MIPSInst_FS(ir));
1834                         rv.s = ieee754sp_fmin(fs, ft);
1835                         break;
1836                 }
1837
1838                 case fmina_op: {
1839                         union ieee754sp fs, ft;
1840
1841                         if (!cpu_has_mips_r6)
1842                                 return SIGILL;
1843
1844                         SPFROMREG(ft, MIPSInst_FT(ir));
1845                         SPFROMREG(fs, MIPSInst_FS(ir));
1846                         rv.s = ieee754sp_fmina(fs, ft);
1847                         break;
1848                 }
1849
1850                 case fmax_op: {
1851                         union ieee754sp fs, ft;
1852
1853                         if (!cpu_has_mips_r6)
1854                                 return SIGILL;
1855
1856                         SPFROMREG(ft, MIPSInst_FT(ir));
1857                         SPFROMREG(fs, MIPSInst_FS(ir));
1858                         rv.s = ieee754sp_fmax(fs, ft);
1859                         break;
1860                 }
1861
1862                 case fmaxa_op: {
1863                         union ieee754sp fs, ft;
1864
1865                         if (!cpu_has_mips_r6)
1866                                 return SIGILL;
1867
1868                         SPFROMREG(ft, MIPSInst_FT(ir));
1869                         SPFROMREG(fs, MIPSInst_FS(ir));
1870                         rv.s = ieee754sp_fmaxa(fs, ft);
1871                         break;
1872                 }
1873
1874                 case fabs_op:
1875                         handler.u = ieee754sp_abs;
1876                         goto scopuop;
1877
1878                 case fneg_op:
1879                         handler.u = ieee754sp_neg;
1880                         goto scopuop;
1881
1882                 case fmov_op:
1883                         /* an easy one */
1884                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1885                         goto copcsr;
1886
1887                         /* binary op on handler */
1888 scopbop:
1889                         SPFROMREG(fs, MIPSInst_FS(ir));
1890                         SPFROMREG(ft, MIPSInst_FT(ir));
1891
1892                         rv.s = (*handler.b) (fs, ft);
1893                         goto copcsr;
1894 scopuop:
1895                         SPFROMREG(fs, MIPSInst_FS(ir));
1896                         rv.s = (*handler.u) (fs);
1897                         goto copcsr;
1898 copcsr:
1899                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1900                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1901                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1902                         }
1903                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1904                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1905                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1906                         }
1907                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1908                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1909                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1910                         }
1911                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1912                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1913                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1914                         }
1915                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1916                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1917                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1918                         }
1919                         break;
1920
1921                         /* unary conv ops */
1922                 case fcvts_op:
1923                         return SIGILL;  /* not defined */
1924
1925                 case fcvtd_op:
1926                         SPFROMREG(fs, MIPSInst_FS(ir));
1927                         rv.d = ieee754dp_fsp(fs);
1928                         rfmt = d_fmt;
1929                         goto copcsr;
1930
1931                 case fcvtw_op:
1932                         SPFROMREG(fs, MIPSInst_FS(ir));
1933                         rv.w = ieee754sp_tint(fs);
1934                         rfmt = w_fmt;
1935                         goto copcsr;
1936
1937                 case fround_op:
1938                 case ftrunc_op:
1939                 case fceil_op:
1940                 case ffloor_op:
1941                         if (!cpu_has_mips_2_3_4_5_r)
1942                                 return SIGILL;
1943
1944                         oldrm = ieee754_csr.rm;
1945                         SPFROMREG(fs, MIPSInst_FS(ir));
1946                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1947                         rv.w = ieee754sp_tint(fs);
1948                         ieee754_csr.rm = oldrm;
1949                         rfmt = w_fmt;
1950                         goto copcsr;
1951
1952                 case fsel_op:
1953                         if (!cpu_has_mips_r6)
1954                                 return SIGILL;
1955
1956                         SPFROMREG(fd, MIPSInst_FD(ir));
1957                         if (fd.bits & 0x1)
1958                                 SPFROMREG(rv.s, MIPSInst_FT(ir));
1959                         else
1960                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
1961                         break;
1962
1963                 case fcvtl_op:
1964                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1965                                 return SIGILL;
1966
1967                         SPFROMREG(fs, MIPSInst_FS(ir));
1968                         rv.l = ieee754sp_tlong(fs);
1969                         rfmt = l_fmt;
1970                         goto copcsr;
1971
1972                 case froundl_op:
1973                 case ftruncl_op:
1974                 case fceill_op:
1975                 case ffloorl_op:
1976                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1977                                 return SIGILL;
1978
1979                         oldrm = ieee754_csr.rm;
1980                         SPFROMREG(fs, MIPSInst_FS(ir));
1981                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1982                         rv.l = ieee754sp_tlong(fs);
1983                         ieee754_csr.rm = oldrm;
1984                         rfmt = l_fmt;
1985                         goto copcsr;
1986
1987                 default:
1988                         if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1989                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1990                                 union ieee754sp fs, ft;
1991
1992                                 SPFROMREG(fs, MIPSInst_FS(ir));
1993                                 SPFROMREG(ft, MIPSInst_FT(ir));
1994                                 rv.w = ieee754sp_cmp(fs, ft,
1995                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1996                                 rfmt = -1;
1997                                 if ((cmpop & 0x8) && ieee754_cxtest
1998                                         (IEEE754_INVALID_OPERATION))
1999                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2000                                 else
2001                                         goto copcsr;
2002
2003                         } else
2004                                 return SIGILL;
2005                         break;
2006                 }
2007                 break;
2008         }
2009
2010         case d_fmt: {
2011                 union ieee754dp fd, fs, ft;
2012                 union {
2013                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2014                         union ieee754dp(*u) (union ieee754dp);
2015                 } handler;
2016
2017                 switch (MIPSInst_FUNC(ir)) {
2018                         /* binary ops */
2019                 case fadd_op:
2020                         handler.b = ieee754dp_add;
2021                         goto dcopbop;
2022                 case fsub_op:
2023                         handler.b = ieee754dp_sub;
2024                         goto dcopbop;
2025                 case fmul_op:
2026                         handler.b = ieee754dp_mul;
2027                         goto dcopbop;
2028                 case fdiv_op:
2029                         handler.b = ieee754dp_div;
2030                         goto dcopbop;
2031
2032                         /* unary  ops */
2033                 case fsqrt_op:
2034                         if (!cpu_has_mips_2_3_4_5_r)
2035                                 return SIGILL;
2036
2037                         handler.u = ieee754dp_sqrt;
2038                         goto dcopuop;
2039                 /*
2040                  * Note that on some MIPS IV implementations such as the
2041                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
2042                  * achieve full IEEE-754 accuracy - however this emulator does.
2043                  */
2044                 case frsqrt_op:
2045                         if (!cpu_has_mips_4_5_64_r2_r6)
2046                                 return SIGILL;
2047
2048                         handler.u = fpemu_dp_rsqrt;
2049                         goto dcopuop;
2050                 case frecip_op:
2051                         if (!cpu_has_mips_4_5_64_r2_r6)
2052                                 return SIGILL;
2053
2054                         handler.u = fpemu_dp_recip;
2055                         goto dcopuop;
2056                 case fmovc_op:
2057                         if (!cpu_has_mips_4_5_r)
2058                                 return SIGILL;
2059
2060                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2061                         if (((ctx->fcr31 & cond) != 0) !=
2062                                 ((MIPSInst_FT(ir) & 1) != 0))
2063                                 return 0;
2064                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2065                         break;
2066                 case fmovz_op:
2067                         if (!cpu_has_mips_4_5_r)
2068                                 return SIGILL;
2069
2070                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
2071                                 return 0;
2072                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2073                         break;
2074                 case fmovn_op:
2075                         if (!cpu_has_mips_4_5_r)
2076                                 return SIGILL;
2077
2078                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
2079                                 return 0;
2080                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2081                         break;
2082
2083                 case fseleqz_op:
2084                         if (!cpu_has_mips_r6)
2085                                 return SIGILL;
2086
2087                         DPFROMREG(rv.d, MIPSInst_FT(ir));
2088                         if (rv.l & 0x1)
2089                                 rv.l = 0;
2090                         else
2091                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
2092                         break;
2093
2094                 case fselnez_op:
2095                         if (!cpu_has_mips_r6)
2096                                 return SIGILL;
2097
2098                         DPFROMREG(rv.d, MIPSInst_FT(ir));
2099                         if (rv.l & 0x1)
2100                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
2101                         else
2102                                 rv.l = 0;
2103                         break;
2104
2105                 case fmaddf_op: {
2106                         union ieee754dp ft, fs, fd;
2107
2108                         if (!cpu_has_mips_r6)
2109                                 return SIGILL;
2110
2111                         DPFROMREG(ft, MIPSInst_FT(ir));
2112                         DPFROMREG(fs, MIPSInst_FS(ir));
2113                         DPFROMREG(fd, MIPSInst_FD(ir));
2114                         rv.d = ieee754dp_maddf(fd, fs, ft);
2115                         break;
2116                 }
2117
2118                 case fmsubf_op: {
2119                         union ieee754dp ft, fs, fd;
2120
2121                         if (!cpu_has_mips_r6)
2122                                 return SIGILL;
2123
2124                         DPFROMREG(ft, MIPSInst_FT(ir));
2125                         DPFROMREG(fs, MIPSInst_FS(ir));
2126                         DPFROMREG(fd, MIPSInst_FD(ir));
2127                         rv.d = ieee754dp_msubf(fd, fs, ft);
2128                         break;
2129                 }
2130
2131                 case frint_op: {
2132                         union ieee754dp fs;
2133
2134                         if (!cpu_has_mips_r6)
2135                                 return SIGILL;
2136
2137                         DPFROMREG(fs, MIPSInst_FS(ir));
2138                         rv.l = ieee754dp_tlong(fs);
2139                         rv.d = ieee754dp_flong(rv.l);
2140                         goto copcsr;
2141                 }
2142
2143                 case fclass_op: {
2144                         union ieee754dp fs;
2145
2146                         if (!cpu_has_mips_r6)
2147                                 return SIGILL;
2148
2149                         DPFROMREG(fs, MIPSInst_FS(ir));
2150                         rv.w = ieee754dp_2008class(fs);
2151                         rfmt = w_fmt;
2152                         break;
2153                 }
2154
2155                 case fmin_op: {
2156                         union ieee754dp fs, ft;
2157
2158                         if (!cpu_has_mips_r6)
2159                                 return SIGILL;
2160
2161                         DPFROMREG(ft, MIPSInst_FT(ir));
2162                         DPFROMREG(fs, MIPSInst_FS(ir));
2163                         rv.d = ieee754dp_fmin(fs, ft);
2164                         break;
2165                 }
2166
2167                 case fmina_op: {
2168                         union ieee754dp fs, ft;
2169
2170                         if (!cpu_has_mips_r6)
2171                                 return SIGILL;
2172
2173                         DPFROMREG(ft, MIPSInst_FT(ir));
2174                         DPFROMREG(fs, MIPSInst_FS(ir));
2175                         rv.d = ieee754dp_fmina(fs, ft);
2176                         break;
2177                 }
2178
2179                 case fmax_op: {
2180                         union ieee754dp fs, ft;
2181
2182                         if (!cpu_has_mips_r6)
2183                                 return SIGILL;
2184
2185                         DPFROMREG(ft, MIPSInst_FT(ir));
2186                         DPFROMREG(fs, MIPSInst_FS(ir));
2187                         rv.d = ieee754dp_fmax(fs, ft);
2188                         break;
2189                 }
2190
2191                 case fmaxa_op: {
2192                         union ieee754dp fs, ft;
2193
2194                         if (!cpu_has_mips_r6)
2195                                 return SIGILL;
2196
2197                         DPFROMREG(ft, MIPSInst_FT(ir));
2198                         DPFROMREG(fs, MIPSInst_FS(ir));
2199                         rv.d = ieee754dp_fmaxa(fs, ft);
2200                         break;
2201                 }
2202
2203                 case fabs_op:
2204                         handler.u = ieee754dp_abs;
2205                         goto dcopuop;
2206
2207                 case fneg_op:
2208                         handler.u = ieee754dp_neg;
2209                         goto dcopuop;
2210
2211                 case fmov_op:
2212                         /* an easy one */
2213                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2214                         goto copcsr;
2215
2216                         /* binary op on handler */
2217 dcopbop:
2218                         DPFROMREG(fs, MIPSInst_FS(ir));
2219                         DPFROMREG(ft, MIPSInst_FT(ir));
2220
2221                         rv.d = (*handler.b) (fs, ft);
2222                         goto copcsr;
2223 dcopuop:
2224                         DPFROMREG(fs, MIPSInst_FS(ir));
2225                         rv.d = (*handler.u) (fs);
2226                         goto copcsr;
2227
2228                 /*
2229                  * unary conv ops
2230                  */
2231                 case fcvts_op:
2232                         DPFROMREG(fs, MIPSInst_FS(ir));
2233                         rv.s = ieee754sp_fdp(fs);
2234                         rfmt = s_fmt;
2235                         goto copcsr;
2236
2237                 case fcvtd_op:
2238                         return SIGILL;  /* not defined */
2239
2240                 case fcvtw_op:
2241                         DPFROMREG(fs, MIPSInst_FS(ir));
2242                         rv.w = ieee754dp_tint(fs);      /* wrong */
2243                         rfmt = w_fmt;
2244                         goto copcsr;
2245
2246                 case fround_op:
2247                 case ftrunc_op:
2248                 case fceil_op:
2249                 case ffloor_op:
2250                         if (!cpu_has_mips_2_3_4_5_r)
2251                                 return SIGILL;
2252
2253                         oldrm = ieee754_csr.rm;
2254                         DPFROMREG(fs, MIPSInst_FS(ir));
2255                         ieee754_csr.rm = MIPSInst_FUNC(ir);
2256                         rv.w = ieee754dp_tint(fs);
2257                         ieee754_csr.rm = oldrm;
2258                         rfmt = w_fmt;
2259                         goto copcsr;
2260
2261                 case fsel_op:
2262                         if (!cpu_has_mips_r6)
2263                                 return SIGILL;
2264
2265                         DPFROMREG(fd, MIPSInst_FD(ir));
2266                         if (fd.bits & 0x1)
2267                                 DPFROMREG(rv.d, MIPSInst_FT(ir));
2268                         else
2269                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
2270                         break;
2271
2272                 case fcvtl_op:
2273                         if (!cpu_has_mips_3_4_5_64_r2_r6)
2274                                 return SIGILL;
2275
2276                         DPFROMREG(fs, MIPSInst_FS(ir));
2277                         rv.l = ieee754dp_tlong(fs);
2278                         rfmt = l_fmt;
2279                         goto copcsr;
2280
2281                 case froundl_op:
2282                 case ftruncl_op:
2283                 case fceill_op:
2284                 case ffloorl_op:
2285                         if (!cpu_has_mips_3_4_5_64_r2_r6)
2286                                 return SIGILL;
2287
2288                         oldrm = ieee754_csr.rm;
2289                         DPFROMREG(fs, MIPSInst_FS(ir));
2290                         ieee754_csr.rm = MIPSInst_FUNC(ir);
2291                         rv.l = ieee754dp_tlong(fs);
2292                         ieee754_csr.rm = oldrm;
2293                         rfmt = l_fmt;
2294                         goto copcsr;
2295
2296                 default:
2297                         if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2298                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2299                                 union ieee754dp fs, ft;
2300
2301                                 DPFROMREG(fs, MIPSInst_FS(ir));
2302                                 DPFROMREG(ft, MIPSInst_FT(ir));
2303                                 rv.w = ieee754dp_cmp(fs, ft,
2304                                         cmptab[cmpop & 0x7], cmpop & 0x8);
2305                                 rfmt = -1;
2306                                 if ((cmpop & 0x8)
2307                                         &&
2308                                         ieee754_cxtest
2309                                         (IEEE754_INVALID_OPERATION))
2310                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2311                                 else
2312                                         goto copcsr;
2313
2314                         }
2315                         else {
2316                                 return SIGILL;
2317                         }
2318                         break;
2319                 }
2320                 break;
2321         }
2322
2323         case w_fmt: {
2324                 union ieee754dp fs;
2325
2326                 switch (MIPSInst_FUNC(ir)) {
2327                 case fcvts_op:
2328                         /* convert word to single precision real */
2329                         SPFROMREG(fs, MIPSInst_FS(ir));
2330                         rv.s = ieee754sp_fint(fs.bits);
2331                         rfmt = s_fmt;
2332                         goto copcsr;
2333                 case fcvtd_op:
2334                         /* convert word to double precision real */
2335                         SPFROMREG(fs, MIPSInst_FS(ir));
2336                         rv.d = ieee754dp_fint(fs.bits);
2337                         rfmt = d_fmt;
2338                         goto copcsr;
2339                 default: {
2340                         /* Emulating the new CMP.condn.fmt R6 instruction */
2341 #define CMPOP_MASK      0x7
2342 #define SIGN_BIT        (0x1 << 3)
2343 #define PREDICATE_BIT   (0x1 << 4)
2344
2345                         int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2346                         int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2347                         union ieee754sp fs, ft;
2348
2349                         /* This is an R6 only instruction */
2350                         if (!cpu_has_mips_r6 ||
2351                             (MIPSInst_FUNC(ir) & 0x20))
2352                                 return SIGILL;
2353
2354                         /* fmt is w_fmt for single precision so fix it */
2355                         rfmt = s_fmt;
2356                         /* default to false */
2357                         rv.w = 0;
2358
2359                         /* CMP.condn.S */
2360                         SPFROMREG(fs, MIPSInst_FS(ir));
2361                         SPFROMREG(ft, MIPSInst_FT(ir));
2362
2363                         /* positive predicates */
2364                         if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2365                                 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2366                                                   sig))
2367                                     rv.w = -1; /* true, all 1s */
2368                                 if ((sig) &&
2369                                     ieee754_cxtest(IEEE754_INVALID_OPERATION))
2370                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2371                                 else
2372                                         goto copcsr;
2373                         } else {
2374                                 /* negative predicates */
2375                                 switch (cmpop) {
2376                                 case 1:
2377                                 case 2:
2378                                 case 3:
2379                                         if (ieee754sp_cmp(fs, ft,
2380                                                           negative_cmptab[cmpop],
2381                                                           sig))
2382                                                 rv.w = -1; /* true, all 1s */
2383                                         if (sig &&
2384                                             ieee754_cxtest(IEEE754_INVALID_OPERATION))
2385                                                 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2386                                         else
2387                                                 goto copcsr;
2388                                         break;
2389                                 default:
2390                                         /* Reserved R6 ops */
2391                                         pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2392                                         return SIGILL;
2393                                 }
2394                         }
2395                         break;
2396                         }
2397                 }
2398         }
2399
2400         case l_fmt:
2401
2402                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2403                         return SIGILL;
2404
2405                 DIFROMREG(bits, MIPSInst_FS(ir));
2406
2407                 switch (MIPSInst_FUNC(ir)) {
2408                 case fcvts_op:
2409                         /* convert long to single precision real */
2410                         rv.s = ieee754sp_flong(bits);
2411                         rfmt = s_fmt;
2412                         goto copcsr;
2413                 case fcvtd_op:
2414                         /* convert long to double precision real */
2415                         rv.d = ieee754dp_flong(bits);
2416                         rfmt = d_fmt;
2417                         goto copcsr;
2418                 default: {
2419                         /* Emulating the new CMP.condn.fmt R6 instruction */
2420                         int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2421                         int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2422                         union ieee754dp fs, ft;
2423
2424                         if (!cpu_has_mips_r6 ||
2425                             (MIPSInst_FUNC(ir) & 0x20))
2426                                 return SIGILL;
2427
2428                         /* fmt is l_fmt for double precision so fix it */
2429                         rfmt = d_fmt;
2430                         /* default to false */
2431                         rv.l = 0;
2432
2433                         /* CMP.condn.D */
2434                         DPFROMREG(fs, MIPSInst_FS(ir));
2435                         DPFROMREG(ft, MIPSInst_FT(ir));
2436
2437                         /* positive predicates */
2438                         if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2439                                 if (ieee754dp_cmp(fs, ft,
2440                                                   cmptab[cmpop], sig))
2441                                     rv.l = -1LL; /* true, all 1s */
2442                                 if (sig &&
2443                                     ieee754_cxtest(IEEE754_INVALID_OPERATION))
2444                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2445                                 else
2446                                         goto copcsr;
2447                         } else {
2448                                 /* negative predicates */
2449                                 switch (cmpop) {
2450                                 case 1:
2451                                 case 2:
2452                                 case 3:
2453                                         if (ieee754dp_cmp(fs, ft,
2454                                                           negative_cmptab[cmpop],
2455                                                           sig))
2456                                                 rv.l = -1LL; /* true, all 1s */
2457                                         if (sig &&
2458                                             ieee754_cxtest(IEEE754_INVALID_OPERATION))
2459                                                 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2460                                         else
2461                                                 goto copcsr;
2462                                         break;
2463                                 default:
2464                                         /* Reserved R6 ops */
2465                                         pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2466                                         return SIGILL;
2467                                 }
2468                         }
2469                         break;
2470                         }
2471                 }
2472         default:
2473                 return SIGILL;
2474         }
2475
2476         /*
2477          * Update the fpu CSR register for this operation.
2478          * If an exception is required, generate a tidy SIGFPE exception,
2479          * without updating the result register.
2480          * Note: cause exception bits do not accumulate, they are rewritten
2481          * for each op; only the flag/sticky bits accumulate.
2482          */
2483         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2484         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2485                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2486                 return SIGFPE;
2487         }
2488
2489         /*
2490          * Now we can safely write the result back to the register file.
2491          */
2492         switch (rfmt) {
2493         case -1:
2494
2495                 if (cpu_has_mips_4_5_r)
2496                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2497                 else
2498                         cbit = FPU_CSR_COND;
2499                 if (rv.w)
2500                         ctx->fcr31 |= cbit;
2501                 else
2502                         ctx->fcr31 &= ~cbit;
2503                 break;
2504
2505         case d_fmt:
2506                 DPTOREG(rv.d, MIPSInst_FD(ir));
2507                 break;
2508         case s_fmt:
2509                 SPTOREG(rv.s, MIPSInst_FD(ir));
2510                 break;
2511         case w_fmt:
2512                 SITOREG(rv.w, MIPSInst_FD(ir));
2513                 break;
2514         case l_fmt:
2515                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2516                         return SIGILL;
2517
2518                 DITOREG(rv.l, MIPSInst_FD(ir));
2519                 break;
2520         default:
2521                 return SIGILL;
2522         }
2523
2524         return 0;
2525 }
2526
2527 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2528         int has_fpu, void *__user *fault_addr)
2529 {
2530         unsigned long oldepc, prevepc;
2531         struct mm_decoded_insn dec_insn;
2532         u16 instr[4];
2533         u16 *instr_ptr;
2534         int sig = 0;
2535
2536         oldepc = xcp->cp0_epc;
2537         do {
2538                 prevepc = xcp->cp0_epc;
2539
2540                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2541                         /*
2542                          * Get next 2 microMIPS instructions and convert them
2543                          * into 32-bit instructions.
2544                          */
2545                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2546                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2547                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2548                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2549                                 MIPS_FPU_EMU_INC_STATS(errors);
2550                                 return SIGBUS;
2551                         }
2552                         instr_ptr = instr;
2553
2554                         /* Get first instruction. */
2555                         if (mm_insn_16bit(*instr_ptr)) {
2556                                 /* Duplicate the half-word. */
2557                                 dec_insn.insn = (*instr_ptr << 16) |
2558                                         (*instr_ptr);
2559                                 /* 16-bit instruction. */
2560                                 dec_insn.pc_inc = 2;
2561                                 instr_ptr += 1;
2562                         } else {
2563                                 dec_insn.insn = (*instr_ptr << 16) |
2564                                         *(instr_ptr+1);
2565                                 /* 32-bit instruction. */
2566                                 dec_insn.pc_inc = 4;
2567                                 instr_ptr += 2;
2568                         }
2569                         /* Get second instruction. */
2570                         if (mm_insn_16bit(*instr_ptr)) {
2571                                 /* Duplicate the half-word. */
2572                                 dec_insn.next_insn = (*instr_ptr << 16) |
2573                                         (*instr_ptr);
2574                                 /* 16-bit instruction. */
2575                                 dec_insn.next_pc_inc = 2;
2576                         } else {
2577                                 dec_insn.next_insn = (*instr_ptr << 16) |
2578                                         *(instr_ptr+1);
2579                                 /* 32-bit instruction. */
2580                                 dec_insn.next_pc_inc = 4;
2581                         }
2582                         dec_insn.micro_mips_mode = 1;
2583                 } else {
2584                         if ((get_user(dec_insn.insn,
2585                             (mips_instruction __user *) xcp->cp0_epc)) ||
2586                             (get_user(dec_insn.next_insn,
2587                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2588                                 MIPS_FPU_EMU_INC_STATS(errors);
2589                                 return SIGBUS;
2590                         }
2591                         dec_insn.pc_inc = 4;
2592                         dec_insn.next_pc_inc = 4;
2593                         dec_insn.micro_mips_mode = 0;
2594                 }
2595
2596                 if ((dec_insn.insn == 0) ||
2597                    ((dec_insn.pc_inc == 2) &&
2598                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2599                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2600                 else {
2601                         /*
2602                          * The 'ieee754_csr' is an alias of ctx->fcr31.
2603                          * No need to copy ctx->fcr31 to ieee754_csr.
2604                          */
2605                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2606                 }
2607
2608                 if (has_fpu)
2609                         break;
2610                 if (sig)
2611                         break;
2612
2613                 cond_resched();
2614         } while (xcp->cp0_epc > prevepc);
2615
2616         /* SIGILL indicates a non-fpu instruction */
2617         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2618                 /* but if EPC has advanced, then ignore it */
2619                 sig = 0;
2620
2621         return sig;
2622 }