arch/mips/lantiq/xway/sysctrl.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
   7  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
   8  */
   9
  10 #include <linux/ioport.h>
  11 #include <linux/export.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/of.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/of_address.h>
  17
  18 #include <lantiq_soc.h>
  19
  20 #include "../clk.h"
  21 #include "../prom.h"
  22
  23 /* clock control register for legacy */
  24 #define CGU_IFCCR       0x0018
  25 #define CGU_IFCCR_VR9   0x0024
  26 /* system clock register for legacy */
  27 #define CGU_SYS         0x0010
  28 /* pci control register */
  29 #define CGU_PCICR       0x0034
  30 #define CGU_PCICR_VR9   0x0038
  31 /* ephy configuration register */
  32 #define CGU_EPHY        0x10
  33
  34 /* Legacy PMU register for ar9, ase, danube */
  35 /* power control register */
  36 #define PMU_PWDCR       0x1C
  37 /* power status register */
  38 #define PMU_PWDSR       0x20
  39 /* power control register */
  40 #define PMU_PWDCR1      0x24
  41 /* power status register */
  42 #define PMU_PWDSR1      0x28
  43 /* power control register */
  44 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
  45 /* power status register */
  46 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
  47
  48
  49 /* PMU register for ar10 and grx390 */
  50
  51 /* First register set */
  52 #define PMU_CLK_SR      0x20 /* status */
  53 #define PMU_CLK_CR_A    0x24 /* Enable */
  54 #define PMU_CLK_CR_B    0x28 /* Disable */
  55 /* Second register set */
  56 #define PMU_CLK_SR1     0x30 /* status */
  57 #define PMU_CLK_CR1_A   0x34 /* Enable */
  58 #define PMU_CLK_CR1_B   0x38 /* Disable */
  59 /* Third register set */
  60 #define PMU_ANA_SR      0x40 /* status */
  61 #define PMU_ANA_CR_A    0x44 /* Enable */
  62 #define PMU_ANA_CR_B    0x48 /* Disable */
  63
  64 /* Status */
  65 static u32 pmu_clk_sr[] = {
  66         PMU_CLK_SR,
  67         PMU_CLK_SR1,
  68         PMU_ANA_SR,
  69 };
  70
  71 /* Enable */
  72 static u32 pmu_clk_cr_a[] = {
  73         PMU_CLK_CR_A,
  74         PMU_CLK_CR1_A,
  75         PMU_ANA_CR_A,
  76 };
  77
  78 /* Disable */
  79 static u32 pmu_clk_cr_b[] = {
  80         PMU_CLK_CR_B,
  81         PMU_CLK_CR1_B,
  82         PMU_ANA_CR_B,
  83 };
  84
  85 #define PWDCR_EN_XRX(x)         (pmu_clk_cr_a[(x)])
  86 #define PWDCR_DIS_XRX(x)        (pmu_clk_cr_b[(x)])
  87 #define PWDSR_XRX(x)            (pmu_clk_sr[(x)])
  88
  89 /* clock gates that we can en/disable */
  90 #define PMU_USB0_P      BIT(0)
  91 #define PMU_ASE_SDIO    BIT(2) /* ASE special */
  92 #define PMU_PCI         BIT(4)
  93 #define PMU_DMA         BIT(5)
  94 #define PMU_USB0        BIT(6)
  95 #define PMU_ASC0        BIT(7)
  96 #define PMU_EPHY        BIT(7)  /* ase */
  97 #define PMU_USIF        BIT(7) /* from vr9 until grx390 */
  98 #define PMU_SPI         BIT(8)
  99 #define PMU_DFE         BIT(9)
 100 #define PMU_EBU         BIT(10)
 101 #define PMU_STP         BIT(11)
 102 #define PMU_GPT         BIT(12)
 103 #define PMU_AHBS        BIT(13) /* vr9 */
 104 #define PMU_FPI         BIT(14)
 105 #define PMU_AHBM        BIT(15)
 106 #define PMU_SDIO        BIT(16) /* danube, ar9, vr9 */
 107 #define PMU_ASC1        BIT(17)
 108 #define PMU_PPE_QSB     BIT(18)
 109 #define PMU_PPE_SLL01   BIT(19)
 110 #define PMU_DEU         BIT(20)
 111 #define PMU_PPE_TC      BIT(21)
 112 #define PMU_PPE_EMA     BIT(22)
 113 #define PMU_PPE_DPLUM   BIT(23)
 114 #define PMU_PPE_DP      BIT(23)
 115 #define PMU_PPE_DPLUS   BIT(24)
 116 #define PMU_USB1_P      BIT(26)
 117 #define PMU_USB1        BIT(27)
 118 #define PMU_SWITCH      BIT(28)
 119 #define PMU_PPE_TOP     BIT(29)
 120 #define PMU_GPHY        BIT(30)
 121 #define PMU_PCIE_CLK    BIT(31)
 122
 123 #define PMU1_PCIE_PHY   BIT(0)  /* vr9-specific,moved in ar10/grx390 */
 124 #define PMU1_PCIE_CTL   BIT(1)
 125 #define PMU1_PCIE_PDI   BIT(4)
 126 #define PMU1_PCIE_MSI   BIT(5)
 127 #define PMU1_CKE        BIT(6)
 128 #define PMU1_PCIE1_CTL  BIT(17)
 129 #define PMU1_PCIE1_PDI  BIT(20)
 130 #define PMU1_PCIE1_MSI  BIT(21)
 131 #define PMU1_PCIE2_CTL  BIT(25)
 132 #define PMU1_PCIE2_PDI  BIT(26)
 133 #define PMU1_PCIE2_MSI  BIT(27)
 134
 135 #define PMU_ANALOG_USB0_P       BIT(0)
 136 #define PMU_ANALOG_USB1_P       BIT(1)
 137 #define PMU_ANALOG_PCIE0_P      BIT(8)
 138 #define PMU_ANALOG_PCIE1_P      BIT(9)
 139 #define PMU_ANALOG_PCIE2_P      BIT(10)
 140 #define PMU_ANALOG_DSL_AFE      BIT(16)
 141 #define PMU_ANALOG_DCDC_2V5     BIT(17)
 142 #define PMU_ANALOG_DCDC_1VX     BIT(18)
 143 #define PMU_ANALOG_DCDC_1V0     BIT(19)
 144
 145 #define pmu_w32(x, y)   ltq_w32((x), pmu_membase + (y))
 146 #define pmu_r32(x)      ltq_r32(pmu_membase + (x))
 147
 148 #define XBAR_ALWAYS_LAST        0x430
 149 #define XBAR_FPI_BURST_EN       BIT(1)
 150 #define XBAR_AHB_BURST_EN       BIT(2)
 151
 152 #define xbar_w32(x, y)  ltq_w32((x), ltq_xbar_membase + (y))
 153 #define xbar_r32(x)     ltq_r32(ltq_xbar_membase + (x))
 154
 155 static void __iomem *pmu_membase;
 156 static void __iomem *ltq_xbar_membase;
 157 void __iomem *ltq_cgu_membase;
 158 void __iomem *ltq_ebu_membase;
 159
 160 static u32 ifccr = CGU_IFCCR;
 161 static u32 pcicr = CGU_PCICR;
 162
 163 static DEFINE_SPINLOCK(g_pmu_lock);
 164
 165 /* legacy function kept alive to ease clkdev transition */
 166 void ltq_pmu_enable(unsigned int module)
 167 {
 168         int retry = 1000000;
 169
 170         spin_lock(&g_pmu_lock);
 171         pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
 172         do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
 173         spin_unlock(&g_pmu_lock);
 174
 175         if (!retry)
 176                 panic("activating PMU module failed!");
 177 }
 178 EXPORT_SYMBOL(ltq_pmu_enable);
 179
 180 /* legacy function kept alive to ease clkdev transition */
 181 void ltq_pmu_disable(unsigned int module)
 182 {
 183         int retry = 1000000;
 184
 185         spin_lock(&g_pmu_lock);
 186         pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
 187         do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
 188         spin_unlock(&g_pmu_lock);
 189
 190         if (!retry)
 191                 pr_warn("deactivating PMU module failed!");
 192 }
 193 EXPORT_SYMBOL(ltq_pmu_disable);
 194
 195 /* enable a hw clock */
 196 static int cgu_enable(struct clk *clk)
 197 {
 198         ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
 199         return 0;
 200 }
 201
 202 /* disable a hw clock */
 203 static void cgu_disable(struct clk *clk)
 204 {
 205         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
 206 }
 207
 208 /* enable a clock gate */
 209 static int pmu_enable(struct clk *clk)
 210 {
 211         int retry = 1000000;
 212
 213         if (of_machine_is_compatible("lantiq,ar10")
 214             || of_machine_is_compatible("lantiq,grx390")) {
 215                 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
 216                 do {} while (--retry &&
 217                              (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
 218
 219         } else {
 220                 spin_lock(&g_pmu_lock);
 221                 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
 222                                 PWDCR(clk->module));
 223                 do {} while (--retry &&
 224                              (pmu_r32(PWDSR(clk->module)) & clk->bits));
 225                 spin_unlock(&g_pmu_lock);
 226         }
 227
 228         if (!retry)
 229                 panic("activating PMU module failed!");
 230
 231         return 0;
 232 }
 233
 234 /* disable a clock gate */
 235 static void pmu_disable(struct clk *clk)
 236 {
 237         int retry = 1000000;
 238
 239         if (of_machine_is_compatible("lantiq,ar10")
 240             || of_machine_is_compatible("lantiq,grx390")) {
 241                 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
 242                 do {} while (--retry &&
 243                              (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
 244         } else {
 245                 spin_lock(&g_pmu_lock);
 246                 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
 247                                 PWDCR(clk->module));
 248                 do {} while (--retry &&
 249                              (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
 250                 spin_unlock(&g_pmu_lock);
 251         }
 252
 253         if (!retry)
 254                 pr_warn("deactivating PMU module failed!");
 255 }
 256
 257 /* the pci enable helper */
 258 static int pci_enable(struct clk *clk)
 259 {
 260         unsigned int val = ltq_cgu_r32(ifccr);
 261         /* set bus clock speed */
 262         if (of_machine_is_compatible("lantiq,ar9") ||
 263                         of_machine_is_compatible("lantiq,vr9")) {
 264                 val &= ~0x1f00000;
 265                 if (clk->rate == CLOCK_33M)
 266                         val |= 0xe00000;
 267                 else
 268                         val |= 0x700000; /* 62.5M */
 269         } else {
 270                 val &= ~0xf00000;
 271                 if (clk->rate == CLOCK_33M)
 272                         val |= 0x800000;
 273                 else
 274                         val |= 0x400000; /* 62.5M */
 275         }
 276         ltq_cgu_w32(val, ifccr);
 277         pmu_enable(clk);
 278         return 0;
 279 }
 280
 281 /* enable the external clock as a source */
 282 static int pci_ext_enable(struct clk *clk)
 283 {
 284         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
 285         ltq_cgu_w32((1 << 30), pcicr);
 286         return 0;
 287 }
 288
 289 /* disable the external clock as a source */
 290 static void pci_ext_disable(struct clk *clk)
 291 {
 292         ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
 293         ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 294 }
 295
 296 static void xbar_fpi_burst_disable(void)
 297 {
 298         u32 reg;
 299
 300         /* bit 1 as 1 --burst; bit 1 as 0 -- single */
 301         reg = xbar_r32(XBAR_ALWAYS_LAST);
 302         reg &= ~XBAR_FPI_BURST_EN;
 303         xbar_w32(reg, XBAR_ALWAYS_LAST);
 304 }
 305
 306 /* enable a clockout source */
 307 static int clkout_enable(struct clk *clk)
 308 {
 309         int i;
 310
 311         /* get the correct rate */
 312         for (i = 0; i < 4; i++) {
 313                 if (clk->rates[i] == clk->rate) {
 314                         int shift = 14 - (2 * clk->module);
 315                         int enable = 7 - clk->module;
 316                         unsigned int val = ltq_cgu_r32(ifccr);
 317
 318                         val &= ~(3 << shift);
 319                         val |= i << shift;
 320                         val |= enable;
 321                         ltq_cgu_w32(val, ifccr);
 322                         return 0;
 323                 }
 324         }
 325         return -1;
 326 }
 327
 328 /* manage the clock gates via PMU */
 329 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
 330                            unsigned int module, unsigned int bits)
 331 {
 332         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 333
 334         clk->cl.dev_id = dev;
 335         clk->cl.con_id = con;
 336         clk->cl.clk = clk;
 337         clk->enable = pmu_enable;
 338         clk->disable = pmu_disable;
 339         clk->module = module;
 340         clk->bits = bits;
 341         if (deactivate) {
 342                 /*
 343                  * Disable it during the initialization. Module should enable
 344                  * when used
 345                  */
 346                 pmu_disable(clk);
 347         }
 348         clkdev_add(&clk->cl);
 349 }
 350
 351 /* manage the clock generator */
 352 static void clkdev_add_cgu(const char *dev, const char *con,
 353                                         unsigned int bits)
 354 {
 355         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 356
 357         clk->cl.dev_id = dev;
 358         clk->cl.con_id = con;
 359         clk->cl.clk = clk;
 360         clk->enable = cgu_enable;
 361         clk->disable = cgu_disable;
 362         clk->bits = bits;
 363         clkdev_add(&clk->cl);
 364 }
 365
 366 /* pci needs its own enable function as the setup is a bit more complex */
 367 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
 368
 369 static void clkdev_add_pci(void)
 370 {
 371         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 372         struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
 373
 374         /* main pci clock */
 375         clk->cl.dev_id = "17000000.pci";
 376         clk->cl.con_id = NULL;
 377         clk->cl.clk = clk;
 378         clk->rate = CLOCK_33M;
 379         clk->rates = valid_pci_rates;
 380         clk->enable = pci_enable;
 381         clk->disable = pmu_disable;
 382         clk->module = 0;
 383         clk->bits = PMU_PCI;
 384         clkdev_add(&clk->cl);
 385
 386         /* use internal/external bus clock */
 387         clk_ext->cl.dev_id = "17000000.pci";
 388         clk_ext->cl.con_id = "external";
 389         clk_ext->cl.clk = clk_ext;
 390         clk_ext->enable = pci_ext_enable;
 391         clk_ext->disable = pci_ext_disable;
 392         clkdev_add(&clk_ext->cl);
 393 }
 394
 395 /* xway socs can generate clocks on gpio pins */
 396 static unsigned long valid_clkout_rates[4][5] = {
 397         {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
 398         {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
 399         {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
 400         {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
 401 };
 402
 403 static void clkdev_add_clkout(void)
 404 {
 405         int i;
 406
 407         for (i = 0; i < 4; i++) {
 408                 struct clk *clk;
 409                 char *name;
 410
 411                 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
 412                 sprintf(name, "clkout%d", i);
 413
 414                 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 415                 clk->cl.dev_id = "1f103000.cgu";
 416                 clk->cl.con_id = name;
 417                 clk->cl.clk = clk;
 418                 clk->rate = 0;
 419                 clk->rates = valid_clkout_rates[i];
 420                 clk->enable = clkout_enable;
 421                 clk->module = i;
 422                 clkdev_add(&clk->cl);
 423         }
 424 }
 425
 426 /* bring up all register ranges that we need for basic system control */
 427 void __init ltq_soc_init(void)
 428 {
 429         struct resource res_pmu, res_cgu, res_ebu;
 430         struct device_node *np_pmu =
 431                         of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
 432         struct device_node *np_cgu =
 433                         of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
 434         struct device_node *np_ebu =
 435                         of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
 436
 437         /* check if all the core register ranges are available */
 438         if (!np_pmu || !np_cgu || !np_ebu)
 439                 panic("Failed to load core nodes from devicetree");
 440
 441         if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
 442                         of_address_to_resource(np_cgu, 0, &res_cgu) ||
 443                         of_address_to_resource(np_ebu, 0, &res_ebu))
 444                 panic("Failed to get core resources");
 445
 446         if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
 447                                 res_pmu.name) ||
 448                 !request_mem_region(res_cgu.start, resource_size(&res_cgu),
 449                                 res_cgu.name) ||
 450                 !request_mem_region(res_ebu.start, resource_size(&res_ebu),
 451                                 res_ebu.name))
 452                 pr_err("Failed to request core resources");
 453
 454         pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
 455         ltq_cgu_membase = ioremap_nocache(res_cgu.start,
 456                                                 resource_size(&res_cgu));
 457         ltq_ebu_membase = ioremap_nocache(res_ebu.start,
 458                                                 resource_size(&res_ebu));
 459         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
 460                 panic("Failed to remap core resources");
 461
 462         if (of_machine_is_compatible("lantiq,vr9")) {
 463                 struct resource res_xbar;
 464                 struct device_node *np_xbar =
 465                                 of_find_compatible_node(NULL, NULL,
 466                                                         "lantiq,xbar-xway");
 467
 468                 if (!np_xbar)
 469                         panic("Failed to load xbar nodes from devicetree");
 470                 if (of_address_to_resource(np_xbar, 0, &res_xbar))
 471                         panic("Failed to get xbar resources");
 472                 if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
 473                         res_xbar.name))
 474                         panic("Failed to get xbar resources");
 475
 476                 ltq_xbar_membase = ioremap_nocache(res_xbar.start,
 477                                                    resource_size(&res_xbar));
 478                 if (!ltq_xbar_membase)
 479                         panic("Failed to remap xbar resources");
 480         }
 481
 482         /* make sure to unprotect the memory region where flash is located */
 483         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 484
 485         /* add our generic xway clocks */
 486         clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
 487         clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
 488         clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
 489         clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
 490         clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
 491         clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
 492         clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
 493         clkdev_add_clkout();
 494
 495         /* add the soc dependent clocks */
 496         if (of_machine_is_compatible("lantiq,vr9")) {
 497                 ifccr = CGU_IFCCR_VR9;
 498                 pcicr = CGU_PCICR_VR9;
 499         } else {
 500                 clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
 501         }
 502
 503         if (!of_machine_is_compatible("lantiq,ase")) {
 504                 clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
 505                 clkdev_add_pci();
 506         }
 507
 508         if (of_machine_is_compatible("lantiq,grx390") ||
 509             of_machine_is_compatible("lantiq,ar10")) {
 510                 clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
 511                 clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
 512                 /* rc 0 */
 513                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
 514                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
 515                 clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);
 516                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
 517                 /* rc 1 */
 518                 clkdev_add_pmu("19000000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
 519                 clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
 520                 clkdev_add_pmu("19000000.pcie", "pdi", 1, 1, PMU1_PCIE1_PDI);
 521                 clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
 522         }
 523
 524         if (of_machine_is_compatible("lantiq,ase")) {
 525                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 526                         clkdev_add_static(CLOCK_266M, CLOCK_133M,
 527                                                 CLOCK_133M, CLOCK_266M);
 528                 else
 529                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
 530                                                 CLOCK_133M, CLOCK_133M);
 531                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 532                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 533                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
 534                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
 535                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
 536                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
 537                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 538         } else if (of_machine_is_compatible("lantiq,grx390")) {
 539                 clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
 540                                   ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
 541                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 542                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 543                 /* rc 2 */
 544                 clkdev_add_pmu("1a800000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
 545                 clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
 546                 clkdev_add_pmu("1a800000.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
 547                 clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
 548                 clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
 549                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 550                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 551         } else if (of_machine_is_compatible("lantiq,ar10")) {
 552                 clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
 553                                   ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
 554                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 555                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 556                 clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
 557                                PMU_PPE_DP | PMU_PPE_TC);
 558                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 559                 clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
 560                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 561                 clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
 562                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 563         } else if (of_machine_is_compatible("lantiq,vr9")) {
 564                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 565                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
 566                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 567                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
 568                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 569                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
 570                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
 571                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
 572                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
 573                 clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);
 574                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
 575                 clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
 576
 577                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 578                 clkdev_add_pmu("1e108000.eth", NULL, 0, 0,
 579                                 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 580                                 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 581                                 PMU_PPE_QSB | PMU_PPE_TOP);
 582                 clkdev_add_pmu("1f203000.rcu", "gphy", 0, 0, PMU_GPHY);
 583                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 584                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 585                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 586         } else if (of_machine_is_compatible("lantiq,ar9")) {
 587                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 588                                 ltq_ar9_fpi_hz(), CLOCK_250M);
 589                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 590                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 591                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 592                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 593                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
 594                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 595                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 596                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 597                 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
 598         } else {
 599                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 600                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
 601                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 602                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 603                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 604                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 605                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 606                 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
 607         }
 608
 609         if (of_machine_is_compatible("lantiq,vr9"))
 610                 xbar_fpi_burst_disable();
 611 }