arch/mips/kernel/perf_event_mipsxx.c

   1 /*
   2  * Linux performance counter support for MIPS.
   3  *
   4  * Copyright (C) 2010 MIPS Technologies, Inc.
   5  * Copyright (C) 2011 Cavium Networks, Inc.
   6  * Author: Deng-Cheng Zhu
   7  *
   8  * This code is based on the implementation for ARM, which is in turn
   9  * based on the sparc64 perf event code and the x86 code. Performance
  10  * counter access is based on the MIPS Oprofile code. And the callchain
  11  * support references the code of MIPS stacktrace.c.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/cpumask.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/smp.h>
  21 #include <linux/kernel.h>
  22 #include <linux/perf_event.h>
  23 #include <linux/uaccess.h>
  24
  25 #include <asm/irq.h>
  26 #include <asm/irq_regs.h>
  27 #include <asm/stacktrace.h>
  28 #include <asm/time.h> /* For perf_irq */
  29
  30 #define MIPS_MAX_HWEVENTS 4
  31 #define MIPS_TCS_PER_COUNTER 2
  32 #define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1)
  33
  34 struct cpu_hw_events {
  35         /* Array of events on this cpu. */
  36         struct perf_event       *events[MIPS_MAX_HWEVENTS];
  37
  38         /*
  39          * Set the bit (indexed by the counter number) when the counter
  40          * is used for an event.
  41          */
  42         unsigned long           used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
  43
  44         /*
  45          * Software copy of the control register for each performance counter.
  46          * MIPS CPUs vary in performance counters. They use this differently,
  47          * and even may not use it.
  48          */
  49         unsigned int            saved_ctrl[MIPS_MAX_HWEVENTS];
  50 };
  51 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  52         .saved_ctrl = {0},
  53 };
  54
  55 /* The description of MIPS performance events. */
  56 struct mips_perf_event {
  57         unsigned int event_id;
  58         /*
  59          * MIPS performance counters are indexed starting from 0.
  60          * CNTR_EVEN indicates the indexes of the counters to be used are
  61          * even numbers.
  62          */
  63         unsigned int cntr_mask;
  64         #define CNTR_EVEN       0x55555555
  65         #define CNTR_ODD        0xaaaaaaaa
  66         #define CNTR_ALL        0xffffffff
  67 #ifdef CONFIG_MIPS_MT_SMP
  68         enum {
  69                 T  = 0,
  70                 V  = 1,
  71                 P  = 2,
  72         } range;
  73 #else
  74         #define T
  75         #define V
  76         #define P
  77 #endif
  78 };
  79
  80 static struct mips_perf_event raw_event;
  81 static DEFINE_MUTEX(raw_event_mutex);
  82
  83 #define C(x) PERF_COUNT_HW_CACHE_##x
  84
  85 struct mips_pmu {
  86         u64             max_period;
  87         u64             valid_count;
  88         u64             overflow;
  89         const char      *name;
  90         int             irq;
  91         u64             (*read_counter)(unsigned int idx);
  92         void            (*write_counter)(unsigned int idx, u64 val);
  93         const struct mips_perf_event *(*map_raw_event)(u64 config);
  94         const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
  95         const struct mips_perf_event (*cache_event_map)
  96                                 [PERF_COUNT_HW_CACHE_MAX]
  97                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  98                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  99         unsigned int    num_counters;
 100 };
 101
 102 static struct mips_pmu mipspmu;
 103
 104 #define M_PERFCTL_EVENT(event)          (((event) << MIPS_PERFCTRL_EVENT_S) & \
 105                                          MIPS_PERFCTRL_EVENT)
 106 #define M_PERFCTL_VPEID(vpe)            ((vpe)    << MIPS_PERFCTRL_VPEID_S)
 107
 108 #ifdef CONFIG_CPU_BMIPS5000
 109 #define M_PERFCTL_MT_EN(filter)         0
 110 #else /* !CONFIG_CPU_BMIPS5000 */
 111 #define M_PERFCTL_MT_EN(filter)         (filter)
 112 #endif /* CONFIG_CPU_BMIPS5000 */
 113
 114 #define    M_TC_EN_ALL                  M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_ALL)
 115 #define    M_TC_EN_VPE                  M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_VPE)
 116 #define    M_TC_EN_TC                   M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_TC)
 117
 118 #define M_PERFCTL_COUNT_EVENT_WHENEVER  (MIPS_PERFCTRL_EXL |            \
 119                                          MIPS_PERFCTRL_K |              \
 120                                          MIPS_PERFCTRL_U |              \
 121                                          MIPS_PERFCTRL_S |              \
 122                                          MIPS_PERFCTRL_IE)
 123
 124 #ifdef CONFIG_MIPS_MT_SMP
 125 #define M_PERFCTL_CONFIG_MASK           0x3fff801f
 126 #else
 127 #define M_PERFCTL_CONFIG_MASK           0x1f
 128 #endif
 129
 130
 131 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 132 static int cpu_has_mipsmt_pertccounters;
 133
 134 static DEFINE_RWLOCK(pmuint_rwlock);
 135
 136 #if defined(CONFIG_CPU_BMIPS5000)
 137 #define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
 138                          0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
 139 #else
 140 /*
 141  * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
 142  * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
 143  */
 144 #define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
 145                          0 : smp_processor_id())
 146 #endif
 147
 148 /* Copied from op_model_mipsxx.c */
 149 static unsigned int vpe_shift(void)
 150 {
 151         if (num_possible_cpus() > 1)
 152                 return 1;
 153
 154         return 0;
 155 }
 156
 157 static unsigned int counters_total_to_per_cpu(unsigned int counters)
 158 {
 159         return counters >> vpe_shift();
 160 }
 161
 162 #else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
 163 #define vpe_id()        0
 164
 165 #endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
 166
 167 static void resume_local_counters(void);
 168 static void pause_local_counters(void);
 169 static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
 170 static int mipsxx_pmu_handle_shared_irq(void);
 171
 172 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
 173 {
 174         if (vpe_id() == 1)
 175                 idx = (idx + 2) & 3;
 176         return idx;
 177 }
 178
 179 static u64 mipsxx_pmu_read_counter(unsigned int idx)
 180 {
 181         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 182
 183         switch (idx) {
 184         case 0:
 185                 /*
 186                  * The counters are unsigned, we must cast to truncate
 187                  * off the high bits.
 188                  */
 189                 return (u32)read_c0_perfcntr0();
 190         case 1:
 191                 return (u32)read_c0_perfcntr1();
 192         case 2:
 193                 return (u32)read_c0_perfcntr2();
 194         case 3:
 195                 return (u32)read_c0_perfcntr3();
 196         default:
 197                 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 198                 return 0;
 199         }
 200 }
 201
 202 static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
 203 {
 204         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 205
 206         switch (idx) {
 207         case 0:
 208                 return read_c0_perfcntr0_64();
 209         case 1:
 210                 return read_c0_perfcntr1_64();
 211         case 2:
 212                 return read_c0_perfcntr2_64();
 213         case 3:
 214                 return read_c0_perfcntr3_64();
 215         default:
 216                 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 217                 return 0;
 218         }
 219 }
 220
 221 static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
 222 {
 223         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 224
 225         switch (idx) {
 226         case 0:
 227                 write_c0_perfcntr0(val);
 228                 return;
 229         case 1:
 230                 write_c0_perfcntr1(val);
 231                 return;
 232         case 2:
 233                 write_c0_perfcntr2(val);
 234                 return;
 235         case 3:
 236                 write_c0_perfcntr3(val);
 237                 return;
 238         }
 239 }
 240
 241 static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
 242 {
 243         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 244
 245         switch (idx) {
 246         case 0:
 247                 write_c0_perfcntr0_64(val);
 248                 return;
 249         case 1:
 250                 write_c0_perfcntr1_64(val);
 251                 return;
 252         case 2:
 253                 write_c0_perfcntr2_64(val);
 254                 return;
 255         case 3:
 256                 write_c0_perfcntr3_64(val);
 257                 return;
 258         }
 259 }
 260
 261 static unsigned int mipsxx_pmu_read_control(unsigned int idx)
 262 {
 263         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 264
 265         switch (idx) {
 266         case 0:
 267                 return read_c0_perfctrl0();
 268         case 1:
 269                 return read_c0_perfctrl1();
 270         case 2:
 271                 return read_c0_perfctrl2();
 272         case 3:
 273                 return read_c0_perfctrl3();
 274         default:
 275                 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 276                 return 0;
 277         }
 278 }
 279
 280 static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
 281 {
 282         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 283
 284         switch (idx) {
 285         case 0:
 286                 write_c0_perfctrl0(val);
 287                 return;
 288         case 1:
 289                 write_c0_perfctrl1(val);
 290                 return;
 291         case 2:
 292                 write_c0_perfctrl2(val);
 293                 return;
 294         case 3:
 295                 write_c0_perfctrl3(val);
 296                 return;
 297         }
 298 }
 299
 300 static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
 301                                     struct hw_perf_event *hwc)
 302 {
 303         int i;
 304
 305         /*
 306          * We only need to care the counter mask. The range has been
 307          * checked definitely.
 308          */
 309         unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
 310
 311         for (i = mipspmu.num_counters - 1; i >= 0; i--) {
 312                 /*
 313                  * Note that some MIPS perf events can be counted by both
 314                  * even and odd counters, wheresas many other are only by
 315                  * even _or_ odd counters. This introduces an issue that
 316                  * when the former kind of event takes the counter the
 317                  * latter kind of event wants to use, then the "counter
 318                  * allocation" for the latter event will fail. In fact if
 319                  * they can be dynamically swapped, they both feel happy.
 320                  * But here we leave this issue alone for now.
 321                  */
 322                 if (test_bit(i, &cntr_mask) &&
 323                         !test_and_set_bit(i, cpuc->used_mask))
 324                         return i;
 325         }
 326
 327         return -EAGAIN;
 328 }
 329
 330 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
 331 {
 332         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 333
 334         WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 335
 336         cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
 337                 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
 338                 /* Make sure interrupt enabled. */
 339                 MIPS_PERFCTRL_IE;
 340         if (IS_ENABLED(CONFIG_CPU_BMIPS5000))
 341                 /* enable the counter for the calling thread */
 342                 cpuc->saved_ctrl[idx] |=
 343                         (1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC;
 344
 345         /*
 346          * We do not actually let the counter run. Leave it until start().
 347          */
 348 }
 349
 350 static void mipsxx_pmu_disable_event(int idx)
 351 {
 352         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 353         unsigned long flags;
 354
 355         WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 356
 357         local_irq_save(flags);
 358         cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
 359                 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
 360         mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
 361         local_irq_restore(flags);
 362 }
 363
 364 static int mipspmu_event_set_period(struct perf_event *event,
 365                                     struct hw_perf_event *hwc,
 366                                     int idx)
 367 {
 368         u64 left = local64_read(&hwc->period_left);
 369         u64 period = hwc->sample_period;
 370         int ret = 0;
 371
 372         if (unlikely((left + period) & (1ULL << 63))) {
 373                 /* left underflowed by more than period. */
 374                 left = period;
 375                 local64_set(&hwc->period_left, left);
 376                 hwc->last_period = period;
 377                 ret = 1;
 378         } else  if (unlikely((left + period) <= period)) {
 379                 /* left underflowed by less than period. */
 380                 left += period;
 381                 local64_set(&hwc->period_left, left);
 382                 hwc->last_period = period;
 383                 ret = 1;
 384         }
 385
 386         if (left > mipspmu.max_period) {
 387                 left = mipspmu.max_period;
 388                 local64_set(&hwc->period_left, left);
 389         }
 390
 391         local64_set(&hwc->prev_count, mipspmu.overflow - left);
 392
 393         mipspmu.write_counter(idx, mipspmu.overflow - left);
 394
 395         perf_event_update_userpage(event);
 396
 397         return ret;
 398 }
 399
 400 static void mipspmu_event_update(struct perf_event *event,
 401                                  struct hw_perf_event *hwc,
 402                                  int idx)
 403 {
 404         u64 prev_raw_count, new_raw_count;
 405         u64 delta;
 406
 407 again:
 408         prev_raw_count = local64_read(&hwc->prev_count);
 409         new_raw_count = mipspmu.read_counter(idx);
 410
 411         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 412                                 new_raw_count) != prev_raw_count)
 413                 goto again;
 414
 415         delta = new_raw_count - prev_raw_count;
 416
 417         local64_add(delta, &event->count);
 418         local64_sub(delta, &hwc->period_left);
 419 }
 420
 421 static void mipspmu_start(struct perf_event *event, int flags)
 422 {
 423         struct hw_perf_event *hwc = &event->hw;
 424
 425         if (flags & PERF_EF_RELOAD)
 426                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 427
 428         hwc->state = 0;
 429
 430         /* Set the period for the event. */
 431         mipspmu_event_set_period(event, hwc, hwc->idx);
 432
 433         /* Enable the event. */
 434         mipsxx_pmu_enable_event(hwc, hwc->idx);
 435 }
 436
 437 static void mipspmu_stop(struct perf_event *event, int flags)
 438 {
 439         struct hw_perf_event *hwc = &event->hw;
 440
 441         if (!(hwc->state & PERF_HES_STOPPED)) {
 442                 /* We are working on a local event. */
 443                 mipsxx_pmu_disable_event(hwc->idx);
 444                 barrier();
 445                 mipspmu_event_update(event, hwc, hwc->idx);
 446                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 447         }
 448 }
 449
 450 static int mipspmu_add(struct perf_event *event, int flags)
 451 {
 452         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 453         struct hw_perf_event *hwc = &event->hw;
 454         int idx;
 455         int err = 0;
 456
 457         perf_pmu_disable(event->pmu);
 458
 459         /* To look for a free counter for this event. */
 460         idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
 461         if (idx < 0) {
 462                 err = idx;
 463                 goto out;
 464         }
 465
 466         /*
 467          * If there is an event in the counter we are going to use then
 468          * make sure it is disabled.
 469          */
 470         event->hw.idx = idx;
 471         mipsxx_pmu_disable_event(idx);
 472         cpuc->events[idx] = event;
 473
 474         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 475         if (flags & PERF_EF_START)
 476                 mipspmu_start(event, PERF_EF_RELOAD);
 477
 478         /* Propagate our changes to the userspace mapping. */
 479         perf_event_update_userpage(event);
 480
 481 out:
 482         perf_pmu_enable(event->pmu);
 483         return err;
 484 }
 485
 486 static void mipspmu_del(struct perf_event *event, int flags)
 487 {
 488         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 489         struct hw_perf_event *hwc = &event->hw;
 490         int idx = hwc->idx;
 491
 492         WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 493
 494         mipspmu_stop(event, PERF_EF_UPDATE);
 495         cpuc->events[idx] = NULL;
 496         clear_bit(idx, cpuc->used_mask);
 497
 498         perf_event_update_userpage(event);
 499 }
 500
 501 static void mipspmu_read(struct perf_event *event)
 502 {
 503         struct hw_perf_event *hwc = &event->hw;
 504
 505         /* Don't read disabled counters! */
 506         if (hwc->idx < 0)
 507                 return;
 508
 509         mipspmu_event_update(event, hwc, hwc->idx);
 510 }
 511
 512 static void mipspmu_enable(struct pmu *pmu)
 513 {
 514 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 515         write_unlock(&pmuint_rwlock);
 516 #endif
 517         resume_local_counters();
 518 }
 519
 520 /*
 521  * MIPS performance counters can be per-TC. The control registers can
 522  * not be directly accessed across CPUs. Hence if we want to do global
 523  * control, we need cross CPU calls. on_each_cpu() can help us, but we
 524  * can not make sure this function is called with interrupts enabled. So
 525  * here we pause local counters and then grab a rwlock and leave the
 526  * counters on other CPUs alone. If any counter interrupt raises while
 527  * we own the write lock, simply pause local counters on that CPU and
 528  * spin in the handler. Also we know we won't be switched to another
 529  * CPU after pausing local counters and before grabbing the lock.
 530  */
 531 static void mipspmu_disable(struct pmu *pmu)
 532 {
 533         pause_local_counters();
 534 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 535         write_lock(&pmuint_rwlock);
 536 #endif
 537 }
 538
 539 static atomic_t active_events = ATOMIC_INIT(0);
 540 static DEFINE_MUTEX(pmu_reserve_mutex);
 541 static int (*save_perf_irq)(void);
 542
 543 static int mipspmu_get_irq(void)
 544 {
 545         int err;
 546
 547         if (mipspmu.irq >= 0) {
 548                 /* Request my own irq handler. */
 549                 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
 550                                   IRQF_PERCPU | IRQF_NOBALANCING |
 551                                   IRQF_NO_THREAD | IRQF_NO_SUSPEND |
 552                                   IRQF_SHARED,
 553                                   "mips_perf_pmu", &mipspmu);
 554                 if (err) {
 555                         pr_warn("Unable to request IRQ%d for MIPS performance counters!\n",
 556                                 mipspmu.irq);
 557                 }
 558         } else if (cp0_perfcount_irq < 0) {
 559                 /*
 560                  * We are sharing the irq number with the timer interrupt.
 561                  */
 562                 save_perf_irq = perf_irq;
 563                 perf_irq = mipsxx_pmu_handle_shared_irq;
 564                 err = 0;
 565         } else {
 566                 pr_warn("The platform hasn't properly defined its interrupt controller\n");
 567                 err = -ENOENT;
 568         }
 569
 570         return err;
 571 }
 572
 573 static void mipspmu_free_irq(void)
 574 {
 575         if (mipspmu.irq >= 0)
 576                 free_irq(mipspmu.irq, &mipspmu);
 577         else if (cp0_perfcount_irq < 0)
 578                 perf_irq = save_perf_irq;
 579 }
 580
 581 /*
 582  * mipsxx/rm9000/loongson2 have different performance counters, they have
 583  * specific low-level init routines.
 584  */
 585 static void reset_counters(void *arg);
 586 static int __hw_perf_event_init(struct perf_event *event);
 587
 588 static void hw_perf_event_destroy(struct perf_event *event)
 589 {
 590         if (atomic_dec_and_mutex_lock(&active_events,
 591                                 &pmu_reserve_mutex)) {
 592                 /*
 593                  * We must not call the destroy function with interrupts
 594                  * disabled.
 595                  */
 596                 on_each_cpu(reset_counters,
 597                         (void *)(long)mipspmu.num_counters, 1);
 598                 mipspmu_free_irq();
 599                 mutex_unlock(&pmu_reserve_mutex);
 600         }
 601 }
 602
 603 static int mipspmu_event_init(struct perf_event *event)
 604 {
 605         int err = 0;
 606
 607         /* does not support taken branch sampling */
 608         if (has_branch_stack(event))
 609                 return -EOPNOTSUPP;
 610
 611         switch (event->attr.type) {
 612         case PERF_TYPE_RAW:
 613         case PERF_TYPE_HARDWARE:
 614         case PERF_TYPE_HW_CACHE:
 615                 break;
 616
 617         default:
 618                 return -ENOENT;
 619         }
 620
 621         if ((unsigned int)event->cpu >= nr_cpumask_bits ||
 622             (event->cpu >= 0 && !cpu_online(event->cpu)))
 623                 return -ENODEV;
 624
 625         if (!atomic_inc_not_zero(&active_events)) {
 626                 mutex_lock(&pmu_reserve_mutex);
 627                 if (atomic_read(&active_events) == 0)
 628                         err = mipspmu_get_irq();
 629
 630                 if (!err)
 631                         atomic_inc(&active_events);
 632                 mutex_unlock(&pmu_reserve_mutex);
 633         }
 634
 635         if (err)
 636                 return err;
 637
 638         return __hw_perf_event_init(event);
 639 }
 640
 641 static struct pmu pmu = {
 642         .pmu_enable     = mipspmu_enable,
 643         .pmu_disable    = mipspmu_disable,
 644         .event_init     = mipspmu_event_init,
 645         .add            = mipspmu_add,
 646         .del            = mipspmu_del,
 647         .start          = mipspmu_start,
 648         .stop           = mipspmu_stop,
 649         .read           = mipspmu_read,
 650 };
 651
 652 static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
 653 {
 654 /*
 655  * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
 656  * event_id.
 657  */
 658 #ifdef CONFIG_MIPS_MT_SMP
 659         return ((unsigned int)pev->range << 24) |
 660                 (pev->cntr_mask & 0xffff00) |
 661                 (pev->event_id & 0xff);
 662 #else
 663         return (pev->cntr_mask & 0xffff00) |
 664                 (pev->event_id & 0xff);
 665 #endif
 666 }
 667
 668 static const struct mips_perf_event *mipspmu_map_general_event(int idx)
 669 {
 670
 671         if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
 672                 return ERR_PTR(-EOPNOTSUPP);
 673         return &(*mipspmu.general_event_map)[idx];
 674 }
 675
 676 static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
 677 {
 678         unsigned int cache_type, cache_op, cache_result;
 679         const struct mips_perf_event *pev;
 680
 681         cache_type = (config >> 0) & 0xff;
 682         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 683                 return ERR_PTR(-EINVAL);
 684
 685         cache_op = (config >> 8) & 0xff;
 686         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 687                 return ERR_PTR(-EINVAL);
 688
 689         cache_result = (config >> 16) & 0xff;
 690         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 691                 return ERR_PTR(-EINVAL);
 692
 693         pev = &((*mipspmu.cache_event_map)
 694                                         [cache_type]
 695                                         [cache_op]
 696                                         [cache_result]);
 697
 698         if (pev->cntr_mask == 0)
 699                 return ERR_PTR(-EOPNOTSUPP);
 700
 701         return pev;
 702
 703 }
 704
 705 static int validate_group(struct perf_event *event)
 706 {
 707         struct perf_event *sibling, *leader = event->group_leader;
 708         struct cpu_hw_events fake_cpuc;
 709
 710         memset(&fake_cpuc, 0, sizeof(fake_cpuc));
 711
 712         if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
 713                 return -EINVAL;
 714
 715         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 716                 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
 717                         return -EINVAL;
 718         }
 719
 720         if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
 721                 return -EINVAL;
 722
 723         return 0;
 724 }
 725
 726 /* This is needed by specific irq handlers in perf_event_*.c */
 727 static void handle_associated_event(struct cpu_hw_events *cpuc,
 728                                     int idx, struct perf_sample_data *data,
 729                                     struct pt_regs *regs)
 730 {
 731         struct perf_event *event = cpuc->events[idx];
 732         struct hw_perf_event *hwc = &event->hw;
 733
 734         mipspmu_event_update(event, hwc, idx);
 735         data->period = event->hw.last_period;
 736         if (!mipspmu_event_set_period(event, hwc, idx))
 737                 return;
 738
 739         if (perf_event_overflow(event, data, regs))
 740                 mipsxx_pmu_disable_event(idx);
 741 }
 742
 743
 744 static int __n_counters(void)
 745 {
 746         if (!cpu_has_perf)
 747                 return 0;
 748         if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
 749                 return 1;
 750         if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
 751                 return 2;
 752         if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
 753                 return 3;
 754
 755         return 4;
 756 }
 757
 758 static int n_counters(void)
 759 {
 760         int counters;
 761
 762         switch (current_cpu_type()) {
 763         case CPU_R10000:
 764                 counters = 2;
 765                 break;
 766
 767         case CPU_R12000:
 768         case CPU_R14000:
 769         case CPU_R16000:
 770                 counters = 4;
 771                 break;
 772
 773         default:
 774                 counters = __n_counters();
 775         }
 776
 777         return counters;
 778 }
 779
 780 static void reset_counters(void *arg)
 781 {
 782         int counters = (int)(long)arg;
 783         switch (counters) {
 784         case 4:
 785                 mipsxx_pmu_write_control(3, 0);
 786                 mipspmu.write_counter(3, 0);
 787         case 3:
 788                 mipsxx_pmu_write_control(2, 0);
 789                 mipspmu.write_counter(2, 0);
 790         case 2:
 791                 mipsxx_pmu_write_control(1, 0);
 792                 mipspmu.write_counter(1, 0);
 793         case 1:
 794                 mipsxx_pmu_write_control(0, 0);
 795                 mipspmu.write_counter(0, 0);
 796         }
 797 }
 798
 799 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
 800 static const struct mips_perf_event mipsxxcore_event_map
 801                                 [PERF_COUNT_HW_MAX] = {
 802         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 803         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 804         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
 805         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
 806 };
 807
 808 /* 74K/proAptiv core has different branch event code. */
 809 static const struct mips_perf_event mipsxxcore_event_map2
 810                                 [PERF_COUNT_HW_MAX] = {
 811         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 812         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 813         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
 814         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
 815 };
 816
 817 static const struct mips_perf_event i6400_event_map[PERF_COUNT_HW_MAX] = {
 818         [PERF_COUNT_HW_CPU_CYCLES]          = { 0x00, CNTR_EVEN | CNTR_ODD },
 819         [PERF_COUNT_HW_INSTRUCTIONS]        = { 0x01, CNTR_EVEN | CNTR_ODD },
 820         /* These only count dcache, not icache */
 821         [PERF_COUNT_HW_CACHE_REFERENCES]    = { 0x45, CNTR_EVEN | CNTR_ODD },
 822         [PERF_COUNT_HW_CACHE_MISSES]        = { 0x48, CNTR_EVEN | CNTR_ODD },
 823         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },
 824         [PERF_COUNT_HW_BRANCH_MISSES]       = { 0x16, CNTR_EVEN | CNTR_ODD },
 825 };
 826
 827 static const struct mips_perf_event loongson3_event_map[PERF_COUNT_HW_MAX] = {
 828         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
 829         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
 830         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
 831         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
 832 };
 833
 834 static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
 835         [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
 836         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
 837         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
 838         [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL  },
 839         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
 840         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
 841         [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
 842 };
 843
 844 static const struct mips_perf_event bmips5000_event_map
 845                                 [PERF_COUNT_HW_MAX] = {
 846         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
 847         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 848         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
 849 };
 850
 851 static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
 852         [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
 853         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
 854         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
 855         [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
 856         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
 857         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
 858 };
 859
 860 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
 861 static const struct mips_perf_event mipsxxcore_cache_map
 862                                 [PERF_COUNT_HW_CACHE_MAX]
 863                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 864                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 865 [C(L1D)] = {
 866         /*
 867          * Like some other architectures (e.g. ARM), the performance
 868          * counters don't differentiate between read and write
 869          * accesses/misses, so this isn't strictly correct, but it's the
 870          * best we can do. Writes and reads get combined.
 871          */
 872         [C(OP_READ)] = {
 873                 [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
 874                 [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
 875         },
 876         [C(OP_WRITE)] = {
 877                 [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
 878                 [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
 879         },
 880 },
 881 [C(L1I)] = {
 882         [C(OP_READ)] = {
 883                 [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
 884                 [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
 885         },
 886         [C(OP_WRITE)] = {
 887                 [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
 888                 [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
 889         },
 890         [C(OP_PREFETCH)] = {
 891                 [C(RESULT_ACCESS)]      = { 0x14, CNTR_EVEN, T },
 892                 /*
 893                  * Note that MIPS has only "hit" events countable for
 894                  * the prefetch operation.
 895                  */
 896         },
 897 },
 898 [C(LL)] = {
 899         [C(OP_READ)] = {
 900                 [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
 901                 [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
 902         },
 903         [C(OP_WRITE)] = {
 904                 [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
 905                 [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
 906         },
 907 },
 908 [C(DTLB)] = {
 909         [C(OP_READ)] = {
 910                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 911                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 912         },
 913         [C(OP_WRITE)] = {
 914                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 915                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 916         },
 917 },
 918 [C(ITLB)] = {
 919         [C(OP_READ)] = {
 920                 [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
 921                 [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
 922         },
 923         [C(OP_WRITE)] = {
 924                 [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
 925                 [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
 926         },
 927 },
 928 [C(BPU)] = {
 929         /* Using the same code for *HW_BRANCH* */
 930         [C(OP_READ)] = {
 931                 [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
 932                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
 933         },
 934         [C(OP_WRITE)] = {
 935                 [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
 936                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
 937         },
 938 },
 939 };
 940
 941 /* 74K/proAptiv core has completely different cache event map. */
 942 static const struct mips_perf_event mipsxxcore_cache_map2
 943                                 [PERF_COUNT_HW_CACHE_MAX]
 944                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 945                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 946 [C(L1D)] = {
 947         /*
 948          * Like some other architectures (e.g. ARM), the performance
 949          * counters don't differentiate between read and write
 950          * accesses/misses, so this isn't strictly correct, but it's the
 951          * best we can do. Writes and reads get combined.
 952          */
 953         [C(OP_READ)] = {
 954                 [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
 955                 [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
 956         },
 957         [C(OP_WRITE)] = {
 958                 [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
 959                 [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
 960         },
 961 },
 962 [C(L1I)] = {
 963         [C(OP_READ)] = {
 964                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 965                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 966         },
 967         [C(OP_WRITE)] = {
 968                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 969                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 970         },
 971         [C(OP_PREFETCH)] = {
 972                 [C(RESULT_ACCESS)]      = { 0x34, CNTR_EVEN, T },
 973                 /*
 974                  * Note that MIPS has only "hit" events countable for
 975                  * the prefetch operation.
 976                  */
 977         },
 978 },
 979 [C(LL)] = {
 980         [C(OP_READ)] = {
 981                 [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
 982                 [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN, P },
 983         },
 984         [C(OP_WRITE)] = {
 985                 [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
 986                 [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN, P },
 987         },
 988 },
 989 /*
 990  * 74K core does not have specific DTLB events. proAptiv core has
 991  * "speculative" DTLB events which are numbered 0x63 (even/odd) and
 992  * not included here. One can use raw events if really needed.
 993  */
 994 [C(ITLB)] = {
 995         [C(OP_READ)] = {
 996                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
 997                 [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
 998         },
 999         [C(OP_WRITE)] = {
1000                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
1001                 [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
1002         },
1003 },
1004 [C(BPU)] = {
1005         /* Using the same code for *HW_BRANCH* */
1006         [C(OP_READ)] = {
1007                 [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
1008                 [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
1009         },
1010         [C(OP_WRITE)] = {
1011                 [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
1012                 [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
1013         },
1014 },
1015 };
1016
1017 static const struct mips_perf_event i6400_cache_map
1018                                 [PERF_COUNT_HW_CACHE_MAX]
1019                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1020                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1021 [C(L1D)] = {
1022         [C(OP_READ)] = {
1023                 [C(RESULT_ACCESS)]      = { 0x46, CNTR_EVEN | CNTR_ODD },
1024                 [C(RESULT_MISS)]        = { 0x49, CNTR_EVEN | CNTR_ODD },
1025         },
1026         [C(OP_WRITE)] = {
1027                 [C(RESULT_ACCESS)]      = { 0x47, CNTR_EVEN | CNTR_ODD },
1028                 [C(RESULT_MISS)]        = { 0x4a, CNTR_EVEN | CNTR_ODD },
1029         },
1030 },
1031 [C(L1I)] = {
1032         [C(OP_READ)] = {
1033                 [C(RESULT_ACCESS)]      = { 0x84, CNTR_EVEN | CNTR_ODD },
1034                 [C(RESULT_MISS)]        = { 0x85, CNTR_EVEN | CNTR_ODD },
1035         },
1036 },
1037 [C(DTLB)] = {
1038         /* Can't distinguish read & write */
1039         [C(OP_READ)] = {
1040                 [C(RESULT_ACCESS)]      = { 0x40, CNTR_EVEN | CNTR_ODD },
1041                 [C(RESULT_MISS)]        = { 0x41, CNTR_EVEN | CNTR_ODD },
1042         },
1043         [C(OP_WRITE)] = {
1044                 [C(RESULT_ACCESS)]      = { 0x40, CNTR_EVEN | CNTR_ODD },
1045                 [C(RESULT_MISS)]        = { 0x41, CNTR_EVEN | CNTR_ODD },
1046         },
1047 },
1048 [C(BPU)] = {
1049         /* Conditional branches / mispredicted */
1050         [C(OP_READ)] = {
1051                 [C(RESULT_ACCESS)]      = { 0x15, CNTR_EVEN | CNTR_ODD },
1052                 [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN | CNTR_ODD },
1053         },
1054 },
1055 };
1056
1057 static const struct mips_perf_event loongson3_cache_map
1058                                 [PERF_COUNT_HW_CACHE_MAX]
1059                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1060                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1061 [C(L1D)] = {
1062         /*
1063          * Like some other architectures (e.g. ARM), the performance
1064          * counters don't differentiate between read and write
1065          * accesses/misses, so this isn't strictly correct, but it's the
1066          * best we can do. Writes and reads get combined.
1067          */
1068         [C(OP_READ)] = {
1069                 [C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
1070         },
1071         [C(OP_WRITE)] = {
1072                 [C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
1073         },
1074 },
1075 [C(L1I)] = {
1076         [C(OP_READ)] = {
1077                 [C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1078         },
1079         [C(OP_WRITE)] = {
1080                 [C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1081         },
1082 },
1083 [C(DTLB)] = {
1084         [C(OP_READ)] = {
1085                 [C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
1086         },
1087         [C(OP_WRITE)] = {
1088                 [C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
1089         },
1090 },
1091 [C(ITLB)] = {
1092         [C(OP_READ)] = {
1093                 [C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
1094         },
1095         [C(OP_WRITE)] = {
1096                 [C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
1097         },
1098 },
1099 [C(BPU)] = {
1100         /* Using the same code for *HW_BRANCH* */
1101         [C(OP_READ)] = {
1102                 [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN },
1103                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD },
1104         },
1105         [C(OP_WRITE)] = {
1106                 [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN },
1107                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD },
1108         },
1109 },
1110 };
1111
1112 /* BMIPS5000 */
1113 static const struct mips_perf_event bmips5000_cache_map
1114                                 [PERF_COUNT_HW_CACHE_MAX]
1115                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1116                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1117 [C(L1D)] = {
1118         /*
1119          * Like some other architectures (e.g. ARM), the performance
1120          * counters don't differentiate between read and write
1121          * accesses/misses, so this isn't strictly correct, but it's the
1122          * best we can do. Writes and reads get combined.
1123          */
1124         [C(OP_READ)] = {
1125                 [C(RESULT_ACCESS)]      = { 12, CNTR_EVEN, T },
1126                 [C(RESULT_MISS)]        = { 12, CNTR_ODD, T },
1127         },
1128         [C(OP_WRITE)] = {
1129                 [C(RESULT_ACCESS)]      = { 12, CNTR_EVEN, T },
1130                 [C(RESULT_MISS)]        = { 12, CNTR_ODD, T },
1131         },
1132 },
1133 [C(L1I)] = {
1134         [C(OP_READ)] = {
1135                 [C(RESULT_ACCESS)]      = { 10, CNTR_EVEN, T },
1136                 [C(RESULT_MISS)]        = { 10, CNTR_ODD, T },
1137         },
1138         [C(OP_WRITE)] = {
1139                 [C(RESULT_ACCESS)]      = { 10, CNTR_EVEN, T },
1140                 [C(RESULT_MISS)]        = { 10, CNTR_ODD, T },
1141         },
1142         [C(OP_PREFETCH)] = {
1143                 [C(RESULT_ACCESS)]      = { 23, CNTR_EVEN, T },
1144                 /*
1145                  * Note that MIPS has only "hit" events countable for
1146                  * the prefetch operation.
1147                  */
1148         },
1149 },
1150 [C(LL)] = {
1151         [C(OP_READ)] = {
1152                 [C(RESULT_ACCESS)]      = { 28, CNTR_EVEN, P },
1153                 [C(RESULT_MISS)]        = { 28, CNTR_ODD, P },
1154         },
1155         [C(OP_WRITE)] = {
1156                 [C(RESULT_ACCESS)]      = { 28, CNTR_EVEN, P },
1157                 [C(RESULT_MISS)]        = { 28, CNTR_ODD, P },
1158         },
1159 },
1160 [C(BPU)] = {
1161         /* Using the same code for *HW_BRANCH* */
1162         [C(OP_READ)] = {
1163                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
1164         },
1165         [C(OP_WRITE)] = {
1166                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
1167         },
1168 },
1169 };
1170
1171
1172 static const struct mips_perf_event octeon_cache_map
1173                                 [PERF_COUNT_HW_CACHE_MAX]
1174                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1175                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1176 [C(L1D)] = {
1177         [C(OP_READ)] = {
1178                 [C(RESULT_ACCESS)]      = { 0x2b, CNTR_ALL },
1179                 [C(RESULT_MISS)]        = { 0x2e, CNTR_ALL },
1180         },
1181         [C(OP_WRITE)] = {
1182                 [C(RESULT_ACCESS)]      = { 0x30, CNTR_ALL },
1183         },
1184 },
1185 [C(L1I)] = {
1186         [C(OP_READ)] = {
1187                 [C(RESULT_ACCESS)]      = { 0x18, CNTR_ALL },
1188         },
1189         [C(OP_PREFETCH)] = {
1190                 [C(RESULT_ACCESS)]      = { 0x19, CNTR_ALL },
1191         },
1192 },
1193 [C(DTLB)] = {
1194         /*
1195          * Only general DTLB misses are counted use the same event for
1196          * read and write.
1197          */
1198         [C(OP_READ)] = {
1199                 [C(RESULT_MISS)]        = { 0x35, CNTR_ALL },
1200         },
1201         [C(OP_WRITE)] = {
1202                 [C(RESULT_MISS)]        = { 0x35, CNTR_ALL },
1203         },
1204 },
1205 [C(ITLB)] = {
1206         [C(OP_READ)] = {
1207                 [C(RESULT_MISS)]        = { 0x37, CNTR_ALL },
1208         },
1209 },
1210 };
1211
1212 static const struct mips_perf_event xlp_cache_map
1213                                 [PERF_COUNT_HW_CACHE_MAX]
1214                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1215                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1216 [C(L1D)] = {
1217         [C(OP_READ)] = {
1218                 [C(RESULT_ACCESS)]      = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1219                 [C(RESULT_MISS)]        = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1220         },
1221         [C(OP_WRITE)] = {
1222                 [C(RESULT_ACCESS)]      = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1223                 [C(RESULT_MISS)]        = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1224         },
1225 },
1226 [C(L1I)] = {
1227         [C(OP_READ)] = {
1228                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1229                 [C(RESULT_MISS)]        = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1230         },
1231 },
1232 [C(LL)] = {
1233         [C(OP_READ)] = {
1234                 [C(RESULT_ACCESS)]      = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1235                 [C(RESULT_MISS)]        = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1236         },
1237         [C(OP_WRITE)] = {
1238                 [C(RESULT_ACCESS)]      = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1239                 [C(RESULT_MISS)]        = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1240         },
1241 },
1242 [C(DTLB)] = {
1243         /*
1244          * Only general DTLB misses are counted use the same event for
1245          * read and write.
1246          */
1247         [C(OP_READ)] = {
1248                 [C(RESULT_MISS)]        = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1249         },
1250         [C(OP_WRITE)] = {
1251                 [C(RESULT_MISS)]        = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1252         },
1253 },
1254 [C(ITLB)] = {
1255         [C(OP_READ)] = {
1256                 [C(RESULT_MISS)]        = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1257         },
1258         [C(OP_WRITE)] = {
1259                 [C(RESULT_MISS)]        = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1260         },
1261 },
1262 [C(BPU)] = {
1263         [C(OP_READ)] = {
1264                 [C(RESULT_MISS)]        = { 0x25, CNTR_ALL },
1265         },
1266 },
1267 };
1268
1269 #ifdef CONFIG_MIPS_MT_SMP
1270 static void check_and_calc_range(struct perf_event *event,
1271                                  const struct mips_perf_event *pev)
1272 {
1273         struct hw_perf_event *hwc = &event->hw;
1274
1275         if (event->cpu >= 0) {
1276                 if (pev->range > V) {
1277                         /*
1278                          * The user selected an event that is processor
1279                          * wide, while expecting it to be VPE wide.
1280                          */
1281                         hwc->config_base |= M_TC_EN_ALL;
1282                 } else {
1283                         /*
1284                          * FIXME: cpu_data[event->cpu].vpe_id reports 0
1285                          * for both CPUs.
1286                          */
1287                         hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
1288                         hwc->config_base |= M_TC_EN_VPE;
1289                 }
1290         } else
1291                 hwc->config_base |= M_TC_EN_ALL;
1292 }
1293 #else
1294 static void check_and_calc_range(struct perf_event *event,
1295                                  const struct mips_perf_event *pev)
1296 {
1297 }
1298 #endif
1299
1300 static int __hw_perf_event_init(struct perf_event *event)
1301 {
1302         struct perf_event_attr *attr = &event->attr;
1303         struct hw_perf_event *hwc = &event->hw;
1304         const struct mips_perf_event *pev;
1305         int err;
1306
1307         /* Returning MIPS event descriptor for generic perf event. */
1308         if (PERF_TYPE_HARDWARE == event->attr.type) {
1309                 if (event->attr.config >= PERF_COUNT_HW_MAX)
1310                         return -EINVAL;
1311                 pev = mipspmu_map_general_event(event->attr.config);
1312         } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1313                 pev = mipspmu_map_cache_event(event->attr.config);
1314         } else if (PERF_TYPE_RAW == event->attr.type) {
1315                 /* We are working on the global raw event. */
1316                 mutex_lock(&raw_event_mutex);
1317                 pev = mipspmu.map_raw_event(event->attr.config);
1318         } else {
1319                 /* The event type is not (yet) supported. */
1320                 return -EOPNOTSUPP;
1321         }
1322
1323         if (IS_ERR(pev)) {
1324                 if (PERF_TYPE_RAW == event->attr.type)
1325                         mutex_unlock(&raw_event_mutex);
1326                 return PTR_ERR(pev);
1327         }
1328
1329         /*
1330          * We allow max flexibility on how each individual counter shared
1331          * by the single CPU operates (the mode exclusion and the range).
1332          */
1333         hwc->config_base = MIPS_PERFCTRL_IE;
1334
1335         /* Calculate range bits and validate it. */
1336         if (num_possible_cpus() > 1)
1337                 check_and_calc_range(event, pev);
1338
1339         hwc->event_base = mipspmu_perf_event_encode(pev);
1340         if (PERF_TYPE_RAW == event->attr.type)
1341                 mutex_unlock(&raw_event_mutex);
1342
1343         if (!attr->exclude_user)
1344                 hwc->config_base |= MIPS_PERFCTRL_U;
1345         if (!attr->exclude_kernel) {
1346                 hwc->config_base |= MIPS_PERFCTRL_K;
1347                 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1348                 hwc->config_base |= MIPS_PERFCTRL_EXL;
1349         }
1350         if (!attr->exclude_hv)
1351                 hwc->config_base |= MIPS_PERFCTRL_S;
1352
1353         hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1354         /*
1355          * The event can belong to another cpu. We do not assign a local
1356          * counter for it for now.
1357          */
1358         hwc->idx = -1;
1359         hwc->config = 0;
1360
1361         if (!hwc->sample_period) {
1362                 hwc->sample_period  = mipspmu.max_period;
1363                 hwc->last_period    = hwc->sample_period;
1364                 local64_set(&hwc->period_left, hwc->sample_period);
1365         }
1366
1367         err = 0;
1368         if (event->group_leader != event)
1369                 err = validate_group(event);
1370
1371         event->destroy = hw_perf_event_destroy;
1372
1373         if (err)
1374                 event->destroy(event);
1375
1376         return err;
1377 }
1378
1379 static void pause_local_counters(void)
1380 {
1381         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1382         int ctr = mipspmu.num_counters;
1383         unsigned long flags;
1384
1385         local_irq_save(flags);
1386         do {
1387                 ctr--;
1388                 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1389                 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1390                                          ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1391         } while (ctr > 0);
1392         local_irq_restore(flags);
1393 }
1394
1395 static void resume_local_counters(void)
1396 {
1397         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1398         int ctr = mipspmu.num_counters;
1399
1400         do {
1401                 ctr--;
1402                 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1403         } while (ctr > 0);
1404 }
1405
1406 static int mipsxx_pmu_handle_shared_irq(void)
1407 {
1408         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1409         struct perf_sample_data data;
1410         unsigned int counters = mipspmu.num_counters;
1411         u64 counter;
1412         int handled = IRQ_NONE;
1413         struct pt_regs *regs;
1414
1415         if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
1416                 return handled;
1417         /*
1418          * First we pause the local counters, so that when we are locked
1419          * here, the counters are all paused. When it gets locked due to
1420          * perf_disable(), the timer interrupt handler will be delayed.
1421          *
1422          * See also mipsxx_pmu_start().
1423          */
1424         pause_local_counters();
1425 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1426         read_lock(&pmuint_rwlock);
1427 #endif
1428
1429         regs = get_irq_regs();
1430
1431         perf_sample_data_init(&data, 0, 0);
1432
1433         switch (counters) {
1434 #define HANDLE_COUNTER(n)                                               \
1435         case n + 1:                                                     \
1436                 if (test_bit(n, cpuc->used_mask)) {                     \
1437                         counter = mipspmu.read_counter(n);              \
1438                         if (counter & mipspmu.overflow) {               \
1439                                 handle_associated_event(cpuc, n, &data, regs); \
1440                                 handled = IRQ_HANDLED;                  \
1441                         }                                               \
1442                 }
1443         HANDLE_COUNTER(3)
1444         HANDLE_COUNTER(2)
1445         HANDLE_COUNTER(1)
1446         HANDLE_COUNTER(0)
1447         }
1448
1449 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1450         read_unlock(&pmuint_rwlock);
1451 #endif
1452         resume_local_counters();
1453
1454         /*
1455          * Do all the work for the pending perf events. We can do this
1456          * in here because the performance counter interrupt is a regular
1457          * interrupt, not NMI.
1458          */
1459         if (handled == IRQ_HANDLED)
1460                 irq_work_run();
1461
1462         return handled;
1463 }
1464
1465 static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1466 {
1467         return mipsxx_pmu_handle_shared_irq();
1468 }
1469
1470 /* 24K */
1471 #define IS_BOTH_COUNTERS_24K_EVENT(b)                                   \
1472         ((b) == 0 || (b) == 1 || (b) == 11)
1473
1474 /* 34K */
1475 #define IS_BOTH_COUNTERS_34K_EVENT(b)                                   \
1476         ((b) == 0 || (b) == 1 || (b) == 11)
1477 #ifdef CONFIG_MIPS_MT_SMP
1478 #define IS_RANGE_P_34K_EVENT(r, b)                                      \
1479         ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
1480          (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 ||           \
1481          (r) == 176 || ((b) >= 50 && (b) <= 55) ||                      \
1482          ((b) >= 64 && (b) <= 67))
1483 #define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1484 #endif
1485
1486 /* 74K */
1487 #define IS_BOTH_COUNTERS_74K_EVENT(b)                                   \
1488         ((b) == 0 || (b) == 1)
1489
1490 /* proAptiv */
1491 #define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b)                              \
1492         ((b) == 0 || (b) == 1)
1493 /* P5600 */
1494 #define IS_BOTH_COUNTERS_P5600_EVENT(b)                                 \
1495         ((b) == 0 || (b) == 1)
1496
1497 /* 1004K */
1498 #define IS_BOTH_COUNTERS_1004K_EVENT(b)                                 \
1499         ((b) == 0 || (b) == 1 || (b) == 11)
1500 #ifdef CONFIG_MIPS_MT_SMP
1501 #define IS_RANGE_P_1004K_EVENT(r, b)                                    \
1502         ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
1503          (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 ||            \
1504          (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) ||        \
1505          (r) == 188 || (b) == 61 || (b) == 62 ||                        \
1506          ((b) >= 64 && (b) <= 67))
1507 #define IS_RANGE_V_1004K_EVENT(r)       ((r) == 47)
1508 #endif
1509
1510 /* interAptiv */
1511 #define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b)                            \
1512         ((b) == 0 || (b) == 1 || (b) == 11)
1513 #ifdef CONFIG_MIPS_MT_SMP
1514 /* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
1515 #define IS_RANGE_P_INTERAPTIV_EVENT(r, b)                               \
1516         ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
1517          (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 ||            \
1518          (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 &&         \
1519          (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 ||          \
1520          ((b) >= 64 && (b) <= 67))
1521 #define IS_RANGE_V_INTERAPTIV_EVENT(r)  ((r) == 47 || (r) == 175)
1522 #endif
1523
1524 /* BMIPS5000 */
1525 #define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b)                             \
1526         ((b) == 0 || (b) == 1)
1527
1528
1529 /*
1530  * For most cores the user can use 0-255 raw events, where 0-127 for the events
1531  * of even counters, and 128-255 for odd counters. Note that bit 7 is used to
1532  * indicate the even/odd bank selector. So, for example, when user wants to take
1533  * the Event Num of 15 for odd counters (by referring to the user manual), then
1534  * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F)
1535  * to be used.
1536  *
1537  * Some newer cores have even more events, in which case the user can use raw
1538  * events 0-511, where 0-255 are for the events of even counters, and 256-511
1539  * are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
1540  */
1541 static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1542 {
1543         /* currently most cores have 7-bit event numbers */
1544         unsigned int raw_id = config & 0xff;
1545         unsigned int base_id = raw_id & 0x7f;
1546
1547         switch (current_cpu_type()) {
1548         case CPU_24K:
1549                 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1550                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1551                 else
1552                         raw_event.cntr_mask =
1553                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1554 #ifdef CONFIG_MIPS_MT_SMP
1555                 /*
1556                  * This is actually doing nothing. Non-multithreading
1557                  * CPUs will not check and calculate the range.
1558                  */
1559                 raw_event.range = P;
1560 #endif
1561                 break;
1562         case CPU_34K:
1563                 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1564                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1565                 else
1566                         raw_event.cntr_mask =
1567                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1568 #ifdef CONFIG_MIPS_MT_SMP
1569                 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1570                         raw_event.range = P;
1571                 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1572                         raw_event.range = V;
1573                 else
1574                         raw_event.range = T;
1575 #endif
1576                 break;
1577         case CPU_74K:
1578         case CPU_1074K:
1579                 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1580                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1581                 else
1582                         raw_event.cntr_mask =
1583                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1584 #ifdef CONFIG_MIPS_MT_SMP
1585                 raw_event.range = P;
1586 #endif
1587                 break;
1588         case CPU_PROAPTIV:
1589                 if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id))
1590                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1591                 else
1592                         raw_event.cntr_mask =
1593                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1594 #ifdef CONFIG_MIPS_MT_SMP
1595                 raw_event.range = P;
1596 #endif
1597                 break;
1598         case CPU_P5600:
1599         case CPU_P6600:
1600                 /* 8-bit event numbers */
1601                 raw_id = config & 0x1ff;
1602                 base_id = raw_id & 0xff;
1603                 if (IS_BOTH_COUNTERS_P5600_EVENT(base_id))
1604                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1605                 else
1606                         raw_event.cntr_mask =
1607                                 raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
1608 #ifdef CONFIG_MIPS_MT_SMP
1609                 raw_event.range = P;
1610 #endif
1611                 break;
1612         case CPU_I6400:
1613                 /* 8-bit event numbers */
1614                 base_id = config & 0xff;
1615                 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1616                 break;
1617         case CPU_1004K:
1618                 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1619                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1620                 else
1621                         raw_event.cntr_mask =
1622                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1623 #ifdef CONFIG_MIPS_MT_SMP
1624                 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1625                         raw_event.range = P;
1626                 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1627                         raw_event.range = V;
1628                 else
1629                         raw_event.range = T;
1630 #endif
1631                 break;
1632         case CPU_INTERAPTIV:
1633                 if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
1634                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1635                 else
1636                         raw_event.cntr_mask =
1637                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1638 #ifdef CONFIG_MIPS_MT_SMP
1639                 if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
1640                         raw_event.range = P;
1641                 else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
1642                         raw_event.range = V;
1643                 else
1644                         raw_event.range = T;
1645 #endif
1646                 break;
1647         case CPU_BMIPS5000:
1648                 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
1649                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1650                 else
1651                         raw_event.cntr_mask =
1652                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1653                 break;
1654         case CPU_LOONGSON3:
1655                 raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1656         break;
1657         }
1658
1659         raw_event.event_id = base_id;
1660
1661         return &raw_event;
1662 }
1663
1664 static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1665 {
1666         unsigned int raw_id = config & 0xff;
1667         unsigned int base_id = raw_id & 0x7f;
1668
1669
1670         raw_event.cntr_mask = CNTR_ALL;
1671         raw_event.event_id = base_id;
1672
1673         if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
1674                 if (base_id > 0x42)
1675                         return ERR_PTR(-EOPNOTSUPP);
1676         } else {
1677                 if (base_id > 0x3a)
1678                         return ERR_PTR(-EOPNOTSUPP);
1679         }
1680
1681         switch (base_id) {
1682         case 0x00:
1683         case 0x0f:
1684         case 0x1e:
1685         case 0x1f:
1686         case 0x2f:
1687         case 0x34:
1688         case 0x3b ... 0x3f:
1689                 return ERR_PTR(-EOPNOTSUPP);
1690         default:
1691                 break;
1692         }
1693
1694         return &raw_event;
1695 }
1696
1697 static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
1698 {
1699         unsigned int raw_id = config & 0xff;
1700
1701         /* Only 1-63 are defined */
1702         if ((raw_id < 0x01) || (raw_id > 0x3f))
1703                 return ERR_PTR(-EOPNOTSUPP);
1704
1705         raw_event.cntr_mask = CNTR_ALL;
1706         raw_event.event_id = raw_id;
1707
1708         return &raw_event;
1709 }
1710
1711 static int __init
1712 init_hw_perf_events(void)
1713 {
1714         int counters, irq;
1715         int counter_bits;
1716
1717         pr_info("Performance counters: ");
1718
1719         counters = n_counters();
1720         if (counters == 0) {
1721                 pr_cont("No available PMU.\n");
1722                 return -ENODEV;
1723         }
1724
1725 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1726         cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
1727         if (!cpu_has_mipsmt_pertccounters)
1728                 counters = counters_total_to_per_cpu(counters);
1729 #endif
1730
1731         if (get_c0_perfcount_int)
1732                 irq = get_c0_perfcount_int();
1733         else if (cp0_perfcount_irq >= 0)
1734                 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1735         else
1736                 irq = -1;
1737
1738         mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1739
1740         switch (current_cpu_type()) {
1741         case CPU_24K:
1742                 mipspmu.name = "mips/24K";
1743                 mipspmu.general_event_map = &mipsxxcore_event_map;
1744                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1745                 break;
1746         case CPU_34K:
1747                 mipspmu.name = "mips/34K";
1748                 mipspmu.general_event_map = &mipsxxcore_event_map;
1749                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1750                 break;
1751         case CPU_74K:
1752                 mipspmu.name = "mips/74K";
1753                 mipspmu.general_event_map = &mipsxxcore_event_map2;
1754                 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1755                 break;
1756         case CPU_PROAPTIV:
1757                 mipspmu.name = "mips/proAptiv";
1758                 mipspmu.general_event_map = &mipsxxcore_event_map2;
1759                 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1760                 break;
1761         case CPU_P5600:
1762                 mipspmu.name = "mips/P5600";
1763                 mipspmu.general_event_map = &mipsxxcore_event_map2;
1764                 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1765                 break;
1766         case CPU_P6600:
1767                 mipspmu.name = "mips/P6600";
1768                 mipspmu.general_event_map = &mipsxxcore_event_map2;
1769                 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1770                 break;
1771         case CPU_I6400:
1772                 mipspmu.name = "mips/I6400";
1773                 mipspmu.general_event_map = &i6400_event_map;
1774                 mipspmu.cache_event_map = &i6400_cache_map;
1775                 break;
1776         case CPU_1004K:
1777                 mipspmu.name = "mips/1004K";
1778                 mipspmu.general_event_map = &mipsxxcore_event_map;
1779                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1780                 break;
1781         case CPU_1074K:
1782                 mipspmu.name = "mips/1074K";
1783                 mipspmu.general_event_map = &mipsxxcore_event_map;
1784                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1785                 break;
1786         case CPU_INTERAPTIV:
1787                 mipspmu.name = "mips/interAptiv";
1788                 mipspmu.general_event_map = &mipsxxcore_event_map;
1789                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1790                 break;
1791         case CPU_LOONGSON1:
1792                 mipspmu.name = "mips/loongson1";
1793                 mipspmu.general_event_map = &mipsxxcore_event_map;
1794                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1795                 break;
1796         case CPU_LOONGSON3:
1797                 mipspmu.name = "mips/loongson3";
1798                 mipspmu.general_event_map = &loongson3_event_map;
1799                 mipspmu.cache_event_map = &loongson3_cache_map;
1800                 break;
1801         case CPU_CAVIUM_OCTEON:
1802         case CPU_CAVIUM_OCTEON_PLUS:
1803         case CPU_CAVIUM_OCTEON2:
1804                 mipspmu.name = "octeon";
1805                 mipspmu.general_event_map = &octeon_event_map;
1806                 mipspmu.cache_event_map = &octeon_cache_map;
1807                 mipspmu.map_raw_event = octeon_pmu_map_raw_event;
1808                 break;
1809         case CPU_BMIPS5000:
1810                 mipspmu.name = "BMIPS5000";
1811                 mipspmu.general_event_map = &bmips5000_event_map;
1812                 mipspmu.cache_event_map = &bmips5000_cache_map;
1813                 break;
1814         case CPU_XLP:
1815                 mipspmu.name = "xlp";
1816                 mipspmu.general_event_map = &xlp_event_map;
1817                 mipspmu.cache_event_map = &xlp_cache_map;
1818                 mipspmu.map_raw_event = xlp_pmu_map_raw_event;
1819                 break;
1820         default:
1821                 pr_cont("Either hardware does not support performance "
1822                         "counters, or not yet implemented.\n");
1823                 return -ENODEV;
1824         }
1825
1826         mipspmu.num_counters = counters;
1827         mipspmu.irq = irq;
1828
1829         if (read_c0_perfctrl0() & MIPS_PERFCTRL_W) {
1830                 mipspmu.max_period = (1ULL << 63) - 1;
1831                 mipspmu.valid_count = (1ULL << 63) - 1;
1832                 mipspmu.overflow = 1ULL << 63;
1833                 mipspmu.read_counter = mipsxx_pmu_read_counter_64;
1834                 mipspmu.write_counter = mipsxx_pmu_write_counter_64;
1835                 counter_bits = 64;
1836         } else {
1837                 mipspmu.max_period = (1ULL << 31) - 1;
1838                 mipspmu.valid_count = (1ULL << 31) - 1;
1839                 mipspmu.overflow = 1ULL << 31;
1840                 mipspmu.read_counter = mipsxx_pmu_read_counter;
1841                 mipspmu.write_counter = mipsxx_pmu_write_counter;
1842                 counter_bits = 32;
1843         }
1844
1845         on_each_cpu(reset_counters, (void *)(long)counters, 1);
1846
1847         pr_cont("%s PMU enabled, %d %d-bit counters available to each "
1848                 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
1849                 irq < 0 ? " (share with timer interrupt)" : "");
1850
1851         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1852
1853         return 0;
1854 }
1855 early_initcall(init_hw_perf_events);